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2024-04-15ARM: dts: sun5i: Add PocketBook 614 Plus supportDenis Burkov2-0/+219
What works: - Serial console - mmc0, mmc2 (both microSD card slots on the board) - All buttons (gpio and lradc based) - Power LED - PMIC - RTC - USB OTG/gadgets mode Signed-off-by: Denis Burkov <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2024-04-15ARM: configs: sunxi: Enable DRM_DW_HDMIMaxime Ripard1-0/+1
Commit 4fc8cb47fcfd ("drm/display: Move HDMI helpers into display-helper module") turned the DRM_DW_HDMI dependency of DRM_SUN8I_DW_HDMI into a depends on which ended up disabling the driver in the defconfig. Make sure it's still enabled. Fixes: 4fc8cb47fcfd ("drm/display: Move HDMI helpers into display-helper module") Reported-by: Mark Brown <[email protected]> Reported-by: Alexander Stein <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2024-04-15arm64: dts: allwinner: h616: Fix I2C0 pinsAndre Przywara1-1/+1
Currently we specify the pins for the I2C0 function as PI6 and PI7, even though they are actually PI5 and PI6. Linux' pinctrl driver and the H616 user manual confirm this. Fix the pin names in the pins property. None of the existing DTs in the tree seems to use I2C0, which explains why this went unnoticed. Fixes: 0d17c8651188 ("arm64: dts: allwinner: Add Allwinner H616 .dtsi file") Signed-off-by: Andre Przywara <[email protected]> Acked-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2024-04-15arm64: dts: allwinner: a64: Run GPU at 432 MHzFrank Oltmanns1-8/+0
The Allwinner A64's GPU has currently three operating points. However, the BSP runs the GPU fixed at 432 MHz. In addition, at least one of the devices using that SoC - the pinephone - shows unstabilities (see link) that can be circumvented by running the GPU at a fixed rate. Therefore, remove the other two operating points from the GPU OPP table, so that the GPU runs at a fixed rate of 432 MHz. Link: https://gitlab.com/postmarketOS/pmaports/-/issues/805 Acked-by: Erico Nunes <[email protected]> Signed-off-by: Frank Oltmanns <[email protected]> Acked-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2024-04-15arm: dts: allwinner: drop underscore in node namesKrzysztof Kozlowski49-86/+86
Underscores should not be used in node names (dtc with W=2 warns about them), so replace them with hyphens. Use also generic name for pwrseq node, because generic naming is favored by Devicetree spec. All the clocks affected by this change use clock-output-names, so resulting clock name should not change. Functional impact checked with comparing before/after DTBs with dtx_diff and fdtdump. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2024-04-15arm64: dts: allwinner: Orange Pi: delete node by phandleKrzysztof Kozlowski1-1/+2
Delete node via phandle, not via full node path, to avoid easy mistakes - if original node name changes, such deletion would be ineffective and not reported by the dtc as error. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2024-04-15arm64: dts: allwinner: drop underscore in node namesKrzysztof Kozlowski22-27/+27
Underscores should not be used in node names (dtc with W=2 warns about them), so replace them with hyphens. Use also generic name for pwrseq node, because generic naming is favored by Devicetree spec. All the clocks affected by this change use clock-output-names, so resulting clock name should not change. Functional impact checked with comparing before/after DTBs with dtx_diff and fdtdump. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2024-04-15arm64: dts: allwinner: Pine H64: correctly remove reg_gmac_3v3Krzysztof Kozlowski1-2/+2
There is no "reg_gmac_3v3" device node in sun50i-h6-pine-h64.dts, although there is "gmac-3v3" with "reg_gmac_3v3" label, so let's assume author wanted to remove that node. Delete node via phandle, not via full node path, to fix this. Fixes: f33a91175029 ("arm64: dts: allwinner: add pineh64 model B") Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2024-04-15arm64: dts: allwinner: pinephone: add multicolor LED nodeAren Moynihan1-3/+10
The red, green, and blue LEDs currently in the device tree represent a single RGB LED on the front of the PinePhone. Signed-off-by: Aren Moynihan <[email protected]> Acked-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2024-04-15arm64: dts: allwinner: pinephone: Retain LEDs state in suspendMiles Alan1-0/+3
Allows user to set a LED before entering suspend to know that the phone is still on (or could be used for notifications etc). Signed-off-by: Miles Alan <[email protected]> Signed-off-by: Ondrej Jirman <[email protected]> Signed-off-by: Aren Moynihan <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2024-04-15Replace macro "ARCH_HAVE_EXTRA_ELF_NOTES" with kconfigVignesh Balasubramanian3-2/+10
"ARCH_HAVE_EXTRA_ELF_NOTES" enables an extra note section in the core dump. Kconfig variable is preferred over ARCH_HAVE_* macro. Co-developed-by: Jini Susan George <[email protected]> Signed-off-by: Jini Susan George <[email protected]> Signed-off-by: Vignesh Balasubramanian <[email protected]> Acked-by: Michael Ellerman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kees Cook <[email protected]>
2024-04-15arm64/hugetlb: Fix page table walk in huge_pte_alloc()Anshuman Khandual1-1/+4
Currently normal HugeTLB fault ends up crashing the kernel, as p4dp derived from p4d_offset() is an invalid address when PGTABLE_LEVEL = 5. A p4d level entry needs to be allocated when not available while walking the page table during HugeTLB faults. Let's call p4d_alloc() to allocate such entries when required instead of current p4d_offset(). Unable to handle kernel paging request at virtual address ffffffff80000000 Mem abort info: ESR = 0x0000000096000005 EC = 0x25: DABT (current EL), IL = 32 bits SET = 0, FnV = 0 EA = 0, S1PTW = 0 FSC = 0x05: level 1 translation fault Data abort info: ISV = 0, ISS = 0x00000005, ISS2 = 0x00000000 CM = 0, WnR = 0, TnD = 0, TagAccess = 0 GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0 swapper pgtable: 4k pages, 52-bit VAs, pgdp=0000000081da9000 [ffffffff80000000] pgd=1000000082cec003, p4d=0000000082c32003, pud=0000000000000000 Internal error: Oops: 0000000096000005 [#1] PREEMPT SMP Modules linked in: CPU: 1 PID: 108 Comm: high_addr_hugep Not tainted 6.9.0-rc4 #48 Hardware name: Foundation-v8A (DT) pstate: 01402005 (nzcv daif +PAN -UAO -TCO +DIT -SSBS BTYPE=--) pc : huge_pte_alloc+0xd4/0x334 lr : hugetlb_fault+0x1b8/0xc68 sp : ffff8000833bbc20 x29: ffff8000833bbc20 x28: fff000080080cb58 x27: ffff800082a7cc58 x26: 0000000000000000 x25: fff0000800378e40 x24: fff00008008d6c60 x23: 00000000de9dbf07 x22: fff0000800378e40 x21: 0004000000000000 x20: 0004000000000000 x19: ffffffff80000000 x18: 1ffe00010011d7a1 x17: 0000000000000001 x16: ffffffffffffffff x15: 0000000000000001 x14: 0000000000000000 x13: ffff8000816120d0 x12: ffffffffffffffff x11: 0000000000000000 x10: fff00008008ebd0c x9 : 0004000000000000 x8 : 0000000000001255 x7 : fff00008003e2000 x6 : 00000000061d54b0 x5 : 0000000000001000 x4 : ffffffff80000000 x3 : 0000000000200000 x2 : 0000000000000004 x1 : 0000000080000000 x0 : 0000000000000000 Call trace: huge_pte_alloc+0xd4/0x334 hugetlb_fault+0x1b8/0xc68 handle_mm_fault+0x260/0x29c do_page_fault+0xfc/0x47c do_translation_fault+0x68/0x74 do_mem_abort+0x44/0x94 el0_da+0x2c/0x9c el0t_64_sync_handler+0x70/0xc4 el0t_64_sync+0x190/0x194 Code: aa000084 cb010084 b24c2c84 8b130c93 (f9400260) ---[ end trace 0000000000000000 ]--- Cc: Will Deacon <[email protected]> Cc: Ard Biesheuvel <[email protected]> Cc: Ryan Roberts <[email protected]> Cc: Mark Rutland <[email protected]> Cc: [email protected] Cc: [email protected] Fixes: a6bbf5d4d9d1 ("arm64: mm: Add definitions to support 5 levels of paging") Reported-by: Dev Jain <[email protected]> Acked-by: Ard Biesheuvel <[email protected]> Acked-by: Mark Rutland <[email protected]> Signed-off-by: Anshuman Khandual <[email protected]> Reviewed-by: Ryan Roberts <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Catalin Marinas <[email protected]>
2024-04-15riscv: dts: starfive: visionfive 2: Remove non-existing I2S hardwareHannah Peuckmann1-58/+0
This partially reverts commit 92cfc35838b2 ("riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1") This added device tree nodes for I2S hardware that is not actually on the VisionFive 2 board, but connected on the 40pin header. Many different extension boards could be added on those pins, so this should be handled by overlays instead. This also conflicts with the TDM node which also attempts to grab GPIO 44: starfive-jh7110-sys-pinctrl 13040000.pinctrl: pin GPIO44 already requested by 10090000.tdm; cannot claim for 120c0000.i2s Fixes: 92cfc35838b2 ("riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1") Signed-off-by: Hannah Peuckmann <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Tested-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-15riscv: dts: starfive: visionfive 2: Remove non-existing TDM hardwareHannah Peuckmann1-40/+0
This partially reverts commit e7c304c0346d ("riscv: dts: starfive: jh7110: add the node and pins configuration for tdm") This added device tree nodes for TDM hardware that is not actually on the VisionFive 2 board, but connected on the 40pin header. Many different extension boards could be added on those pins, so this should be handled by overlays instead. This also conflicts with the I2S node which also attempts to grab GPIO 44: starfive-jh7110-sys-pinctrl 13040000.pinctrl: pin GPIO44 already requested by 10090000.tdm; cannot claim for 120c0000.i2s Fixes: e7c304c0346d ("riscv: dts: starfive: jh7110: add the node and pins configuration for tdm") Signed-off-by: Hannah Peuckmann <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Tested-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-15openrisc: Move FPU state out of pt_regsStafford Horne8-32/+76
My original, naive, FPU support patch had the FPCSR register stored during both the *mode switch* and *context switch*. This is wasteful. Also, the original patches did not save the FPU state when handling signals during the system call fast path. We fix this by moving the FPCSR state to thread_struct in task_struct. We also introduce new helper functions save_fpu and restore_fpu which can be used to sync the FPU with thread_struct. These functions are now called when needed: - Setting up and restoring sigcontext when handling signals - Before and after __switch_to during context switches - When handling FPU exceptions - When reading and writing FPU register sets In the future we can further optimize this by doing lazy FPU save and restore. For example, FPU sync is not needed when switching to and from kernel threads (x86 does this). FPU save and restore does not need to be done two times if we have both rescheduling and signal work to do. However, since OpenRISC FPU state is a single register, I leave these optimizations for future consideration. Signed-off-by: Stafford Horne <[email protected]>
2024-04-15openrisc: Add FPU configStafford Horne3-1/+17
Allow disabling FPU related code sequences to save space. Signed-off-by: Stafford Horne <[email protected]>
2024-04-15openrisc: traps: Don't send signals to kernel mode threadsStafford Horne1-19/+29
OpenRISC exception handling sends signals to user processes on floating point exceptions and trap instructions (for debugging) among others. There is a bug where the trap handling logic may send signals to kernel threads, we should not send these signals to kernel threads, if that happens we treat it as an error. This patch adds conditions to die if the kernel receives these exceptions in kernel mode code. Fixes: 27267655c531 ("openrisc: Support floating point user api") Signed-off-by: Stafford Horne <[email protected]>
2024-04-15openrisc: traps: Remove calls to show_registers before dieStafford Horne1-3/+0
The die function calls show_registers unconditionally. Remove calls to show_registers before calling die to avoid printing all registers and stack status two times during a crash. This was found when testing kernel trap and floating point exception handling. Signed-off-by: Stafford Horne <[email protected]>
2024-04-15openrisc: traps: Convert printks to pr_<level> macrosStafford Horne1-44/+44
The pr_* macros are the convention and my upcoming patches add even more printk's. Use this opportunity to convert the printks in this file to the pr_* macros to avoid patch check warnings. Signed-off-by: Stafford Horne <[email protected]>
2024-04-15openrisc: Add support for more module relocationsStafford Horne1-0/+10
When testing modules in OpenRISC I found R_OR1K_AHI16 (signed adjusted high 16-bit) and R_OR1K_SLO16 (split low 16-bit) relocations are used in modules but not implemented yet. This patch implements the relocations. I have tested with a few modules. Signed-off-by: Stafford Horne <[email protected]>
2024-04-15openrisc: Define openrisc relocation typesStafford Horne2-13/+70
This defines the current OpenRISC relocation types using the current R_OR1K_* naming conventions. The old R_OR32_* definitions are left for backwards compatibility. Note, the R_OR32_VTENTRY and R_OR32_VTINHERIT macros were defined with the wrong values the have always been 7 and 8 respectively, not 8 and 7. They are not used for module loading and I have updated them to use the correct values. Signed-off-by: Stafford Horne <[email protected]>
2024-04-15openrisc: Use do_kernel_power_off()Stafford Horne1-5/+3
After commit 14c5678720bd ("power: reset: syscon-poweroff: Use devm_register_sys_off_handler(POWER_OFF)") setting up of pm_power_off was removed from the driver, this causes OpenRISC platforms using syscon-poweroff to no longer shutdown. The kernel now supports chained power-off handlers. Use do_kernel_power_off() that invokes chained power-off handlers. All architectures have moved away from using pm_power_off except OpenRISC. This patch migrates openrisc to use do_kernel_power_off() instead of the legacy pm_power_off(). Fixes: 14c5678720bd ("power: reset: syscon-poweroff: Use devm_register_sys_off_handler(POWER_OFF)") Signed-off-by: Stafford Horne <[email protected]> Reviewed-by: Sebastian Reichel <[email protected]>
2024-04-15arm64: dts: renesas: s4sk: Fix ethernet0 aliasGeert Uytterhoeven1-3/+3
U-Boot uses "ethernet0", not "eth0". While at it, fix nearby whitespace errors (TAB instead of space before equal sign). Fixes: 93be50c7ff8e8087 ("arm64: dts: renesas: Add R-Car S4 Starter Kit support") Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/2f62c29e4222387a95ebadc65ba90a0cdea9b78c.1712647914.git.geert+renesas@glider.be
2024-04-15MIPS: SGI-IP27: micro-optimize arch_init_irq()Yury Norov1-5/+2
The function sets adjasted groups of bits in hub_irq_map by using for-loops. There's a bitmap_set() function dedicated to do this. Because [0, CPU_CALL_B_IRQ] and [NI_BRDCAST_ERR_A, MSC_PANIC_INTR] ranges belong to the same machine word, bitmap_set() would boil down to an inline wrapper in both cases, avoiding generating a loop, whth the associate overhead. Signed-off-by: Yury Norov <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15mips: dts: ralink: mt7621: reorder the attributes of the root nodeJustin Swartz1-1/+2
Move the compatible attribute of the DTS root node to first place. Signed-off-by: Justin Swartz <[email protected]> Reviewed-by: Arınç ÜNAL <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15mips: dts: ralink: mt7621: reorder pci?_phy attributesJustin Swartz1-2/+6
Reorder the attributes of the PCIe PHY nodes node to match what the DTS style guide recommends. Signed-off-by: Justin Swartz <[email protected]> Reviewed-by: Arınç ÜNAL <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15mips: dts: ralink: mt7621: reorder pcie node attributes and childrenJustin Swartz1-25/+43
Reorder the attributes and child nodes of the PCIe Controller node to meet the DTS style guidelines. Signed-off-by: Justin Swartz <[email protected]> Reviewed-by: Arınç ÜNAL <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15mips: dts: ralink: mt7621: reorder ethernet node attributes and kidsJustin Swartz1-40/+48
Rearrange attributes and descendents declared under the ethernet node, recursively, to follow the DTS style guide. Signed-off-by: Justin Swartz <[email protected]> Reviewed-by: Arınç ÜNAL <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15mips: dts: ralink: mt7621: reorder gic node attributesJustin Swartz1-2/+2
Reorder the attributes of the Global Interrupt Controller node to fit DTS style guidelines. Signed-off-by: Justin Swartz <[email protected]> Reviewed-by: Arınç ÜNAL <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15mips: dts: ralink: mt7621: reorder mmc node attributesJustin Swartz1-11/+15
Shuffle the attributes of the MMC node to meet the guidelines provided by the DTS style guide. Signed-off-by: Justin Swartz <[email protected]> Reviewed-by: Arınç ÜNAL <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15mips: dts: ralink: mt7621: move pinctrl and sort its childrenJustin Swartz1-86/+86
Move the pinctrl node prior to the nodes that feature unit addresses. Sort pinctrl's child nodes into alphabetical order. Signed-off-by: Justin Swartz <[email protected]> Reviewed-by: Arınç ÜNAL <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15mips: dts: ralink: mt7621: reorder spi0 node attributesJustin Swartz1-8/+8
Reorder the attributes of the SPI controller node so that they're aligned with the DTS style guide. Signed-off-by: Justin Swartz <[email protected]> Reviewed-by: Arınç ÜNAL <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15mips: dts: ralink: mt7621: reorder i2c node attributesJustin Swartz1-6/+7
Rearrange the order of the i2c node's attributes so that they are inline with the DTS style guide. Signed-off-by: Justin Swartz <[email protected]> Reviewed-by: Arınç ÜNAL <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15mips: dts: ralink: mt7621: reorder gpio node attributesJustin Swartz1-2/+5
Shuffle the attributes of the gpio node to appease the DTS style guide. Signed-off-by: Justin Swartz <[email protected]> Reviewed-by: Arınç ÜNAL <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15mips: dts: ralink: mt7621: reorder sysc node attributesJustin Swartz1-1/+4
Reorder the attributes of the sysc node so that the ralink prefixed attribute is placed after those which lack prefixes. Signed-off-by: Justin Swartz <[email protected]> Reviewed-by: Arınç ÜNAL <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15mips: dts: ralink: mt7621: reorder mmc regulator attributesJustin Swartz1-6/+10
Reorder the attributes of MMC fixed voltage regulator nodes for the sake of compliance with the DTS style guide. Signed-off-by: Justin Swartz <[email protected]> Reviewed-by: Arınç ÜNAL <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15mips: dts: ralink: mt7621: reorder cpuintc node attributesJustin Swartz1-1/+3
Reorder the CPU Interrupt Controller node's attributes to follow what the DTS Coding Style dictates. Signed-off-by: Justin Swartz <[email protected]> Reviewed-by: Arınç ÜNAL <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15mips: dts: ralink: mt7621: reorder cpu node attributesJustin Swartz1-2/+2
Reorder cpu node attributes to fit the DTS Coding Style. Signed-off-by: Justin Swartz <[email protected]> Reviewed-by: Arınç ÜNAL <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15MIPS: Add prototypes for plat_post_relocation() and relocate_kernel()Nathan Chancellor1-0/+6
When building malta_defconfig with CONFIG_RELOCATABLE=y, there are two warnings due to missing prototypes for functions only used when that configuration is enabled: arch/mips/kernel/relocate.c:42:12: warning: no previous prototype for 'plat_post_relocation' [-Wmissing-prototypes] 42 | int __weak plat_post_relocation(long offset) | ^~~~~~~~~~~~~~~~~~~~ arch/mips/kernel/relocate.c:324:14: warning: no previous prototype for 'relocate_kernel' [-Wmissing-prototypes] 324 | void *__init relocate_kernel(void) | ^~~~~~~~~~~~~~~ While relocate_kernel() is only called from assembly, it makes sense to keep the prototypes together in C to fix the warnings. Add them to silence the warnings. Signed-off-by: Nathan Chancellor <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15MIPS: Octeon: Add PCIe link status checkSongyang Li1-0/+6
The standard PCIe configuration read-write interface is used to access the configuration space of the peripheral PCIe devices of the mips processor after the PCIe link surprise down, it can generate kernel panic caused by "Data bus error". So it is necessary to add PCIe link status check for system protection. When the PCIe link is down or in training, assigning a value of 0 to the configuration address can prevent read-write behavior to the configuration space of peripheral PCIe devices, thereby preventing kernel panic. Signed-off-by: Songyang Li <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15MIPS: Guard some macros with __ASSEMBLY__ in asm.hJiaxun Yang1-0/+3
There are some assembly macros with very generic naming being defined asm.h. They are clashing with other macros from C code. Guard them with __ASSEMBLY__ to prevent futher clashes. Reported-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/linux-mips/[email protected]/ Signed-off-by: Jiaxun Yang <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15MIPS: RB532: Declare prom_setup_cmdline() and rb532_gpio_init() staticYongzhen Zhang2-2/+2
early_tlb_init() and rb532_gpio_init() were local to file but not declared static, leading to error: arch/mips/rb532/prom.c:49:13: error: no previous prototype for ‘prom_setup_cmdline’ [-Werror=missing-prototypes] 49 | void __init prom_setup_cmdline(void) | ^~~~~~~~~~~~~~~~~~ arch/mips/rb532/gpio.c:200:12: error: no previous prototype for ‘rb532_gpio_init’ [-Werror=missing-prototypes] 200 | int __init rb532_gpio_init(void) | ^~~~~~~~~~~~~~~ Signed-off-by: Yongzhen Zhang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15MIPS: BCM47XX: Declare early_tlb_init() staticYongzhen Zhang1-1/+1
early_tlb_init() was local to file but not declared static, leading to error: arch/mips/bcm47xx/prom.c:126:6: error: no previous prototype for ‘early_tlb_init’ [-Werror=missing-prototypes] 126 | void early_tlb_init(void) | ^~~~~~~~~~~~~~ Signed-off-by: Yongzhen Zhang <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15MIPS: BCM47XX: include header for bcm47xx_prom_highmem_init() prototypeYongzhen Zhang1-0/+1
bcm47xx_prom_highmem_init() is a global function declared in arch/mips/bcm47xx/bcm47xx_private.h, but this header is not included before the definition, causing a error: arch/mips/bcm47xx/prom.c:134:13: error: no previous prototype for ‘bcm47xx_prom_highmem_init’ [-Werror=missing-prototypes] 134 | void __init bcm47xx_prom_highmem_init(void) | ^~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Yongzhen Zhang <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-04-15powerpc: Avoid nmi_enter/nmi_exit in real mode interrupt.Mahesh Salgaonkar3-0/+22
nmi_enter()/nmi_exit() touches per cpu variables which can lead to kernel crash when invoked during real mode interrupt handling (e.g. early HMI/MCE interrupt handler) if percpu allocation comes from vmalloc area. Early HMI/MCE handlers are called through DEFINE_INTERRUPT_HANDLER_NMI() wrapper which invokes nmi_enter/nmi_exit calls. We don't see any issue when percpu allocation is from the embedded first chunk. However with CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK enabled there are chances where percpu allocation can come from the vmalloc area. With kernel command line "percpu_alloc=page" we can force percpu allocation to come from vmalloc area and can see kernel crash in machine_check_early: [ 1.215714] NIP [c000000000e49eb4] rcu_nmi_enter+0x24/0x110 [ 1.215717] LR [c0000000000461a0] machine_check_early+0xf0/0x2c0 [ 1.215719] --- interrupt: 200 [ 1.215720] [c000000fffd73180] [0000000000000000] 0x0 (unreliable) [ 1.215722] [c000000fffd731b0] [0000000000000000] 0x0 [ 1.215724] [c000000fffd73210] [c000000000008364] machine_check_early_common+0x134/0x1f8 Fix this by avoiding use of nmi_enter()/nmi_exit() in real mode if percpu first chunk is not embedded. Reviewed-by: Christophe Leroy <[email protected]> Tested-by: Shirisha Ganta <[email protected]> Signed-off-by: Mahesh Salgaonkar <[email protected]> Signed-off-by: Michael Ellerman <[email protected]> Link: https://msgid.link/[email protected]
2024-04-15powerpc: Add static_key_feature_checks_initialized flagNicholas Miehlbradt4-2/+12
JUMP_LABEL_FEATURE_CHECK_DEBUG used static_key_intialized to determine whether {cpu,mmu}_has_feature() is used before static keys were initialized. However, {cpu,mmu}_has_feature() should not be used before setup_feature_keys() is called but static_key_initialized is set well before this by the call to jump_label_init() in early_init_devtree(). This creates a window in which JUMP_LABEL_FEATURE_CHECK_DEBUG will not detect misuse and report errors. Add a flag specifically to indicate when {cpu,mmu}_has_feature() is safe to use. Signed-off-by: Nicholas Miehlbradt <[email protected]> Signed-off-by: Michael Ellerman <[email protected]> Link: https://msgid.link/[email protected]
2024-04-14locking/atomic/x86: Introduce arch_try_cmpxchg64_local()Uros Bizjak2-0/+40
Introduce arch_try_cmpxchg64_local() for 64-bit and 32-bit targets to improve code using cmpxchg64_local(). On 64-bit targets, the generated assembly improves from: 3e28: 31 c0 xor %eax,%eax 3e2a: 4d 0f b1 7d 00 cmpxchg %r15,0x0(%r13) 3e2f: 48 85 c0 test %rax,%rax 3e32: 0f 85 9f 00 00 00 jne 3ed7 <...> to: 3e28: 31 c0 xor %eax,%eax 3e2a: 4d 0f b1 7d 00 cmpxchg %r15,0x0(%r13) 3e2f: 0f 85 9f 00 00 00 jne 3ed4 <...> where a TEST instruction after CMPXCHG is saved. The improvements for 32-bit targets are even more noticeable, because double-word compare after CMPXCHG8B gets eliminated. Signed-off-by: Uros Bizjak <[email protected]> Signed-off-by: Ingo Molnar <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Waiman Long <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-04-14Merge branch 'linus' into perf/core, to pick up perf/urgent fixesIngo Molnar107-519/+1122
Pick up perf/urgent fixes that are upstream already, but not yet in the perf/core development branch. Signed-off-by: Ingo Molnar <[email protected]>
2024-04-14x86/pat: Fix W^X violation false-positives when running as Xen PV guestJuergen Gross1-8/+18
When running as Xen PV guest in some cases W^X violation WARN()s have been observed. Those WARN()s are produced by verify_rwx(), which looks into the PTE to verify that writable kernel pages have the NX bit set in order to avoid code modifications of the kernel by rogue code. As the NX bits of all levels of translation entries are or-ed and the RW bits of all levels are and-ed, looking just into the PTE isn't enough for the decision that a writable page is executable, too. When running as a Xen PV guest, the direct map PMDs and kernel high map PMDs share the same set of PTEs. Xen kernel initialization will set the NX bit in the direct map PMD entries, and not the shared PTEs. Fixes: 652c5bf380ad ("x86/mm: Refuse W^X violations") Reported-by: Jason Andryuk <[email protected]> Signed-off-by: Juergen Gross <[email protected]> Signed-off-by: Ingo Molnar <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-04-14x86/pat: Restructure _lookup_address_cpa()Juergen Gross1-4/+7
Modify _lookup_address_cpa() to no longer use lookup_address(), but only lookup_address_in_pgd(). This is done in preparation of using lookup_address_in_pgd_attr(). No functional change intended. Signed-off-by: Juergen Gross <[email protected]> Signed-off-by: Ingo Molnar <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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