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2024-04-29s390/os_info: Fix array size in struct os_infoSven Schnelle2-2/+4
gcc's -Warray-bounds warned about an out-of-bounds access to the entry array contained in struct os_info. This doesn't trigger a bug right now because there's a large reserved space after the array. Nevertheless fix this, and also add a BUILD_BUG_ON to make sure struct os_info is always exactly on page in size. Fixes: f4cac27dc0d6 ("s390/crash: Use old os_info to create PT_LOAD headers") Reviewed-by: Alexander Gordeev <[email protected]> Signed-off-by: Sven Schnelle <[email protected]> Signed-off-by: Alexander Gordeev <[email protected]>
2024-04-29s390/os_info: Initialize old os_info in standalone dump kernelAlexander Egorenkov1-1/+2
The commit be42660d0c13 ("s390/crash: use old os_info to create PT_LOAD headers") introduced use of the old os_info into standalone dump kernel. Before this change os_info_old_init() expected to be called only from a regular kdump kernel although the function itself is able to work in standalone dump kernels as well (because copy_oldmem_kernel() is able to handle both use cases). Therefore, fix the expectation of os_info_old_init() and enable it to be called from a standalone dump kernel. Fixes: f4cac27dc0d6 ("s390/crash: Use old os_info to create PT_LOAD headers") Acked-by: Alexander Gordeev <[email protected]> Signed-off-by: Alexander Egorenkov <[email protected]> Signed-off-by: Alexander Gordeev <[email protected]>
2024-04-29m68k: amiga: Use str_plural() to fix Coccinelle warningThorsten Blum1-1/+1
Fixes the following Coccinelle/coccicheck warning reported by string_choices.cocci: opportunity for str_plural(zorro_num_autocon) Signed-off-by: Thorsten Blum <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-04-29Merge tag 'qcom-arm64-for-6.10' of ↵Arnd Bergmann58-126/+2711
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt Qualcomm Arm64 DeviceTree updates for v6.10 Support for Sony Xperia 1V, on the SM8550 platform, is added. On IPQ8074, UART6 is described and unused gpios from QPIC are removed. Backlight and touchscreen are described on Samsung Grand Prime devices. RGB LED is added to Sony Xperia "Yoshino" devices, on which the volume-up key definition is corrected as well. Light Pulse Generator node is added to PM6150L PMIC, and blocks related to USB Type-C on PM6150 are added. On QCS6490 Rb3Gen2 UFS storage, USB Type-C management, a couple of remoteprocs and both USB Type-C and native DisplayPort are enabled. For the related IDP display is enabled, and the PMIC volume and power buttons are described. The inline crypto engine is added for SC7280, and an additional turbo frequency is added to the MDP. USB Type-C port management is introduce for the QRB2210 RB1. WiFi firmware-name qualifier is added to both RB1 and RB2 boards. The LMH node is added for the QCM2290, to configure the thresholds as well as provide thermal pressure input. The regulator range is adjusted for SD-card IO on SA8155P ADP, to allow UHS modes. The unused DCC is disabled on SC7180, and unused PMIC gpio block is disabled on Trogdor. For Lenovo Flex 5G, on SC8180X, the GPU firmware path is aligned with agreed upon firmware structure. The frequency of the I2C bus for touchpad is brought up to mitigate missing events. A number of additional cleanups are introduced. For SC8280XP GICv3 ITS is wired up for PCIe. EAS properties ad introduced. A PS_HOLD-based restart node is introduced and acts as a fallback if other mechanisms are unavailable to restart the board. QFPROM is described, missing LMH interrupts for thermal pressure are added. The TCSR download mode register is added, to allow configuring if download mode should be entered on a crash. USB Type-C handling is introduce for Fairphone FP3 as well. On SM6350 crypto engine and DisplayPort controllers are introduced. WiFi is enabled on the SM8150 Hardware Development Kit (HDK) USB PD properties are added on Xiaomi Mi Pad 5 Pro devices. Interconnect paths are added for UFS on SM8350, to ensure the bus is voted for when the controller is operating. On SM8550 the DMA coherency properties are corrected for SMMU and a few consumers. Missing DWC3 quirks are added and the SNPS PHY parameters are adjusted. Fastrpc banks are marked non-secure as needed. The GPU description is introduced on SM8650, and enabled on the QRD. A missing reserved-memory node is added, as is a few missing fastrpc compute banks, and the non-secure-domain flag for other banks. On X1 Elite SPMI support is added, together with PMIC definitons. The link properties for DP3 are corrected, and audio-related resets are introduced. SoundWire properties are corrected. Nodes describing the PCIe bridge under the host controller is added for a bunch of platforms. The GPIO carrying orientation information for USB Type-C is added across Fairphone 5, Lenovo Flex 5G, Lenovo Thinkpad X13s, SM8350 and SM845 HDKs. A few dtbTool-specific compatibles for msm8916 is dropped from the bindings. A number of DeviceTree binding validation issues are corrected. * tag 'qcom-arm64-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (110 commits) dt-bindings: arm: qcom: Add Samsung Galaxy S5 China (kltechn) arm64: dts: qcom: qrb4210-rb1: add firmware-name qualifier to WiFi node arm64: dts: qcom: qrb2210-rb1: add firmware-name qualifier to WiFi node arm64: dts: qcom: ipq6018: Add PCIe bridge node arm64: dts: qcom: ipq8074: Add PCIe bridge node arm64: dts: qcom: msm8996: Add PCIe bridge node arm64: dts: qcom: sc8180x: Add PCIe bridge node arm64: dts: qcom: qcs404: Add PCIe bridge node arm64: dts: qcom: sc7280: Add PCIe bridge node arm64: dts: qcom: msm8998: Add PCIe bridge node arm64: dts: qcom: sc8280xp: Add PCIe bridge node arm64: dts: qcom: sa8775p: Add PCIe bridge node arm64: dts: qcom: sm8650: Add PCIe bridge node arm64: dts: qcom: sm8550: Add PCIe bridge node arm64: dts: qcom: sm8450: Add PCIe bridge node arm64: dts: qcom: sm8350: Add PCIe bridge node arm64: dts: qcom: sm8150: Add PCIe bridge node arm64: dts: qcom: sdm845: Add PCIe bridge node arm64: dts: qcom: sm8250: Add PCIe bridge node arm64: dts: qcom: sdm845-db845c: make pcie0_3p3v_dual always-on ... Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29Merge tag 'qcom-arm32-for-6.10' of ↵Arnd Bergmann15-1376/+1897
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt Qualcomm Arm32 DeviceTree updates for v6.10 The QCA8074 PHY package found in IPQ4019 is properly described. The Sony Xperia Z2 Tablet is cleaned up and improved, vibrator support is added, upon support for Sony Xperia Z3 is added. Also based on MSM8974, support for Samsung Galaxy S5 China is introduced. The WiFi board type is added for these "klte" Samsung devices, to select appropriate NVRAM firmware file. Based on MSM8226, support for Motorola Moto G (2013) is added. Nodes representing the PCIe bridges under existing controllers are added for APQ8064, IPQ4019, IPQ8064, and SDX55. A number of fixes throughout to improve compliance with DeviceTree bindings. * tag 'qcom-arm32-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (22 commits) ARM: dts: qcom: msm8974: Add DTS for Samsung Galaxy S5 China (kltechn) ARM: dts: qcom: msm8974-klte-common: Pin WiFi board type ARM: dts: qcom: msm8974: Split out common part of samsung-klte ARM: dts: qcom: sdx55: Add PCIe bridge node ARM: dts: qcom: apq8064: Add PCIe bridge node ARM: dts: qcom: ipq4019: Add PCIe bridge node ARM: dts: qcom: ipq8064: Add PCIe bridge node ARM: dts: qcom: msm8974-sony-shinano: Enable vibrator ARM: dts: qcom: ipq4019: add QCA8075 PHY Package nodes ARM: dts: qcom: Add support for Motorola Moto G (2013) dt-bindings: arm: qcom: Add Motorola Moto G (2013) ARM: dts: qcom: msm8974: Add empty chosen node ARM: dts: qcom: msm8974: Add @0 to memory node name ARM: dts: qcom: Add Sony Xperia Z3 smartphone ARM: dts: qcom: msm8974-sony-castor: Split into shinano-common ARM: dts: qcom: msm8916: idle-state compatible require the generic idle-state ARM: dts: qcom: include cpu in idle-state node names ARM: dts: qcom: msm8974pro-castor: Rename wifi node name ARM: dts: qcom: msm8974pro-castor: Add debounce-interval for keys ARM: dts: qcom: msm8974pro-castor: Remove camera button definitions ... Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29Merge tag 'sunxi-dt-for-6.10-2' of ↵Arnd Bergmann4-0/+419
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt - new boards: RG35XX 2024, RG35XX-Plus, RG35XX-H * tag 'sunxi-dt-for-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: dts: allwinner: h700: Add RG35XX-H DTS arm64: dts: allwinner: h700: Add RG35XX-Plus DTS arm64: dts: allwinner: h700: Add RG35XX 2024 DTS dt-bindings: arm: sunxi: document Anbernic RG35XX handheld gaming device variants Link: https://lore.kernel.org/r/20240427133006.GA146501@jernej-laptop Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29Merge tag 'tegra-for-6.10-arm64-dt' of ↵Arnd Bergmann3-3/+19
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt arm64: tegra: Changes for v6.10-rc1 Adds the Security Engine devices found on Tegra234 and fixes RTC aliases by referencing them by label rather than path so that errors can be detected more easily. * tag 'tegra-for-6.10-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Add Tegra Security Engine DT nodes arm64: tegra: Correct Tegra132 I2C alias Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29Merge tag 'tegra-for-6.10-arm-dt' of ↵Arnd Bergmann2-2/+45
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt ARM: tegra: Changes for v6.10-rc1 Adds support for EMC frequency scaling on PAZ100 devices with RAM code 1 and cleans up deprecated device tree properties. * tag 'tegra-for-6.10-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: tegra20-ac97: Replace deprecated "gpio" suffix ARM: tegra: paz00: Add emc-tables for ram-code 1 Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29powerpc/pseries/vio: Don't return ENODEV if node or compatible missingLidong Zhong1-6/+2
We noticed the following nuisance messages during boot process: vio vio: uevent: failed to send synthetic uevent vio 4000: uevent: failed to send synthetic uevent vio 4001: uevent: failed to send synthetic uevent vio 4002: uevent: failedto send synthetic uevent vio 4004: uevent: failed to send synthetic uevent It's caused by either vio_register_device_node() failing to set dev->of_node or the node is missing a "compatible" property. To match the definition of modalias in modalias_show(), remove the return of ENODEV in such cases. The failure messages is also suppressed with this change. Signed-off-by: Lidong Zhong <[email protected]> Signed-off-by: Michael Ellerman <[email protected]> Link: https://msgid.link/[email protected]
2024-04-29powerpc/pseries: Enforce hcall result buffer validity and sizeNathan Lynch1-4/+4
plpar_hcall(), plpar_hcall9(), and related functions expect callers to provide valid result buffers of certain minimum size. Currently this is communicated only through comments in the code and the compiler has no idea. For example, if I write a bug like this: long retbuf[PLPAR_HCALL_BUFSIZE]; // should be PLPAR_HCALL9_BUFSIZE plpar_hcall9(H_ALLOCATE_VAS_WINDOW, retbuf, ...); This compiles with no diagnostics emitted, but likely results in stack corruption at runtime when plpar_hcall9() stores results past the end of the array. (To be clear this is a contrived example and I have not found a real instance yet.) To make this class of error less likely, we can use explicitly-sized array parameters instead of pointers in the declarations for the hcall APIs. When compiled with -Warray-bounds[1], the code above now provokes a diagnostic like this: error: array argument is too small; is of size 32, callee requires at least 72 [-Werror,-Warray-bounds] 60 | plpar_hcall9(H_ALLOCATE_VAS_WINDOW, retbuf, | ^ ~~~~~~ [1] Enabled for LLVM builds but not GCC for now. See commit 0da6e5fd6c37 ("gcc: disable '-Warray-bounds' for gcc-13 too") and related changes. Signed-off-by: Nathan Lynch <[email protected]> Signed-off-by: Michael Ellerman <[email protected]> Link: https://msgid.link/[email protected]
2024-04-29powerpc/dart: Drop unnecessary call to kmemleak_no_scan()Michael Ellerman1-4/+0
Erhard reported that kmemleak was showing a warning at boot: kmemleak: Not scanning unknown object at 0xc00000007f000000 CPU: 0 PID: 0 Comm: swapper Not tainted 5.19.0-rc3-PMacG5+ #2 Call Trace: .dump_stack_lvl+0x7c/0xc4 (unreliable) .kmemleak_no_scan+0xe0/0x100 .iommu_init_early_dart+0x2f0/0x924 .pmac_probe+0x1b0/0x20c .setup_arch+0x1b8/0x674 .start_kernel+0xdc/0xb74 start_here_common+0x1c/0x44 DART table allocated at: (____ptrval____) Which he bisected to a change in kmemleak, commit 23c2d497de21 ("mm: kmemleak: take a full lowmem check in kmemleak_*_phys()"). Because pmac_probe() is called before mem_topology_setup(), the min/ max PFN variables are still zero. That causes kmemleak_alloc_phys() to ignore the allocation, because the checks against the PFN fail. Then kmemleak_no_scan() can't find the allocation and prints warning. Given that kmemleak_alloc_phys() is ignoring the allocation to begin with, there's no need to call kmemleak_no_scan() at all, which avoids the warning. Reported-by: Erhard Furtner <[email protected]> Closes: https://lore.kernel.org/all/[email protected]%2F/ Signed-off-by: Michael Ellerman <[email protected]> Link: https://msgid.link/[email protected]
2024-04-29powerpc/eeh: Permanently disable the removed deviceGanesh Goudar2-3/+21
When a device is hot removed on powernv, the hotplug driver clears the device's state. However, on pseries, if a device is removed by phyp after reaching the error threshold, the kernel remains unaware, leading to the device not being torn down. This prevents necessary remediation actions like failover. Permanently disable the device if the presence check fails. Also, in eeh_dev_check_failure in we may consider the error as false positive if the device is hotpluged out as the get_state call returns EEH_STATE_NOT_SUPPORT and we may end up not clearing the device state, so log the event if the state is not moved to permanent failure state. Signed-off-by: Ganesh Goudar <[email protected]> Signed-off-by: Michael Ellerman <[email protected]> Link: https://msgid.link/[email protected]
2024-04-29powerpc/fadump: add hotplug_ready sysfs interfaceSourabh Jain1-0/+14
The elfcorehdr describes the CPUs and memory of the crashed kernel to the kernel that captures the dump, known as the second or fadump kernel. The elfcorehdr needs to be updated if the system's memory changes due to memory hotplug or online/offline events. Currently, memory hotplug events are monitored in userspace by udev rules, and fadump is re-registered, which recreates the elfcorehdr with the latest available memory in the system. However, the previous patch ("powerpc: make fadump resilient with memory add/remove events") moved the creation of elfcorehdr to the second or fadump kernel. This eliminates the need to regenerate the elfcorehdr during memory hotplug or online/offline events. Create a sysfs entry at /sys/kernel/fadump/hotplug_ready to let userspace know that fadump re-registration is not required for memory add/remove events. Signed-off-by: Sourabh Jain <[email protected]> Signed-off-by: Michael Ellerman <[email protected]> Link: https://msgid.link/[email protected]
2024-04-29powerpc: make fadump resilient with memory add/remove eventsSourabh Jain4-206/+242
Due to changes in memory resources caused by either memory hotplug or online/offline events, the elfcorehdr, which describes the CPUs and memory of the crashed kernel to the kernel that collects the dump (known as second/fadump kernel), becomes outdated. Consequently, attempting dump collection with an outdated elfcorehdr can lead to failed or inaccurate dump collection. Memory hotplug or online/offline events is referred as memory add/remove events in reset of the commit message. The current solution to address the aforementioned issue is as follows: Monitor memory add/remove events in userspace using udev rules, and re-register fadump whenever there are changes in memory resources. This leads to the creation of a new elfcorehdr with updated system memory information. There are several notable issues associated with re-registering fadump for every memory add/remove events. 1. Bulk memory add/remove events with udev-based fadump re-registration can lead to race conditions and, more importantly, it creates a wide window during which fadump is inactive until all memory add/remove events are settled. 2. Re-registering fadump for every memory add/remove event is inefficient. 3. The memory for elfcorehdr is allocated based on the memblock regions available during early boot and remains fixed thereafter. However, if elfcorehdr is later recreated with additional memblock regions, its size will increase, potentially leading to memory corruption. Address the aforementioned challenges by shifting the creation of elfcorehdr from the first kernel (also referred as the crashed kernel), where it was created and frequently recreated for every memory add/remove event, to the fadump kernel. As a result, the elfcorehdr only needs to be created once, thus eliminating the necessity to re-register fadump during memory add/remove events. At present, the first kernel prepares fadump header and stores it in the fadump reserved area. The fadump header includes the start address of the elfcorehdr, crashing CPU details, and other relevant information. In the event of a crash in the first kernel, the second/fadump boots and accesses the fadump header prepared by the first kernel. It then performs the following steps in a platform-specific function [rtas|opal]_fadump_process: 1. Sanity check for fadump header 2. Update CPU notes in elfcorehdr Along with the above, update the setup_fadump()/fadump.c to create elfcorehdr and set its address to the global variable elfcorehdr_addr for the vmcore module to process it in the second/fadump kernel. Section below outlines the information required to create the elfcorehdr and the changes made to make it available to the fadump kernel if it's not already. To create elfcorehdr, the following crashed kernel information is required: CPU notes, vmcoreinfo, and memory ranges. At present, the CPU notes are already prepared in the fadump kernel, so no changes are needed in that regard. The fadump kernel has access to all crashed kernel memory regions, including boot memory regions that are relocated by firmware to fadump reserved areas, so no changes for that either. However, it is necessary to add new members to the fadump header, i.e., the 'fadump_crash_info_header' structure, in order to pass the crashed kernel's vmcoreinfo address and its size to fadump kernel. In addition to the vmcoreinfo address and size, there are a few other attributes also added to the fadump_crash_info_header structure. 1. version: It stores the fadump header version, which is currently set to 1. This provides flexibility to update the fadump crash info header in the future without changing the magic number. For each change in the fadump header, the version will be increased. This will help the updated kernel determine how to handle kernel dumps from older kernels. The magic number remains relevant for checking fadump header corruption. 2. pt_regs_sz/cpu_mask_sz: Store size of pt_regs and cpu_mask structure of first kernel. These attributes are used to prevent dump processing if the sizes of pt_regs or cpu_mask structure differ between the first and fadump kernels. Note: if either first/crashed kernel or second/fadump kernel do not have the changes introduced here then kernel fail to collect the dump and prints relevant error message on the console. Signed-off-by: Sourabh Jain <[email protected]> Signed-off-by: Michael Ellerman <[email protected]> Link: https://msgid.link/[email protected]
2024-04-29powerpc/pseries: Add failure related checks for h_get_mpp and h_get_pppShrikanth Hegde3-7/+7
Couple of Minor fixes: - hcall return values are long. Fix that for h_get_mpp, h_get_ppp and parse_ppp_data - If hcall fails, values set should be at-least zero. It shouldn't be uninitialized values. Fix that for h_get_mpp and h_get_ppp Signed-off-by: Shrikanth Hegde <[email protected]> Signed-off-by: Michael Ellerman <[email protected]> Link: https://msgid.link/[email protected]
2024-04-29powerpc/pseries: Add pool idle time at LPAR bootShrikanth Hegde1-9/+30
When there are no options specified for lparstat, it is expected to give reports since LPAR(Logical Partition) boot. APP(Available Processor Pool) is an indicator of how many cores in the shared pool are free to use in Shared Processor LPAR(SPLPAR). APP is derived using pool_idle_time which is obtained using H_PIC call. The interval based reports show correct APP value while since boot report shows very high APP values. This happens because in that case APP is obtained by dividing pool idle time by LPAR uptime. Since pool idle time is reported by the PowerVM hypervisor since its boot, it need not align with LPAR boot. To fix that export boot pool idle time in lparcfg and powerpc-utils will use this info to derive APP as below for since boot reports. APP = (pool idle time - boot pool idle time) / (uptime * timebase) Results:: Observe APP values. ====================== Shared LPAR ================================ lparstat System Configuration type=Shared mode=Uncapped smt=8 lcpu=12 mem=15573440 kB cpus=37 ent=12.00 reboot stress-ng --cpu=$(nproc) -t 600 sleep 600 So in this case app is expected to close to 37-6=31. ====== 6.9-rc1 and lparstat 1.3.10 ============= %user %sys %wait %idle physc %entc lbusy app vcsw phint ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- 47.48 0.01 0.00 52.51 0.00 0.00 47.49 69099.72 541547 21 === With this patch and powerpc-utils patch to do the above equation === %user %sys %wait %idle physc %entc lbusy app vcsw phint ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- 47.48 0.01 0.00 52.51 5.73 47.75 47.49 31.21 541753 21 ===================================================================== Note: physc, purr/idle purr being inaccurate is being handled in a separate patch in powerpc-utils tree. Signed-off-by: Shrikanth Hegde <[email protected]> Signed-off-by: Michael Ellerman <[email protected]> Link: https://msgid.link/[email protected]
2024-04-29ARM: 9392/2: Support CLANG CFILinus Walleij1-0/+1
Support Control Flow Integrity (CFI) when compiling with CLANG. In the as-of-writing LLVM CLANG implementation (v17) the 32-bit ARM platform is supported by the generic CFI implementation, which isn't tailored specifically for ARM32 but works well enough to enable the feature. Tested-by: Kees Cook <[email protected]> Reviewed-by: Sami Tolvanen <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Signed-off-by: Russell King (Oracle) <[email protected]>
2024-04-29ARM: 9391/2: hw_breakpoint: Handle CFI breakpointsLinus Walleij2-0/+36
This registers a breakpoint handler for the new breakpoint type (0x03) inserted by LLVM CLANG for CFI breakpoints. If we are in permissive mode, just print a backtrace and continue. Example with CONFIG_CFI_PERMISSIVE enabled: > echo CFI_FORWARD_PROTO > /sys/kernel/debug/provoke-crash/DIRECT lkdtm: Performing direct entry CFI_FORWARD_PROTO lkdtm: Calling matched prototype ... lkdtm: Calling mismatched prototype ... CFI failure at lkdtm_indirect_call+0x40/0x4c (target: 0x0; expected type: 0x00000000) WARNING: CPU: 1 PID: 112 at lkdtm_indirect_call+0x40/0x4c CPU: 1 PID: 112 Comm: sh Not tainted 6.8.0-rc1+ #150 Hardware name: ARM-Versatile Express (...) lkdtm: FAIL: survived mismatched prototype function call! lkdtm: Unexpected! This kernel (6.8.0-rc1+ armv7l) was built with CONFIG_CFI_CLANG=y As you can see the LKDTM test fails, but I expect that this would be expected behaviour in the permissive mode. We are currently not implementing target and type for the CFI breakpoint as this requires additional operand bundling compiler extensions. CPUs without breakpoint support cannot handle breakpoints naturally, in these cases the permissive mode will not work, CFI will fall over on an undefined instruction: Internal error: Oops - undefined instruction: 0 [#1] PREEMPT ARM CPU: 0 PID: 186 Comm: ash Tainted: G W 6.9.0-rc1+ #7 Hardware name: Gemini (Device Tree) PC is at lkdtm_indirect_call+0x38/0x4c LR is at lkdtm_CFI_FORWARD_PROTO+0x30/0x6c This is reasonable I think: it's the best CFI can do to ascertain the the control flow is not broken on these CPUs. Reviewed-by: Kees Cook <[email protected]> Tested-by: Kees Cook <[email protected]> Reviewed-by: Sami Tolvanen <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Signed-off-by: Russell King (Oracle) <[email protected]>
2024-04-29ARM: 9390/2: lib: Annotate loop delay instructions for CFILinus Walleij1-6/+10
When we annotate the loop delay code with SYM_TYPED_FUNC_START() a function prototype signature will be emitted into the object file above each site called from C, and the delay loop code is using "fallthroughs" from the different assembly callbacks. This will not work as the execution flow will run into the prototype signatures. Rewrite the code to use explicit branches to the other code segments and annotate the code using SYM_TYPED_FUNC_START(). Tested on the ARM Versatile which uses the calibrated loop delay. Tested-by: Kees Cook <[email protected]> Reviewed-by: Sami Tolvanen <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Signed-off-by: Russell King (Oracle) <[email protected]>
2024-04-29ARM: 9389/2: mm: Define prototypes for all per-processor callsLinus Walleij2-0/+501
Each CPU type ("proc") has assembly calls for initializing and setting up the MM context, idle and so forth. These calls have the C form of e.g.: void cpu_arm920_init(void); However this prototype is not really specified, instead it is generated by the glue code in <asm/glue-proc.h> and the prototype is implicit from the generic prototype defined in <asm/proc-fns.h> such as cpu_proc_init() in this case. (This is a bit similar to the "interface" or inheritance concept in other languages.) To be able to annotate these assembly calls for CFI, they all need to have a proper C prototype per CPU call. Define these in a new C file that is only compiled when we use CFI, and add __ADDRESSABLE() to each so the compiler knows that these will be addressed (they are not explicitly called in C, they are called by way of cpu_proc_init() etc). It is a bit of definitions, but we do not expect new ARM32 CPUs to appear very much so it should be pretty static. Tested-by: Kees Cook <[email protected]> Reviewed-by: Sami Tolvanen <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Signed-off-by: Russell King (Oracle) <[email protected]>
2024-04-29ARM: 9388/2: mm: Type-annotate all per-processor assembly routinesLinus Walleij26-274/+434
Type tag the remaining per-processor assembly using the CFI symbol macros, in addition to those that were previously tagged for cache maintenance calls. This will be used to finally provide proper C prototypes for all these calls as well so that CFI can be made to work. Tested-by: Kees Cook <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Reviewed-by: Sami Tolvanen <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Signed-off-by: Russell King (Oracle) <[email protected]>
2024-04-29ARM: 9387/2: mm: Rewrite cacheflush vtables in CFI safe CLinus Walleij27-259/+688
Instead of defining all cache flush operations with an assembly macro in proc-macros.S, provide an explicit struct cpu_cache_fns for each CPU cache type in mm/cache.c. As a side effect from rewriting the vtables in C, we can avoid the aliasing for the "louis" cache callback, instead we can just assign the NN_flush_kern_cache_all() function to the louis callback in the C vtable. As the louis cache callback is called explicitly (not through the vtable) if we only have one type of cache support compiled in, we need an ifdef quirk for this in the !MULTI_CACHE case. Feroceon and XScale have some dma mapping quirk, in this case we can just define two structs and assign all but one callback to the main implementation; since each of them invoked define_cache_functions twice they require MULTI_CACHE by definition so the compiled-in shortcut is not used on these variants. Tested-by: Kees Cook <[email protected]> Reviewed-by: Sami Tolvanen <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Signed-off-by: Russell King (Oracle) <[email protected]>
2024-04-29ARM: 9386/2: mm: Use symbol alias for cache functionsLinus Walleij19-54/+22
The cache functions to flush user cache (*_flush_user_cache_all) are in many cases just a branch to the corresponfing userspace or kernelspace function. These functions also have the same arguments. Simplify these by using SYM_FUNC_ALIAS() in all affected sites. The NOP cache has very many similar calls which are just returns, but it would be confusing to use aliases here, so leave all the explicit returns and drop a comment on why we are not using aliases. Reviewed-by: Sami Tolvanen <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Signed-off-by: Russell King (Oracle) <[email protected]>
2024-04-29ARM: 9385/2: mm: Type-annotate all cache assembly routinesLinus Walleij22-373/+544
Tag all references to assembly functions with SYM_TYPED_FUNC_START() and SYM_FUNC_END() so they also become CFI-safe. When we add SYM_TYPED_FUNC_START() to assembly calls, a function prototype signature will be emitted into the object file at (pc-4) at the call site, so that the KCFI runtime check can compare this to the expected call. Example: 8011ae38: a540670c .word 0xa540670c 8011ae3c <v7_flush_icache_all>: 8011ae3c: e3a00000 mov r0, #0 8011ae40: ee070f11 mcr 15, 0, r0, cr7, cr1, {0} 8011ae44: e12fff1e bx lr This means no "fallthrough" code can enter a SYM_TYPED_FUNC_START() call from above it: there will be a function prototype signature there, so those are consistently converted to a branch or ret lr depending on context. Tested-by: Kees Cook <[email protected]> Reviewed-by: Sami Tolvanen <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Signed-off-by: Russell King (Oracle) <[email protected]>
2024-04-29ARM: 9384/2: mm: Make tlbflush routines CFI safeArd Biesheuvel9-58/+119
Instead of avoiding CFI entirely on the TLB flush helpers, reorganize the code so that the CFI machinery can deal with it. The important things to take into account are: - functions in asm called indirectly from C need to be defined using SYM_TYPED_FUNC_START() - a reference to the asm function needs to be visible to the compiler, in order to get it to emit the typeid symbol. The latter means that defining the cpu_tlb_fns structs is best done from C code, so that the references in the static initializers will be visible to the compiler. Signed-off-by: Ard Biesheuvel <[email protected]> Tested-by: Kees Cook <[email protected]> Reviewed-by: Sami Tolvanen <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Signed-off-by: Russell King (Oracle) <[email protected]>
2024-04-29ARM: 9381/1: kasan: clear stale stack poisonBoy.Wu1-0/+4
We found below OOB crash: [ 33.452494] ================================================================== [ 33.453513] BUG: KASAN: stack-out-of-bounds in refresh_cpu_vm_stats.constprop.0+0xcc/0x2ec [ 33.454660] Write of size 164 at addr c1d03d30 by task swapper/0/0 [ 33.455515] [ 33.455767] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G O 6.1.25-mainline #1 [ 33.456880] Hardware name: Generic DT based system [ 33.457555] unwind_backtrace from show_stack+0x18/0x1c [ 33.458326] show_stack from dump_stack_lvl+0x40/0x4c [ 33.459072] dump_stack_lvl from print_report+0x158/0x4a4 [ 33.459863] print_report from kasan_report+0x9c/0x148 [ 33.460616] kasan_report from kasan_check_range+0x94/0x1a0 [ 33.461424] kasan_check_range from memset+0x20/0x3c [ 33.462157] memset from refresh_cpu_vm_stats.constprop.0+0xcc/0x2ec [ 33.463064] refresh_cpu_vm_stats.constprop.0 from tick_nohz_idle_stop_tick+0x180/0x53c [ 33.464181] tick_nohz_idle_stop_tick from do_idle+0x264/0x354 [ 33.465029] do_idle from cpu_startup_entry+0x20/0x24 [ 33.465769] cpu_startup_entry from rest_init+0xf0/0xf4 [ 33.466528] rest_init from arch_post_acpi_subsys_init+0x0/0x18 [ 33.467397] [ 33.467644] The buggy address belongs to stack of task swapper/0/0 [ 33.468493] and is located at offset 112 in frame: [ 33.469172] refresh_cpu_vm_stats.constprop.0+0x0/0x2ec [ 33.469917] [ 33.470165] This frame has 2 objects: [ 33.470696] [32, 76) 'global_zone_diff' [ 33.470729] [112, 276) 'global_node_diff' [ 33.471294] [ 33.472095] The buggy address belongs to the physical page: [ 33.472862] page:3cd72da8 refcount:1 mapcount:0 mapping:00000000 index:0x0 pfn:0x41d03 [ 33.473944] flags: 0x1000(reserved|zone=0) [ 33.474565] raw: 00001000 ed741470 ed741470 00000000 00000000 00000000 ffffffff 00000001 [ 33.475656] raw: 00000000 [ 33.476050] page dumped because: kasan: bad access detected [ 33.476816] [ 33.477061] Memory state around the buggy address: [ 33.477732] c1d03c00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 33.478630] c1d03c80: 00 00 00 00 00 00 00 00 f1 f1 f1 f1 00 00 00 00 [ 33.479526] >c1d03d00: 00 04 f2 f2 f2 f2 00 00 00 00 00 00 f1 f1 f1 f1 [ 33.480415] ^ [ 33.481195] c1d03d80: 00 00 00 00 00 00 00 00 00 00 04 f3 f3 f3 f3 f3 [ 33.482088] c1d03e00: f3 f3 f3 f3 00 00 00 00 00 00 00 00 00 00 00 00 [ 33.482978] ================================================================== We find the root cause of this OOB is that arm does not clear stale stack poison in the case of cpuidle. This patch refer to arch/arm64/kernel/sleep.S to resolve this issue. From cited commit [1] that explain the problem Functions which the compiler has instrumented for KASAN place poison on the stack shadow upon entry and remove this poison prior to returning. In the case of cpuidle, CPUs exit the kernel a number of levels deep in C code. Any instrumented functions on this critical path will leave portions of the stack shadow poisoned. If CPUs lose context and return to the kernel via a cold path, we restore a prior context saved in __cpu_suspend_enter are forgotten, and we never remove the poison they placed in the stack shadow area by functions calls between this and the actual exit of the kernel. Thus, (depending on stackframe layout) subsequent calls to instrumented functions may hit this stale poison, resulting in (spurious) KASAN splats to the console. To avoid this, clear any stale poison from the idle thread for a CPU prior to bringing a CPU online. From cited commit [2] Extend to check for CONFIG_KASAN_STACK [1] commit 0d97e6d8024c ("arm64: kasan: clear stale stack poison") [2] commit d56a9ef84bd0 ("kasan, arm64: unpoison stack only with CONFIG_KASAN_STACK") Signed-off-by: Boy Wu <[email protected]> Reviewed-by: Mark Rutland <[email protected]> Acked-by: Andrey Ryabinin <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Fixes: 5615f69bc209 ("ARM: 9016/2: Initialize the mapping of KASan shadow memory") Signed-off-by: Russell King (Oracle) <[email protected]>
2024-04-29Merge tag 'sunxi-dt-for-6.10-1' of ↵Arnd Bergmann77-128/+543
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt - added multicolor LED node for pinephone - marked pinephone LEDs to retain status in suspend - DT cleanups & fixes - fixed A64 GPU frequency at 432 MHz - added H616 NMI node - new boards: PocketBook 614 Plus, Tanix TX1 * tag 'sunxi-dt-for-6.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: dts: allwinner: h616: Add NMI device node arm64: dts: allwinner: Add Tanix TX1 support dt-bindings: arm: sunxi: document Tanix TX1 name ARM: dts: sun5i: Add PocketBook 614 Plus support dt-bindings: arm: sunxi: Add PocketBook 614 Plus arm64: dts: allwinner: h616: Fix I2C0 pins arm64: dts: allwinner: a64: Run GPU at 432 MHz arm: dts: allwinner: drop underscore in node names arm64: dts: allwinner: Orange Pi: delete node by phandle arm64: dts: allwinner: drop underscore in node names arm64: dts: allwinner: Pine H64: correctly remove reg_gmac_3v3 arm64: dts: allwinner: pinephone: add multicolor LED node arm64: dts: allwinner: pinephone: Retain LEDs state in suspend Link: https://lore.kernel.org/r/20240426164510.GA101219@jernej-laptop Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29Merge tag 'renesas-dts-for-v6.10-tag2' of ↵Arnd Bergmann7-24/+306
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v6.10 (take two) - Add external interrupt (IRQC) support for the RZ/Five SoC, - Add SPI (MSIOF), external interrupt (INTC-EX), and IOMMU support for the R-Car V4M SoC, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: r8a779h0: Link IOMMU consumers arm64: dts: renesas: r8a779h0: Add IPMMU nodes arm64: dts: renesas: r8a779h0: Add INTC-EX node arm64: dts: renesas: r8a779h0: Add MSIOF nodes arm64: dts: renesas: rzg3s-smarc-som: Enable eMMC by default riscv: dts: renesas: rzfive-smarc-som: Drop deleting interrupt properties from ETH0/1 nodes arm64: dts: renesas: r9a07g043: Move interrupt-parent property to common DTSI riscv: dts: renesas: r9a07g043f: Add IRQC node to RZ/Five SoC DTSI arm64: dts: renesas: s4sk: Fix ethernet0 alias Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29parisc: Define sigset_t in parisc uapi headerHelge Deller2-12/+10
The util-linux debian package fails to build on parisc, because sigset_t isn't defined in asm/signal.h when included from userspace. Move the sigset_t type from internal header to the uapi header to fix the build. Link: https://buildd.debian.org/status/fetch.php?pkg=util-linux&arch=hppa&ver=2.40-7&stamp=1714163443&raw=0 Signed-off-by: Helge Deller <[email protected]> Cc: [email protected] # v6.0+
2024-04-29Merge tag 'v6.10-rockchip-dts64-1' of ↵Arnd Bergmann47-146/+5187
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt New boards: ArmSom Sige7, GameForce Chi,Forlinx FET3588-C with OK3588-C baseboard, Protonic MECSBC, Wolfvision PF5. The panthor driver for Mali Valhall GPUs landed, so a number of boards enable their gpu (Cool Pi, Theobroma-Systems boards, QuartzPro64, Rock5b, EVB1) Also the USBDP phy driver landed, allowing the usb3 dual-role controllers to be used on EVB1, Rock 5A and 5B, Indiedroid-Nova, Theobroma-Systems Tiger and Jaguar. A lot new peripherals for the Khadas Edge 2 (rtc, uart, sfc, adc, ir, usb, pcie, tf-card, pmic); PCIe3 support on Jaguar, audio support for the rk3308 and cache descriptions for rk356x and rk3328. Corrected model names for boards from Radxa, Pine64, Powkiddy, Anberic and general more dt cleanups. * tag 'v6.10-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (64 commits) arm64: dts: rockchip: add dual-role usb3 hosts to rk3588 Tiger-Haikou arm64: dts: rockchip: add usb-id extcon on rk3588 tiger arm64: dts: rockchip: fix comment for upper usb3 port arm64: dts: rockchip: fix pcie-refclk frequency on rk3588 tiger arm64: dts: rockchip: correct gpio_pwrctrl1 typos on rk3588(s) boards arm64: dts: rockchip: Correct the model names for Pine64 boards dt-bindings: arm: rockchip: Correct the descriptions for Pine64 boards arm64: dts: rockchip: Add ArmSom Sige7 board dt-bindings: arm: rockchip: Add ArmSoM Sige7 dt-bindings: vendor-prefixes: add ArmSoM arm64: dts: rockchip: add PCIe3 support on rk3588-jaguar arm64: dts: rockchip: move uart2 pinmux to dtsi on rk3588-tiger arm64: dts: rockchip: Add USB-C Support for rk3588s-indiedroid-nova arm64: dts: rockchip: correct the model name for Radxa ROCK 3A dt-bindings: arm: rockchip: correct the model name for Radxa ROCK 3A arm64: dts: rockchip: Correct the model names for Radxa ROCK 5 boards dt-bindings: arm: rockchip: Correct the descriptions for Radxa boards arm64: dts: rockchip: add lower USB3 port to rock-5b arm64: dts: rockchip: add upper USB3 port to rock-5a arm64: dts: rockchip: add USB3 to rk3588-evb1 ... Link: https://lore.kernel.org/r/15361932.O9o76ZdvQC@phil Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29x86/sev: Add callback to apply RMP table fixups for kexecAshish Kalra3-0/+45
Handle cases where the RMP table placement in the BIOS is not 2M aligned and the kexec-ed kernel could try to allocate from within that chunk which then causes a fatal RMP fault. The kexec failure is illustrated below: SEV-SNP: RMP table physical range [0x0000007ffe800000 - 0x000000807f0fffff] BIOS-provided physical RAM map: BIOS-e820: [mem 0x0000000000000000-0x000000000008efff] usable BIOS-e820: [mem 0x000000000008f000-0x000000000008ffff] ACPI NVS ... BIOS-e820: [mem 0x0000004080000000-0x0000007ffe7fffff] usable BIOS-e820: [mem 0x0000007ffe800000-0x000000807f0fffff] reserved BIOS-e820: [mem 0x000000807f100000-0x000000807f1fefff] usable As seen here in the e820 memory map, the end range of the RMP table is not aligned to 2MB and not reserved but it is usable as RAM. Subsequently, kexec -s (KEXEC_FILE_LOAD syscall) loads it's purgatory code and boot_param, command line and other setup data into this RAM region as seen in the kexec logs below, which leads to fatal RMP fault during kexec boot. Loaded purgatory at 0x807f1fa000 Loaded boot_param, command line and misc at 0x807f1f8000 bufsz=0x1350 memsz=0x2000 Loaded 64bit kernel at 0x7ffae00000 bufsz=0xd06200 memsz=0x3894000 Loaded initrd at 0x7ff6c89000 bufsz=0x4176014 memsz=0x4176014 E820 memmap: 0000000000000000-000000000008efff (1) 000000000008f000-000000000008ffff (4) 0000000000090000-000000000009ffff (1) ... 0000004080000000-0000007ffe7fffff (1) 0000007ffe800000-000000807f0fffff (2) 000000807f100000-000000807f1fefff (1) 000000807f1ff000-000000807fffffff (2) nr_segments = 4 segment[0]: buf=0x00000000e626d1a2 bufsz=0x4000 mem=0x807f1fa000 memsz=0x5000 segment[1]: buf=0x0000000029c67bd6 bufsz=0x1350 mem=0x807f1f8000 memsz=0x2000 segment[2]: buf=0x0000000045c60183 bufsz=0xd06200 mem=0x7ffae00000 memsz=0x3894000 segment[3]: buf=0x000000006e54f08d bufsz=0x4176014 mem=0x7ff6c89000 memsz=0x4177000 kexec_file_load: type:0, start:0x807f1fa150 head:0x1184d0002 flags:0x0 Check if RMP table start and end physical range in the e820 tables are not aligned to 2MB and in that case map this range to reserved in all the three e820 tables. [ bp: Massage. ] Fixes: c3b86e61b756 ("x86/cpufeatures: Enable/unmask SEV-SNP CPU feature") Signed-off-by: Ashish Kalra <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/r/df6e995ff88565262c2c7c69964883ff8aa6fc30.1714090302.git.ashish.kalra@amd.com
2024-04-29x86/e820: Add a new e820 table update helperAshish Kalra2-3/+5
Add a new API helper e820__range_update_table() with which to update an arbitrary e820 table. Move all current users of e820__range_update_kexec() to this new helper. [ bp: Massage. ] Signed-off-by: Ashish Kalra <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/r/b726af213ad55053f8a7a1e793b01bb3f1ca9dd5.1714090302.git.ashish.kalra@amd.com
2024-04-29Merge tag 'stm32-dt-for-v6.10-1' of ↵Arnd Bergmann18-1997/+2659
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt STM32 DT for v6.10, round 1 Highlights: ---------- - MPU: - STM32MP13: - Add and enable LTDC display (rocktech,rk043fn48h) on stm32mp135f-dk. - Add firewall bus based on ETZPC firewall controller. - Add PWR regulator support: Can be only used if the platform is set as "no-secure" (RCC_SECCFGR cleared) either use SCMI regulator. - STMP32MP15: - Add firewall bus based on ETZPC firewall controller. - Add heartbeat on stm32mp157c-ed1. - STM32MP25: - Add firewall bus based on RIFSC firewall controller. - Add clock support (RCC) based on SCMI clock protocol for root clocks. - Add all I2C instances and declare i2c2/i2c8 on stm32mp257f-ev1. - Add all SPI instances. and declare spi3/spi8 on stm32mp257f-ev1. * tag 'stm32-dt-for-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (21 commits) arm64: dts: st: correct masks for GIC PPI interrupts on stm32mp25 arm64: dts: st: add spi3 / spi8 properties on stm32mp257f-ev1 arm64: dts: st: add spi3/spi8 pins for stm32mp25 arm64: dts: st: add all 8 spi nodes on stm32mp251 arm64: dts: st: add i2c2 / i2c8 properties on stm32mp257f-ev1 arm64: dts: st: add i2c2/i2c8 pins for stm32mp25 arm64: dts: st: add all 8 i2c nodes on stm32mp251 arm64: dts: st: add rcc support for STM32MP25 ARM: dts: stm32: enable display support on stm32mp135f-dk board ARM: dts: stm32: add LTDC pinctrl on STM32MP13x SoC family ARM: dts: stm32: add LTDC support for STM32MP13x SoC family dt-bindings: display: simple: allow panel-common properties ARM: dts: stm32: add PWR regulators support on stm32mp131 media: dt-bindings: add access-controllers to STM32MP25 video codecs ARM: dts: stm32: add heartbeat led for stm32mp157c-ed1 ARM: dts: stm32: move can3 node from stm32f746 to stm32f769 ARM: dts: stm32: put ETZPC as an access controller for STM32MP13x boards ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards ARM: dts: stm32: put ETZPC as an access controller for STM32MP15x boards ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards ... Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29Merge tag 'hisi-arm64-dt-for-6.10' of ↵Arnd Bergmann6-98/+99
https://github.com/hisilicon/linux-hisi into soc/dt ARM64: DT: HiSilicon ARM64 DT updates for v6.10 - Move non-MMIO node out of soc for the hip05, hip06 and hip07 SoC - Miscellaneous fixes and improvements like correcting unit addresses and missing reg * tag 'hisi-arm64-dt-for-6.10' of https://github.com/hisilicon/linux-hisi: arm64: dts: hisilicon: hi6220: correct tsensor unit addresses arm64: dts: hisilicon: hi6220-hikey: drop unit addresses from fixed regulators arm64: dts: hisilicon: hi6220-hikey: add missing port@0 reg arm64: dts: hisilicon: hip07: correct unit addresses arm64: dts: hisilicon: hip07: move non-MMIO node out of soc arm64: dts: hisilicon: hip06: correct unit addresses arm64: dts: hisilicon: hip06: move non-MMIO node out of soc arm64: dts: hisilicon: hip05-d02: correct local-bus unit addresses arm64: dts: hisilicon: hip05: move non-MMIO node out of soc Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29Merge tag 'samsung-dt64-6.10' of ↵Arnd Bergmann5-15/+823
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt Samsung DTS ARM64 changes for v6.10 1. Add FIFO depth to each SPI node so we can avoid matching this through DTS alias. Difference SPI instances on given SoC have different FIFO depths. 2. Exynos850: add clock controllers providing clocks to CPUs. 3. Google GS101: few cleanups and add missing serial engine (USI) interface nodes. * tag 'samsung-dt64-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos: gs101: define all PERIC USI nodes arm64: dts: exynos: gs101: join lines close to 80 chars arm64: dts: exynos: gs101: move pinctrl-* properties after clocks arm64: dts: exynos: gs101: move serial_0 pinctrl-0/names to dtsi arm64: dts: exynos: gs101: reorder pinctrl-* properties arm64: dts: exynos850: Add CPU clocks arm64: dts: exynosautov9: specify the SPI FIFO depth arm64: dts: exynos5433: specify the SPI FIFO depth Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29x86/mm: Switch to new Intel CPU model definesTony Luck1-10/+6
New CPU #defines encode vendor and family as well as model. [ dhansen: vertically align 0's in invlpg_miss_ids[] ] Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/all/20240424181518.41946-1-tony.luck%40intel.com
2024-04-29x86/tsc_msr: Switch to new Intel CPU model definesTony Luck1-7/+7
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/all/20240424181518.41927-1-tony.luck%40intel.com
2024-04-29x86/tsc: Switch to new Intel CPU model definesTony Luck1-3/+3
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/all/20240424181517.41907-1-tony.luck%40intel.com
2024-04-29x86/cpu: Switch to new Intel CPU model definesTony Luck1-3/+3
New CPU #defines encode vendor and family as well as model. [ dhansen: vertically align macro and remove stray subject / ] Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/all/20240424181516.41887-1-tony.luck%40intel.com
2024-04-29x86/resctrl: Switch to new Intel CPU model definesTony Luck2-16/+16
New CPU #defines encode vendor and family as well as model. [ bp: Squash two resctrl patches into one. ] Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/all/20240424181514.41848-1-tony.luck%40intel.com
2024-04-29x86/microcode/intel: Switch to new Intel CPU model definesTony Luck1-3/+2
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/all/20240424181513.41829-1-tony.luck%40intel.com
2024-04-29x86/mce: Switch to new Intel CPU model definesTony Luck3-19/+18
New CPU #defines encode vendor and family as well as model. [ bp: Squash *three* mce patches into one, fold in fix: https://lore.kernel.org/r/[email protected] ] Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/all/20240424181511.41772-1-tony.luck%40intel.com
2024-04-29x86/cpu: Switch to new Intel CPU model definesTony Luck1-1/+1
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/all/20240424181511.41753-1-tony.luck%40intel.com
2024-04-29x86/cpu/intel_epb: Switch to new Intel CPU model definesTony Luck1-6/+6
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/all/20240424181510.41733-1-tony.luck%40intel.com
2024-04-29x86/aperfmperf: Switch to new Intel CPU model definesTony Luck1-9/+8
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/all/20240424181505.41654-1-tony.luck%40intel.com
2024-04-29x86/apic: Switch to new Intel CPU model definesTony Luck1-19/+19
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/all/20240424181504.41634-1-tony.luck%40intel.com
2024-04-29perf/x86/msr: Switch to new Intel CPU model definesTony Luck1-66/+66
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/all/20240424181503.41614-1-tony.luck%40intel.com
2024-04-29perf/x86/intel/uncore: Switch to new Intel CPU model definesTony Luck3-53/+55
New CPU #defines encode vendor and family as well as model. [ bp: Squash *three* uncore patches into one. ] Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/all/20240424181501.41557-1-tony.luck%40intel.com
2024-04-29Merge tag 'samsung-dt-6.10' of ↵Arnd Bergmann10-11/+30
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt Samsung DTS ARM changes for v6.10 1. Few cleanups of deprecated properties and node names pointed out by bindings newly converted to DT schema. 2. Fix S5PV210 NAND node size-cells, pointed out by DT schema. 3. Add FIFO depth to each SPI node so we can avoid matching this through DTS alias. Difference SPI instances on given SoC have different FIFO depths. 4. Fix Exynos4212 Galaxy Tab3 usable memory, because stock bootloader is not telling us truth. * tag 'samsung-dt-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos4212-tab3: limit usable memory range ARM: dts: samsung: s5pv210: specify the SPI FIFO depth ARM: dts: samsung: exynos5420: specify the SPI FIFO depth ARM: dts: samsung: exynos5250: specify the SPI FIFO depth ARM: dts: samsung: exynos4: specify the SPI FIFO depth ARM: dts: samsung: exynos3250: specify the SPI FIFO depth ARM: dts: samsung: s5pv210: correct onenand size-cells ARM: dts: samsung: s5pv210: align onenand node name with bindings ARM: dts: samsung: exynos5800-peach-pi: switch to undeprecated DP HPD GPIOs ARM: dts: samsung: smdk4412: align keypad node names with dtschema ARM: dts: samsung: smdk4412: fix keypad no-autorepeat ARM: dts: samsung: exynos4412-origen: fix keypad no-autorepeat ARM: dts: samsung: smdkv310: fix keypad no-autorepeat Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29Merge tag 'omap-for-v6.10/dt-signed' of ↵Arnd Bergmann3-114/+221
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/dt Devicetree changes for omaps for v6.10 Update n900 charge limit, and make use of the clksel binding for dra7 for the clksel clocks and other dpll output related clocks. * tag 'omap-for-v6.10/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: dra7: Use clksel binding for CTRL_CORE_SMA_SW_0 ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_USB ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_PER ARM: dts: dra7: Use clksel binding for CM_CLKSEL_ABE_PLL_SYS ARM: dts: dra7: Use clksel binding for CM_CLKSEL_CORE ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_EVE ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GMAC ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DRR ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GPU ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_IVA ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DSP ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_CORE ARM: dts: n900: set charge current limit to 950mA Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
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