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Main ESM address change was missing for J784S4 SOC,
So adding main ESM address mapping.
Signed-off-by: Udit Kumar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
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Main ESM address change was missing for J721S2 SOC,
So adding main ESM address mapping.
Signed-off-by: Udit Kumar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
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Previously, we had the sleep-moci pin set to always on. However, the
Dahlia carrier board supports disabling the sleep-moci when the system
is suspended to power down peripherals that support it. This reduces
overall power consumption. This commit adds support for this feature by
disabling the reg_force_sleep_moci regulator and adding a new regulator
for the USB hub that can be turned off when the system is suspended.
Signed-off-by: Stefan Eichenberger <[email protected]>
Reviewed-by: Francesco Dolcini <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
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The Verdin family has a signal called sleep-moci which can be used to
turn off peripherals on the carrier board when the SoM goes into
suspend. So far we have hogged this signal, which means the peripherals
are always on and it is not possible to add peripherals that depend on
the sleep-moci to be on. With this change, we replace the hog with a
regulator so that peripherals can add their own regulators that use the
same gpio. Carrier boards that allow peripherals to be powered off in
suspend can disable this regulator and implement their own regulator to
control the sleep-moci.
Signed-off-by: Stefan Eichenberger <[email protected]>
Reviewed-by: Francesco Dolcini <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
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Enable the UHS modes for MMCSD in J722S by removing the
no-1-8-v property.
Signed-off-by: Bhavya Kapoor <[email protected]>
Reviewed-by: Judith Mendez <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
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Remove sdhci-caps-mask to enable support for SDR104 speed mode for
SD card and remove no-1-8-v property so that SD card can work in
any UHS-1 high speed mode it can support.
Fixes: 4664ebd8346a ("arm64: dts: ti: Add initial support for J784S4 SoC")
Signed-off-by: Bhavya Kapoor <[email protected]>
Signed-off-by: Dasnavis Sabiya <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
Signed-off-by: Judith Mendez <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
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According to TRM for J721S2, SDR104 speed mode is supported by the SoC
but its capabilities were masked in device tree. Remove sdhci-caps-mask
to enable support for SDR104 speed mode for SD card in J721S2 SoC.
[+] Refer to : section 12.3.6.1.1 MMCSD Features, in J721S2 TRM
- https://www.ti.com/lit/zip/spruj28
Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC")
Signed-off-by: Bhavya Kapoor <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
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Hook up required IO voltage regulators and drop no-1-8-v to support UHS
modes on SD cards.
Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs")
Signed-off-by: Vignesh Raghavendra <[email protected]>
Signed-off-by: Judith Mendez <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
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On AM65x platform, sdhci0 is for eMMC and sdhci1 is for SD.
Remove the properties that are not applicable for each device.
Fixes: eac99d38f861 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel values")
Fixes: d7600d070fb0 ("arm64: dts: ti: k3-am65-main: Add support for sdhci1")
Signed-off-by: Judith Mendez <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
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Update otap-del-sel properties as per datasheet [0].
Add missing clkbuf-sel and itap-del-sel values also as per
datasheet [0].
Move clkbuf-sel and ti,trm-icp above the otap-del-sel properties
so the sdhci nodes could be more uniform across platforms.
[0] https://www.ti.com/lit/ds/symlink/am6548.pdf
Fixes: eac99d38f861 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel values")
Fixes: d7600d070fb0 ("arm64: dts: ti: k3-am65-main: Add support for sdhci1")
Signed-off-by: Judith Mendez <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
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Add symbols when building the am625-phyboard-lyra-rdk DTB so
overlays can be applied.
Fixes: d8280f30a9cd ("arm64: dts: ti: am62-phyboard-lyra: Add overlay to enable a GPIO fan")
Signed-off-by: Nathan Morrisson <[email protected]>
Reviewed-by: Wadim Egorov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
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The phyBOARD-Electra has a GPIO fan header. This overlay enables the fan
header and sets the fan to turn on at 65C.
Signed-off-by: Nathan Morrisson <[email protected]>
Reviewed-by: Wadim Egorov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
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This patch adds support for the Wave521cl on the AM62A-SK.
Signed-off-by: Brandon Brnich <[email protected]>
Reviewed-by: Devarsh Thakkar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
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Along fixing wkup UART RTS and TX pins as OUTPUT instead of INPUT
updating J784S4 macro for pin mux instead of J721S2.
Fixes: 45299dd1991b ("arm64: dts: ti: k3-am69-sk: Add mcu and wakeup uarts")
Fixes: 08ae12b63750 ("arm64: dts: ti: k3-am69-sk: Enable wakeup_i2c0 and eeprom")
Signed-off-by: Udit Kumar <[email protected]>
Reviewed-by: Francesco Dolcini <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
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Along fixing wkup UART TX pin as OUTPUT instead of INPUT,
updating J784S4 macro for pin mux instead of J721S2.
Fixes: 5dfbd1debc8c ("arm64: dts: ti: k3-j784s4-evm: Enable wakeup_i2c0 and eeprom")
Fixes: 6fa5d37a2f34 ("arm64: dts: ti: k3-j784s4-evm: Add mcu and wakeup uarts")
Signed-off-by: Udit Kumar <[email protected]>
Reviewed-by: Francesco Dolcini <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
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As per AM62A TRM [1] USB Link Power Management (LPM)
feature is not supported. Disable it else it may
cause enumeration failure on some devices.
> 4.9.2.1 USB2SS Unsupported Features
> The following features are not supported on this family of devices:
> ...
> - USB 2.0 ECN: Link Power Management (LPM)
> ...
[1] - https://www.ti.com/lit/pdf/spruj16
Signed-off-by: Roger Quadros <[email protected]>
Reviewed-by: Ravi Gunasekaran <[email protected]>
Link: https://lore.kernel.org/r/20240412-for-v6-10-am62-usb-typec-dt-v7-3-93b827adf97e@kernel.org
Signed-off-by: Nishanth Menon <[email protected]>
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There are two USB instances available on the am62p5 starter kit. Include
and enable them for use on the board.
USB LPM feature is kept disabled as it is not supported.
Signed-off-by: Vignesh Raghavendra <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
Reviewed-by: Andrew Davis <[email protected]>
Link: https://lore.kernel.org/r/20240412-for-v6-10-am62-usb-typec-dt-v7-2-93b827adf97e@kernel.org
Signed-off-by: Nishanth Menon <[email protected]>
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Exposing the entire CTRL_MMR space to syscon is not a good idea.
Add sub-nodes for USB0_PHY_CTRL and USB1_PHY_CTRL and use them
in the USB0/USB1 nodes.
Signed-off-by: Roger Quadros <[email protected]>
Reviewed-by: Andrew Davis <[email protected]>
Link: https://lore.kernel.org/r/20240412-for-v6-10-am62-usb-typec-dt-v7-1-93b827adf97e@kernel.org
Signed-off-by: Nishanth Menon <[email protected]>
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Add PHY2 register space to USB wrapper node. This is required
to deal with Errata i2409.
Signed-off-by: Roger Quadros <[email protected]>
Reviewed-by: Francesco Dolcini <[email protected]>
Link: https://lore.kernel.org/r/20240412-for-v6-9-am62-usb-errata-dt-v1-1-ef0d79920f75@kernel.org
Closes: https://lore.kernel.org/all/20240408095200.GA14655@francesco-nb/
Signed-off-by: Nishanth Menon <[email protected]>
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Add the required nodes to enable ICSSG SR1.0 based prueth networking.
Signed-off-by: Jan Kiszka <[email protected]>
Signed-off-by: Diogo Ivo <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
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The Audio Codec runs over the MCASP (Multichannel Audio Serial Port).
Add pinmux for the Audio Reference Clock and MCASP2.
Add DT nodes for Audio Codec, MCASP2, VCC 1v8 and VCC 3v3 regulators.
Additionally, create a sound node that connects our sound card and the
MCASP2.
Signed-off-by: Garrett Giordano <[email protected]>
Reviewed-by: Wadim Egorov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/defconfig
Enablement of rk3308 audio codec, panthor driver for Valhall GPUs
and USBDP phy driver for rk3588.
* tag 'v6.10-rockchip-defconfig64' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: defconfig: enable Rockchip Samsung USBDP PHY
arm64: defconfig: support Mali CSF-based GPUs
arm64: defconfig: enable Rockchip RK3308 internal audio codec driver
Link: https://lore.kernel.org/r/8976550.lOV4Wx5bFT@phil
Signed-off-by: Arnd Bergmann <[email protected]>
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Thomas needs the defio fixes, Maíra needs the vkms fixes and Joonas
has some fun with i915-gem conflicts.
Signed-off-by: Daniel Vetter <[email protected]>
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Even if multiple ASIDs are not supported, using the single-ASID variant
of the sfence.vma instruction preserves TLB entries for global (kernel)
pages. So it is always more efficient to use the single-ASID code path.
Reviewed-by: Alexandre Ghiti <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
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If the CPU does not support multiple ASIDs, all MM contexts use ASID 0.
In this case, it is still beneficial to flush the TLB by ASID, as the
single-ASID variant of the sfence.vma instruction preserves TLB entries
for global (kernel) pages.
This optimization is recommended by the RISC-V privileged specification:
If the implementation does not provide ASIDs, or software chooses
to always use ASID 0, then after every satp write, software should
execute SFENCE.VMA with rs1=x0. In the common case that no global
translations have been modified, rs2 should be set to a register
other than x0 but which contains the value zero, so that global
translations are not flushed.
It is not possible to apply this optimization when using the ASID
allocator, because that code must flush the TLB for all ASIDs at once
when incrementing the version number.
Reviewed-by: Alexandre Ghiti <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
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This variable is only used inside asids_init().
Reviewed-by: Alexandre Ghiti <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
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Currently, the size of the ASID field in the MM context ID dynamically
depends on the number of hardware-supported ASID bits. This requires
reading a global variable to extract either field from the context ID.
Instead, allocate the maximum possible number of bits to the ASID field,
so the layout of the context ID is known at compile-time.
Reviewed-by: Alexandre Ghiti <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
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When using the ASID allocator, the MM context ID contains two values:
the ASID in the lower bits, and the allocator version number in the
remaining bits. Use macros to make this separation more obvious.
Reviewed-by: Alexandre Ghiti <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
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Implementations affected by SiFive errata CIP-1200 have a bug which
forces the kernel to always use the global variant of the sfence.vma
instruction. When affected by this errata, do not attempt to flush a
range of addresses; each iteration of the loop would actually flush the
whole TLB instead. Instead, minimize the overall number of sfence.vma
instructions.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Yunhui Cui <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
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commit 3f1e782998cd ("riscv: add ASID-based tlbflushing methods") added
calls to the sfence.vma instruction with rs2 != x0. These single-ASID
instruction variants are also affected by SiFive errata CIP-1200.
Until now, the errata workaround was not needed for the single-ASID
sfence.vma variants, because they were only used when the ASID allocator
was enabled, and the affected SiFive platforms do not support multiple
ASIDs. However, we are going to start using those sfence.vma variants
regardless of ASID support, so now we need alternatives covering them.
Signed-off-by: Samuel Holland <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
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In SMP configurations, all TLB flushing narrower than flush_tlb_all()
goes through __flush_tlb_range(). Do the same in UP configurations.
This allows UP configurations to take advantage of recent improvements
to the code in tlbflush.c, such as support for huge pages and flushing
multiple-page ranges.
Reviewed-by: Alexandre Ghiti <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Yunhui Cui <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
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If no other CPU is online, a local cache or TLB flush is sufficient.
These checks can be constant-folded when SMP is disabled.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Alexandre Ghiti <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
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__flush_tlb_range() avoids broadcasting TLB flushes when an mm context
is only active on the local CPU. Apply this same optimization to TLB
flushes of kernel memory when only one CPU is online. This check can be
constant-folded when SMP is disabled.
Reviewed-by: Alexandre Ghiti <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
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An IPI backend is always required in an SMP configuration, but an SBI
implementation is not. For example, SBI will be unavailable when the
kernel runs in M mode. For this reason, consider IPI delivery of cache
and TLB flushes to be the base case, and any other implementation (such
as the SBI remote fence extension) to be an optimization.
Generally, if IPIs can be delivered without firmware assistance, they
are assumed to be faster than SBI calls due to the SBI context switch
overhead. However, when SBI is used as the IPI backend, then the context
switch cost must be paid anyway, and performing the cache/TLB flush
directly in the SBI implementation is more efficient than injecting an
interrupt to S-mode. This is the only existing scenario where
riscv_ipi_set_virq_range() is called with use_for_rfence set to false.
sbi_ipi_init() already checks riscv_ipi_have_virq_range(), so it only
calls riscv_ipi_set_virq_range() when no other IPI device is available.
This allows moving the static key and dropping the use_for_rfence
parameter. This decouples the static key from the irqchip driver probe
order.
Furthermore, the static branch only makes sense when CONFIG_RISCV_SBI is
enabled. Optherwise, IPIs must be used. Add a fallback definition of
riscv_use_sbi_for_rfence() which handles this case and removes the need
to check CONFIG_RISCV_SBI elsewhere, such as in cacheflush.c.
Reviewed-by: Anup Patel <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Alexandre Ghiti <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
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The logic is the same for all page table levels. See commit 69be3fb111e7
("riscv: enable MMU_GATHER_RCU_TABLE_FREE for SMP && MMU").
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Alexandre Ghiti <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
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Instruction cache flush IPIs are sent only to CPUs in cpu_online_mask,
so they will not target a CPU until it calls set_cpu_online() earlier in
smp_callin(). As a result, if instruction memory is modified between the
CPU coming out of reset and that point, then its instruction cache may
contain stale data. Therefore, the instruction cache must be flushed
after the set_cpu_online() synchronization point.
Fixes: 08f051eda33b ("RISC-V: Flush I$ when making a dirty page executable")
Reviewed-by: Alexandre Ghiti <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
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This is doubled compared to previous GPUs. We can't access the new
SW_FUSE_VALUE register without this.
Fixes: db33633b05c0 ("arm64: dts: qcom: sm8650: add GPU nodes")
Signed-off-by: Connor Abbott <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Pixel 6 (Oriole) has a USB-C connector that can act as host or device.
The USB role is detected dynamically using a MAX77759 TCPCI controller,
but since there is no driver for the MAX77759, the role is defaulted to
peripheral, without any endpoints / ports.
This allows Oriole to be configured as a gadget, e.g. using configfs.
As PMIC regulators are not implemented yet, we rely on USB LDOs being
enabled by the bootloader. A placeholder regulator is used for now.
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Add the USB 3.1 Dual Role Device (DRD) controller and USB-PHY nodes for
Google Tensor GS101.
The USB 3.1 DRD controller has the following features:
* compliant with both USB device 3.1 and USB device 2.0 standards
* compliant with USB host 3.1 and USB host 2.0 standards
* supports USB device 3.1 and USB device 2.0 interfaces
* supports USB host 3.1 and USB host 2.0 interfaces
* full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB device
2.0 interface
* super-speed (5 Gbps) mode with USB device 3.1 Gen1 interface
* super-speed plus (10 Gbps) mode with USB device 3.1 Gen2 interface
* single USB port which can be used for USB 3.1 or USB 2.0
* on-chip USB PHY transceiver
* DWC3 compatible
* supports up to 16 bi-directional endpoints
* compliant with xHCI 1.1 specification
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Enable the cmu_hsi2 clock management unit. It feeds some of
the high speed interfaces such as PCIe and UFS.
Signed-off-by: Peter Griffin <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Enable the cmu-hsi0 clock controller. It feeds USB.
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
Microchip ARM64 device tree updates for v6.10
It contains:
- dtbs_check and dtc W=1 warning fixes
- mdio2 and serdes address fixes for sparx5
* tag 'microchip-dt64-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
arm64: dts: microchip: sparx5_pcb135: drop duplicated NOR flash
arm64: dts: microchip: sparx5_pcb134: drop duplicated NOR flash
arm64: dts: microchip: sparx5_pcb135: drop LED unit addresses
arm64: dts: microchip: sparx5_pcb134: drop LED unit addresses
arm64: dts: microchip: sparx5_pcb135: align I2C mux node name with bindings
arm64: dts: microchip: sparx5_pcb134: align I2C mux node name with bindings
arm64: dts: microchip: sparx5_pcb135: add missing I2C mux unit addresses
arm64: dts: microchip: sparx5_pcb134: add missing I2C mux unit addresses
arm64: dts: microchip: sparx5: correct serdes unit address
arm64: dts: microchip: sparx5: fix mdio reg
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Arnd Bergmann <[email protected]>
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https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
Minor improvements in ARM DTS for v6.10
1. TI: add missing white-spaces for code readability.
2. Aspeed: add vendor prefix to compatibles, to properly describe
hardware, even though Linux drivers match by device name.
* tag 'dt-cleanup-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt:
ARM: dts: aspeed: Add vendor prefixes to lm25066 compat strings
ARM: dts: ti: omap: minor whitespace cleanup
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Arnd Bergmann <[email protected]>
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https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
Minor improvements in ARM64 DTS for v6.10
Fixes, which might have practical impact, however things were broken for
long enough to justify pushing it regular path:
1. ARM Juno: shorten node names for thermal zones, because Linux drivers
have strict limit of 20 characters.
2. HiSilicon: correct size of GIC GICC address space and add missing
GICH and GICV spaces, add cache info to properly describe cache
topology and solve kernel boot warning.
Several cleanups:
1. Use capital "OR" for multiple licenses in SPDX.
2. Correct white-spaces for code readability.
3. Fix W=1 dtc compiler warnings, which should not have practical
impact for Amazon, APM, Cavium, Realtek, Socionext Uniphier and
Spreadtrum like:
- missing unit addresses,
- nodes not belonging to soc node,
- not using generic node names,
- few incorrect unit addresses.
* tag 'dt64-cleanup-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt: (28 commits)
arm64: dts: cavium: thunder2-99xx: drop redundant reg-names
arm64: dts: amazon: alpine-v3: correct gic unit addresses
arm64: dts: amazon: alpine-v3: drop cache nodes unit addresses
arm64: dts: amazon: alpine-v3: add missing io-fabric unit addresses
arm64: dts: amazon: alpine-v2: move non-MMIO node out of soc
arm64: dts: amazon: alpine-v2: add missing io-fabric unit addresses
arm64: dts: apm: shadowcat: move non-MMIO node out of soc
arm64: dts: apm: storm: move non-MMIO node out of soc
arm64: dts: cavium: correct unit addresses
arm64: dts: cavium: move non-MMIO node out of soc
arm64: dts: realtek: rtc16xx: add missing unit address to soc node
arm64: dts: realtek: rtd139x: add missing unit address to soc node
arm64: dts: realtek: rtd129x: add missing unit address to soc node
arm64: dts: uniphier: ld20-global: drop audio codec port unit address
arm64: dts: uniphier: ld20-global: use generic node name for audio-codec
arm64: dts: uniphier: ld11-global: drop audio codec port unit address
arm64: dts: uniphier: ld11-global: use generic node name for audio-codec
arm64: dts: sharkl3: add missing unit addresses
arm64: dts: whale2: add missing ap-apb unit address
arm64: dts: sc9860: move GIC to soc node
...
Signed-off-by: Arnd Bergmann <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
i.MX arm64 device tree for 6.10:
- New board support: Emcraft Systems NavQ+ Kit, Toradex Colibri iMX8DX,
and S32G-VNP-RDB3 board.
- A series from Alexander Stein that adds empty DSI output endpoint to
simplify DSI connection description at board level.
- Add pinmux and I2C GPIOs to support bus recovery for LX2160A.
- Add cm40 subsystem description for i.MX8 SoCs.
- A series from Frank Li that adds ADC, LPSPI and FlexSPI devices for
imx8qm-mek board.
- Add audio devices ASRC, ESAI, SPDIF and SAI for i.MX8QXP and correct
audio LPCG index.
- A couple of changes from Ghennadi Procopciuc that add SCMI firmware
and uSDHC nodes for S32G SoC.
- A couple of imx8mp-msc-sm2s updates from Ian Ray improving I2C pad
drive strength and adding SDA/SCL GPIOs for I2C devices.
- Add PCA9451A PMIC and PCF2131 RTC support for imx93-11x11-evk board.
- A series from Lucas Stach to enable HDMI display support for i.MX8MP.
- A series from Peng Fan to improve i.MX93 support for LPI2C, LPSPI, FEC
and eQoS.
- A couple of LS1028A changes from Rob Herring to improve PCI device
description.
- A series from Shengjiu Wang adding HDMI and PDM mic sound support for
imx8mp-evk board.
- A number of i.MX8M Venice device improvements from Stefan Eichenberger,
Tim Harvey and Vitor Soares.
- A series from Xu Yang that enables USB support for imx8ulp-evk and
imx93-11x11-evk board.
- Other small and random updates on various boards.
* tag 'imx-dt64-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (78 commits)
arm64: dts: imx93-11x11-evk: add RTC PCF2131 support
arm64: dts: imx93-11x11-evk: add reset gpios for ethernet PHYs
arm64: dts: imx93-11x11-evk: add sleep pinctrl for sdhc2
arm64: dts: imx93-11x11-evk: add different usdhc pinctrl for different timing usage
arm64: dts: imx93-11x11-evk: add sleep pinctrl for eqos and fec
arm64: dts: imx93-11x11-evk: update resource table address
arm64: dts: imx93: add nvmem property for eqos
arm64: dts: imx93: add nvmem property for fec1
arm64: dts: imx93: assign usdhc[1..3] root clock to 400MHz
arm64: dts: imx93: add dma support for lpspi[1..8]
arm64: dts: imx93: add dma support for lpi2c[1..8]
arm64: dts: imx93: use FSL_EDMA_RX for rx channel
arm64: dts: freescale: ls1028a: Add standard PCI device compatible strings to ENETC
arm64: dts: freescale: ls1028a: Fix embedded PCI interrupt mapping
arm64: dts: imx8qxp-mek: add cm40_i2c, wm8960 and sai[0,1,4,5]
arm64: dts: imx8mp: Align both CSI2 pixel clock
arm64: dts: freescale: imx8m[mp]-verdin: Update audio card name
arm64: dts: imx8mp: Enable HDMI on TQMa8MPxL/MBa8MPxL
arm64: dts: imx8ulp: add caam jr
arm64: dts: imx8mp-msc-sm2s: Add i2c{1,6} sda-/scl-gpios
...
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Arnd Bergmann <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
i.MX ARM device tree for 6.10:
- New board support: Seeed Studio NPi dev board, UNI-T UTi260B thermal
camera board.
- A couple of IRQ config correction for touchscreen and RC5T619 on
tolino-shine2hd device.
- Add snvs-poweroff support for i.MX7.
- A couple of dtb_check warning fixes on i.MX6SX and i.MX6QDL ESAI.
- Enable USB support for imx6qdl-udoo and imx27-phytec.
- A big series from Uwe Kleine-König to adopt #pwm-cells = <3> for i.MX
devices.
- Other small changes and clean-ups.
* tag 'imx-dt-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (64 commits)
ARM: dts: imx6ul-pico: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-kontron-bl-common: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-kontron-bl-43: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-isiot: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-imx6ull-opos6uldev: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-geam: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-ccimx6ulsbcpro: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-14x14-evk: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6sx-softing-vining-2000: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6sx-sdb: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6sx-nitrogen6sx: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6sll-evk: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6sl-evk: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-var-dt6customboard: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-prti6q: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-pistachio: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-novena: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-kp: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-skov-cpu: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-savageboard: Use #pwm-cells = <3> for imx27-pwm device
...
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Arnd Bergmann <[email protected]>
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When the kernel is built with CONFIG_PIE_BUILD option enabled it
uses dynamic symbols, for which the linker does not allow more
than 64K number of entries. This can break features like kpatch.
Hence, whenever possible the kernel is built with CONFIG_PIE_BUILD
option disabled. For that support of unaligned symbols generated by
linker scripts in the compiler is necessary.
However, older compilers might lack such support. In that case the
build process resorts to CONFIG_PIE_BUILD option-enabled build.
Compile object files with -fPIC option and then link the kernel
binary with -no-pie linker option.
As result, the dynamic symbols are not generated and not only kpatch
feature succeeds, but also the whole CONFIG_PIE_BUILD option-enabled
code could be dropped.
[ agordeev: Reworded the commit message ]
Suggested-by: Ulrich Weigand <[email protected]>
Signed-off-by: Sumanth Korikkar <[email protected]>
Reviewed-by: Alexander Gordeev <[email protected]>
Signed-off-by: Alexander Gordeev <[email protected]>
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Sections .hash and .gnu.hash are only created when CONFIG_PIE_BUILD
option is enabled. Drop these for the case CONFIG_PIE_BUILD is disabled.
[ agordeev: Reworded the commit message ]
Fixes: 778666df60f0 ("s390: compile relocatable kernel without -fPIE")
Suggested-by: Alexander Gordeev <[email protected]>
Signed-off-by: Sumanth Korikkar <[email protected]>
Reviewed-by: Alexander Gordeev <[email protected]>
Signed-off-by: Alexander Gordeev <[email protected]>
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Using __builtin_return_address(n) might return undefined values
when used with values of n outside of the stack. This was noticed
when __builtin_return_address() was called in ftrace on top level
functions like the interrupt handlers.
As this behaviour cannot be fixed, use the s390 stack unwinder and
remove the ftrace compilation flags for unwind_bc.c and stacktrace.c
to prevent the unwinding function polluting function traces.
Another advantage is that this also works with clang.
Reviewed-by: Heiko Carstens <[email protected]>
Signed-off-by: Sven Schnelle <[email protected]>
Signed-off-by: Alexander Gordeev <[email protected]>
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The S/390 architecture doesn't support SMBIOS, so CONFIG_DMI will
never be defined there. So we can simply omit these preprocessing
directives and speed up the build a bit.
Signed-off-by: Jean Delvare <[email protected]>
Cc: Niklas Schnelle <[email protected]>
Cc: Gerald Schaefer <[email protected]>
Acked-by: Niklas Schnelle <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexander Gordeev <[email protected]>
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