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2024-04-30arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodesPeter Griffin1-0/+36
Add the ufs controller node and phy node for gs101. Signed-off-by: Peter Griffin <[email protected]> Acked-by: André Draszik <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2024-04-30arm64: dts: exynos: gs101: Add the hsi2 sysreg nodePeter Griffin1-0/+6
This has some configuration bits such as sharability that are required by UFS. Signed-off-by: Peter Griffin <[email protected]> Reviewed-by: André Draszik <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2024-04-30Merge tag 'kvmarm-fixes-6.9-2' of ↵Paolo Bonzini1-4/+4
git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/arm64 fixes for 6.9, part #2 - Fix + test for a NULL dereference resulting from unsanitised user input in the vgic-v2 device attribute accessors
2024-04-30Merge patch series "riscv: ASID-related and UP-related TLB flush enhancements"Palmer Dabbelt15-151/+113
Samuel Holland <[email protected]> says: This series converts uniprocessor kernel builds to use the same TLB flushing code as SMP builds, to take advantage of batching and existing range- and ASID-based TLB flush optimizations. It optimizes out IPIs and SBI calls based on the online CPU count, which also covers the scenario where SMP was enabled at build time but only one CPU is present/online. A final optimization is to use single-ASID flushes wherever possible, to avoid unnecessary TLB misses for kernel mappings. This series has a semantic conflict with the AIA patches that are in linux-next due to the removal of the third parameter of riscv_ipi_set_virq_range(), which is called from imsic_ipi_domain_init() in drivers/irqchip/irq-riscv-imsic-early.c. The resolution is to remove the extra argument from the call site. Here are some numbers from D1 which show the performance impact: v6.9-rc1: System Benchmarks Partial Index BASELINE RESULT INDEX Execl Throughput 43.0 198.5 46.2 File Copy 1024 bufsize 2000 maxblocks 3960.0 73934.4 186.7 File Copy 256 bufsize 500 maxblocks 1655.0 20242.6 122.3 File Copy 4096 bufsize 8000 maxblocks 5800.0 197706.4 340.9 Pipe Throughput 12440.0 176974.2 142.3 Pipe-based Context Switching 4000.0 23626.8 59.1 Process Creation 126.0 449.9 35.7 Shell Scripts (1 concurrent) 42.4 544.4 128.4 Shell Scripts (16 concurrent) --- 35.3 --- Shell Scripts (8 concurrent) 6.0 71.6 119.3 System Call Overhead 15000.0 248072.6 165.4 ======== System Benchmarks Index Score (Partial Only) 110.6 v6.9-rc1 + this patch series: System Benchmarks Partial Index BASELINE RESULT INDEX Execl Throughput 43.0 196.8 45.8 File Copy 1024 bufsize 2000 maxblocks 3960.0 71782.2 181.3 File Copy 256 bufsize 500 maxblocks 1655.0 21269.4 128.5 File Copy 4096 bufsize 8000 maxblocks 5800.0 199424.0 343.8 Pipe Throughput 12440.0 196468.6 157.9 Pipe-based Context Switching 4000.0 24261.8 60.7 Process Creation 126.0 459.0 36.4 Shell Scripts (1 concurrent) 42.4 543.8 128.2 Shell Scripts (16 concurrent) --- 35.5 --- Shell Scripts (8 concurrent) 6.0 71.7 119.6 System Call Overhead 15000.0 259415.2 172.9 ======== System Benchmarks Index Score (Partial Only) 113.0 * b4-shazam-lts: riscv: mm: Always use an ASID to flush mm contexts riscv: mm: Preserve global TLB entries when switching contexts riscv: mm: Make asid_bits a local variable riscv: mm: Use a fixed layout for the MM context ID riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: mm: Combine the SMP and UP TLB flush code riscv: Only send remote fences when some other CPU is online riscv: mm: Broadcast kernel TLB flushes only when needed riscv: Use IPIs for remote cache/TLB flushes by default riscv: Factor out page table TLB synchronization riscv: Flush the instruction cache during SMP bringup Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
2024-04-30riscv: select ARCH_HAS_FAST_MULTIPLIERJisheng Zhang1-0/+1
Currently, riscv linux requires at least IMA, so all platforms have a multiplier. And I assume the 'mul' efficiency is comparable or better than a sequence of five or so register-dependent arithmetic instructions. Select ARCH_HAS_FAST_MULTIPLIER to get slightly nicer codegen. Refer to commit f9b4192923fa ("[PATCH] bitops: hweight() speedup") for more details. In a simple benchmark test calling hweight64() in a loop, it got: about 14% performance improvement on JH7110, tested on Milkv Mars. about 23% performance improvement on TH1520 and SG2042, tested on Sipeed LPI4A and SG2042 platform. a slight performance drop on CV1800B, tested on milkv duo. Among all riscv platforms in my hands, this is the only one which sees a slight performance drop. It means the 'mul' isn't quick enough. However, the situation exists on x86 too, for example, P4 doesn't have fast integer multiplies as said in the above commit, x86 also selects ARCH_HAS_FAST_MULTIPLIER. So let's select ARCH_HAS_FAST_MULTIPLIER which can benefit almost riscv platforms. Samuel also provided some performance numbers: On Unmatched: 20% speedup for __sw_hweight32 and 30% speedup for __sw_hweight64. On D1: 8% speedup for __sw_hweight32 and 8% slowdown for __sw_hweight64. Signed-off-by: Jisheng Zhang <[email protected]> Reviewed-by: Samuel Holland <[email protected]> Tested-by: Samuel Holland <[email protected]> Reviewed-by: Alexandre Ghiti <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
2024-04-30Merge patch series "riscv: enable lockless lockref implementation"Palmer Dabbelt2-0/+19
Jisheng Zhang <[email protected]> says: This series selects ARCH_USE_CMPXCHG_LOCKREF to enable the cmpxchg-based lockless lockref implementation for riscv. Then, implement arch_cmpxchg64_{relaxed|acquire|release}. After patch1: Using Linus' test case[1] on TH1520 platform, I see a 11.2% improvement. On JH7110 platform, I see 12.0% improvement. After patch2: on both TH1520 and JH7110 platforms, I didn't see obvious performance improvement with Linus' test case [1]. IMHO, this may be related with the fence and lr.d/sc.d hw implementations. In theory, lr/sc without fence could give performance improvement over lr/sc plus fence, so add the code here to leave performance improvement room on newer HW platforms. * b4-shazam-merge: riscv: cmpxchg: implement arch_cmpxchg64_{relaxed|acquire|release} riscv: select ARCH_USE_CMPXCHG_LOCKREF Link: http://marc.info/?l=linux-fsdevel&m=137782380714721&w=4 [1] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
2024-04-30riscv: mm: still create swiotlb buffer for kmalloc() bouncing if requiredJisheng Zhang2-2/+16
After commit f51f7a0fc2f4 ("riscv: enable DMA_BOUNCE_UNALIGNED_KMALLOC for !dma_coherent"), for non-coherent platforms with less than 4GB memory, we rely on users to pass "swiotlb=mmnn,force" kernel parameters to enable DMA bouncing for unaligned kmalloc() buffers. Now let's go further: If no bouncing needed for ZONE_DMA, let kernel automatically allocate 1MB swiotlb buffer per 1GB of RAM for kmalloc() bouncing on non-coherent platforms, so that no need to pass "swiotlb=mmnn,force" any more. The math of "1MB swiotlb buffer per 1GB of RAM for kmalloc() bouncing" is taken from arm64. Users can still force smaller swiotlb buffer by passing "swiotlb=mmnn". Signed-off-by: Jisheng Zhang <[email protected]> Reviewed-by: Alexandre Ghiti <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
2024-04-30riscv: Annotate pgtable_l{4,5}_enabled with __ro_after_initDawei Li1-2/+2
pgtable_l{4,5}_enabled are read only after initialization, make explicit annotation of __ro_after_init on them. Signed-off-by: Dawei Li <[email protected]> Reviewed-by: Alexandre Ghiti <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
2024-04-30riscv: Remove redundant CONFIG_64BIT from pgtable_l{4,5}_enabledDawei Li1-2/+2
IS_ENABLED(CONFIG_64BIT) in initialization of pgtable_l{4,5}_enabled is redundant, remove it. Signed-off-by: Dawei Li <[email protected]> Reviewed-by: Alexandre Ghiti <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
2024-04-30Merge patch series "riscv: Create and document PR_RISCV_SET_ICACHE_FLUSH_CTX ↵Palmer Dabbelt6-9/+159
prctl" Charlie Jenkins <[email protected]> says: Improve the performance of icache flushing by creating a new prctl flag PR_RISCV_SET_ICACHE_FLUSH_CTX. The interface is left generic to allow for future expansions such as with the proposed J extension [1]. Documentation is also provided to explain the use case. Patch sent to add PR_RISCV_SET_ICACHE_FLUSH_CTX to man-pages [2]. [1] https://github.com/riscv/riscv-j-extension [2] https://lore.kernel.org/linux-man/[email protected] * b4-shazam-merge: cpumask: Add assign cpu documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl riscv: Include riscv_set_icache_flush_ctx prctl riscv: Remove unnecessary irqflags processor.h include Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
2024-04-30Merge patch series "riscv: fix patching with IPI"Palmer Dabbelt3-9/+53
Alexandre Ghiti <[email protected]> says: patch 1 removes a useless memory barrier and patch 2 actually fixes the issue with IPI in the patching code. * b4-shazam-merge: riscv: Fix text patching when IPI are used riscv: Remove superfluous smp_mb() Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
2024-04-30um: virtio_uml: Convert to platform remove callback returning voidUwe Kleine-König1-3/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Richard Weinberger <[email protected]>
2024-04-30um: rtc: Convert to platform remove callback returning voidUwe Kleine-König1-3/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Richard Weinberger <[email protected]>
2024-04-30um: Remove unused do_get_thread_area functionTiwei Bie1-17/+0
It's not used since it was introduced by commit aa6758d4867c ("[PATCH] uml: implement {get,set}_thread_area for i386"). Now, it's causing a -Wmissing-prototypes warning: arch/x86/um/tls_32.c:39:5: warning: no previous prototype for ‘do_get_thread_area’ [-Wmissing-prototypes] 39 | int do_get_thread_area(struct user_desc *info) | ^~~~~~~~~~~~~~~~~~ The original author also had doubts about whether it should be used. Considering that 18 years have passed, let's just remove it. Signed-off-by: Tiwei Bie <[email protected]> Signed-off-by: Richard Weinberger <[email protected]>
2024-04-30um: Fix -Wmissing-prototypes warnings for __vdso_*Tiwei Bie1-2/+8
The VDSO functions are defined as globals and intended to be called from userspace. Let's just workaround the -Wmissing-prototypes warnings by declaring them locally. This will address below -Wmissing-prototypes warnings: arch/x86/um/vdso/um_vdso.c:16:5: warning: no previous prototype for ‘__vdso_clock_gettime’ [-Wmissing-prototypes] arch/x86/um/vdso/um_vdso.c:30:5: warning: no previous prototype for ‘__vdso_gettimeofday’ [-Wmissing-prototypes] arch/x86/um/vdso/um_vdso.c:44:21: warning: no previous prototype for ‘__vdso_time’ [-Wmissing-prototypes] arch/x86/um/vdso/um_vdso.c:57:1: warning: no previous prototype for ‘__vdso_getcpu’ [-Wmissing-prototypes] While at it, also fix the "WARNING: Prefer 'unsigned int *' to bare use of 'unsigned *'" checkpatch warning. Signed-off-by: Tiwei Bie <[email protected]> Signed-off-by: Richard Weinberger <[email protected]>
2024-04-30um: Add an internal header shared among the user codeTiwei Bie7-6/+26
Move relevant declarations to this header. This will address below -Wmissing-prototypes warnings: arch/um/os-Linux/elf_aux.c:26:13: warning: no previous prototype for ‘scan_elf_aux’ [-Wmissing-prototypes] arch/um/os-Linux/mem.c:213:13: warning: no previous prototype for ‘check_tmpexec’ [-Wmissing-prototypes] arch/um/os-Linux/skas/process.c:107:6: warning: no previous prototype for ‘wait_stub_done’ [-Wmissing-prototypes] Signed-off-by: Tiwei Bie <[email protected]> Signed-off-by: Richard Weinberger <[email protected]>
2024-04-30um: Fix the declaration of kasan_map_memoryTiwei Bie3-1/+3
Make it match its definition (size_t vs unsigned long). And declare it in a shared header to fix the -Wmissing-prototypes warning, as it is defined in the user code and called in the kernel code. Fixes: 5b301409e8bc ("UML: add support for KASAN under x86_64") Signed-off-by: Tiwei Bie <[email protected]> Signed-off-by: Richard Weinberger <[email protected]>
2024-04-30um: Fix the -Wmissing-prototypes warning for get_thread_regTiwei Bie2-1/+7
The get_thread_reg function is defined in the user code, and is called by the kernel code. It should be declared in a shared header. Fixes: dbba7f704aa0 ("um: stop polluting the namespace with registers.h contents") Signed-off-by: Tiwei Bie <[email protected]> Signed-off-by: Richard Weinberger <[email protected]>
2024-04-30um: Fix the -Wmissing-prototypes warning for __switch_mmTiwei Bie2-2/+2
The __switch_mm function is defined in the user code, and is called by the kernel code. It should be declared in a shared header. Fixes: 4dc706c2f292 ("um: take um_mmu.h to asm/mmu.h, clean asm/mmu_context.h a bit") Signed-off-by: Tiwei Bie <[email protected]> Signed-off-by: Richard Weinberger <[email protected]>
2024-04-30um: Fix -Wmissing-prototypes warnings for (rt_)sigreturnTiwei Bie1-2/+3
Use SYSCALL_DEFINE0 to define (rt_)sigreturn. This will address below -Wmissing-prototypes warnings: arch/x86/um/signal.c:453:6: warning: no previous prototype for ‘sys_sigreturn’ [-Wmissing-prototypes] arch/x86/um/signal.c:560:6: warning: no previous prototype for ‘sys_rt_sigreturn’ [-Wmissing-prototypes] Signed-off-by: Tiwei Bie <[email protected]> Signed-off-by: Richard Weinberger <[email protected]>
2024-04-30um: Stop tracking host PID in cpu_tasksTiwei Bie3-15/+2
The host PID tracked in 'cpu_tasks' is no longer used. Stopping tracking it will also save some cycles. Signed-off-by: Tiwei Bie <[email protected]> Signed-off-by: Richard Weinberger <[email protected]>
2024-04-30powerpc: Mark memory_limit as initdataMichael Ellerman1-1/+1
The `memory_limit` variable should only be used during boot, enforce that by marking it initdata. Signed-off-by: Michael Ellerman <[email protected]> Link: https://msgid.link/[email protected]
2024-04-30Merge tag 'cpufreq-arm-updates-6.10' of ↵Rafael J. Wysocki9-0/+158
git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm Merge ARM cpufreq updates for 6.10 from Viresh Kumar: "- Sun50i: Add support for opp_supported_hw, H616 platform and general cleaups (Andre Przywara, Martin Botka, Brandon Cheo Fusi, Dan Carpenter, and Viresh Kumar). - cppc: Fix possible null pointer dereference (Aleksandr Mishin). - Eliminate uses of of_node_put() (Javier Carrasco, and Shivani Gupta). - brcmstb-avs: ISO C90 forbids mixed declarations (Portia Stephens). - mediatek: Add support for MT7988A (Sam Shih). - cpufreq-qcom-hw: Add SM4450 compatibles in DT bindings (Tengfei Fan)." * tag 'cpufreq-arm-updates-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm: dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM4450 compatibles cpufreq: sun50i: fix error returns in dt_has_supported_hw() cpufreq: brcmstb-avs-cpufreq: ISO C90 forbids mixed declarations cpufreq: dt-platdev: eliminate uses of of_node_put() cpufreq: dt: eliminate uses of of_node_put() cpufreq: ti: Implement scope-based cleanup in ti_cpufreq_match_node() cpufreq: mediatek: Add support for MT7988A cpufreq: sun50i: Fix build warning around snprint() arm64: dts: allwinner: h616: enable DVFS for all boards arm64: dts: allwinner: h616: Add CPU OPPs table cpufreq: sun50i: Add H616 support cpufreq: sun50i: Add support for opp_supported_hw cpufreq: sun50i: Refactor speed bin decoding dt-bindings: opp: Describe H616 OPPs and opp-supported-hw cpufreq: dt-platdev: Blocklist Allwinner H616/618 SoCs firmware: smccc: Export revision soc_id function cppc_cpufreq: Fix possible null pointer dereference cpupfreq: tegra124: eliminate uses of of_node_put()
2024-04-30Merge tag 'arm-soc/for-6.10/devicetree-arm64' of ↵Arnd Bergmann2-1/+1
https://github.com/Broadcom/stblinux into soc/dt This pull request contains Broadcom ARM64-based SoCs Device Tree updates for 6.10, please pull the following: - Rafal moves the "brcm,wp-not-connected" property from the individual board DTSes to the SoC' DTSI since all boards a designed the same way * tag 'arm-soc/for-6.10/devicetree-arm64' of https://github.com/Broadcom/stblinux: arm64: dts: broadcom: bcmbca: bcm4908: set brcm,wp-not-connected Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-30Merge tag 'arm-soc/for-6.10/devicetree' of ↵Arnd Bergmann14-111/+567
https://github.com/Broadcom/stblinux into soc/dt This pull request contains Broadcom ARM-based SoCs Device Tree changes for 6.10, please pull the following: - Laurent converts the Raspberry Pi firmware DT binding to YAML, updates the firmware driver to use the proper 'struct device' reference for DMA mappings and drops unneeded properties from the DT node and finishes by removing the duplicate firmware-clocks property to bcm2835-rpi.dtsi. He also added support for the CAM1 camera interface regulator. - Uwe adds a pinctrl-based multiplexing description to allow the use of I2C0 pins to allow usage between the 40-pin Raspberry Pi header and the CSI and DSI connectors. He then describes the PCF85063 RTC device available on the CM4 I/O board making use of that pinctrl-based muxing. - Arinc updates the Asus RT-AC3100 and RT-AC88U DTs to have proper LED colors and function properties, NVMEM MAC addresses and removes duplicates and unnecessary properties and does a few Device Tree cleanups.. He then adds support for the Asus RT-AC3200 (BCM4709-based) and RT-AC3500 routers. - Jean-Michel adds DT nodes for the CSI Unicam camera interfaces on the Raspberry Pi 4 / BCM2711 SoCs - Florian adds support for the Ethernet LEDs on Raspberry Pi 4 B and Raspberry Pi 4 CM boards. * tag 'arm-soc/for-6.10/devicetree' of https://github.com/Broadcom/stblinux: arm: dts: bcm2711: Describe Ethernet LEDs ARM: dts: BCM5301X: Conform to DTS Coding Style on ASUS RT-AC3100 & AC88U ARM: dts: BCM5301X: Add DT for ASUS RT-AC5300 ARM: dts: BCM5301X: Add DT for ASUS RT-AC3200 dt-bindings: arm: bcm: add bindings for ASUS RT-AC5300 dt-bindings: arm: bcm: add bindings for ASUS RT-AC3200 ARM: dts: bcm2835: Add Unicam CSI nodes ARM: dts: BCM5301X: remove earlycon on ASUS RT-AC3100 and ASUS RT-AC88U ARM: dts: BCM5301X: remove duplicate compatible on ASUS RT-AC3100 & AC88U ARM: dts: BCM5301X: provide address for SoC MACs on ASUS RT-AC3100 & AC88U ARM: dts: BCM5301X: use color and function on ASUS RT-AC3100 and RT-AC88U ARM: dts: bcm2711-rpi-4-b: Add CAM1 regulator ARM: dts: bcm2711-rpi-cm4-io: Add RTC on I2C0 ARM: dts: bcm2711-rpi: Add pinctrl-based multiplexing for I2C0 ARM: dts: bcm2835-rpi: Move duplicate firmware-clocks to bcm2835-rpi.dtsi ARM: dts: bcm283x: Drop unneeded properties in the bcm2835-firmware node firmware: raspberrypi: Use correct device for DMA mappings dt-bindings: arm: bcm: raspberrypi,bcm2835-firmware: Add gpio child node Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-30Merge tag 'arm-soc/for-6.10/defconfig-arm64' of ↵Arnd Bergmann1-0/+1
https://github.com/Broadcom/stblinux into soc/defconfig This pull request contains updates to the ARM64 defconfig file for 6.10, please pull the following: - Stefan enables the snd_bcm2835 module build to mimic what is done in bcm2835_defconfig and improve build coverage and testing * tag 'arm-soc/for-6.10/defconfig-arm64' of https://github.com/Broadcom/stblinux: arm64: defconfig: build snd_bcm2835 as module Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-30Merge tag 'renesas-arm-defconfig-for-v6.10-tag1' of ↵Arnd Bergmann2-1/+8
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/defconfig Renesas ARM defconfig updates for v6.10 - Enable support for the Renesas RZ/G2L display unit, DA9062 PMIC, and RZ/V2H (R9A09G057) SoC in the ARM64 defconfig, - Refresh shmobile_defconfig for v6.9-rc1. * tag 'renesas-arm-defconfig-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: ARM: shmobile: defconfig: Refresh for v6.9-rc1 arm64: defconfig: Enable R9A09G057 SoC arm64: defconfig: Enable Renesas DA9062 PMIC arm64: defconfig: Enable Renesas RZ/G2L display unit DRM driver Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-30x86/apic: Don't access the APIC when disabling x2APICThomas Gleixner1-5/+11
With 'iommu=off' on the kernel command line and x2APIC enabled by the BIOS the code which disables the x2APIC triggers an unchecked MSR access error: RDMSR from 0x802 at rIP: 0xffffffff94079992 (native_apic_msr_read+0x12/0x50) This is happens because default_acpi_madt_oem_check() selects an x2APIC driver before the x2APIC is disabled. When the x2APIC is disabled because interrupt remapping cannot be enabled due to 'iommu=off' on the command line, x2apic_disable() invokes apic_set_fixmap() which in turn tries to read the APIC ID. This triggers the MSR warning because x2APIC is disabled, but the APIC driver is still x2APIC based. Prevent that by adding an argument to apic_set_fixmap() which makes the APIC ID read out conditional and set it to false from the x2APIC disable path. That's correct as the APIC ID has already been read out during early discovery. Fixes: d10a904435fa ("x86/apic: Consolidate boot_cpu_physical_apicid initialization sites") Reported-by: Adrian Huang <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Signed-off-by: Ingo Molnar <[email protected]> Tested-by: Adrian Huang <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/875xw5t6r7.ffs@tglx
2024-04-29arm64: defconfig: select INTERCONNECT_QCOM_SM6115 as built-inDmitry Baryshkov1-0/+1
Enable CONFIG_INTERCONNECT_QCOM_SM6115 as built-in to enable the interconnect driver for the SoC used on Qualcomm Robotics RB2 board. Building as built-in is required as on this platform interconnects are required to bring up the console. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-04-30iommu/vt-d: Make posted MSI an opt-in command line optionJacob Pan1-0/+7
Add a command line opt-in option for posted MSI if CONFIG_X86_POSTED_MSI=y. Also introduce a helper function for testing if posted MSI is supported on the platform. Signed-off-by: Jacob Pan <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-04-30x86/irq: Extend checks for pending vectors to posted interruptsJacob Pan2-1/+20
During interrupt affinity change, it is possible to have interrupts delivered to the old CPU after the affinity has changed to the new one. To prevent lost interrupts, local APIC IRR is checked on the old CPU. Similar checks must be done for posted MSIs given the same reason. Consider the following scenario: Device system agent iommu memory CPU/LAPIC 1 FEEX_XXXX 2 Interrupt request 3 Fetch IRTE -> 4 ->Atomic Swap PID.PIR(vec) Push to Global Observable(GO) 5 if (ON*) done;* else 6 send a notification -> * ON: outstanding notification, 1 will suppress new notifications If the affinity change happens between 3 and 5 in the IOMMU, the old CPU's posted interrupt request (PIR) could have the pending bit set for the vector being moved. Add a helper function to check individual vector status. Then use the helper to check for pending interrupts on the source CPU's PID. Signed-off-by: Jacob Pan <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-04-30x86/irq: Factor out common code for checking pending interruptsJacob Pan3-6/+15
Use a common function for checking pending interrupt vector in APIC IRR instead of duplicated open coding them. Additional checks for posted MSI vectors can then be contained in this function. Signed-off-by: Jacob Pan <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-04-30x86/irq: Install posted MSI notification handlerJacob Pan5-4/+135
All MSI vectors are multiplexed into a single notification vector when posted MSI is enabled. It is the responsibility of the notification vector handler to demultiplex MSI vectors. In the handler the MSI vector handlers are dispatched without IDT delivery for each pending MSI interrupt. For example, the interrupt flow will change as follows: (3 MSIs of different vectors arrive in a a high frequency burst) BEFORE: interrupt(MSI) irq_enter() handler() /* EOI */ irq_exit() process_softirq() interrupt(MSI) irq_enter() handler() /* EOI */ irq_exit() process_softirq() interrupt(MSI) irq_enter() handler() /* EOI */ irq_exit() process_softirq() AFTER: interrupt /* Posted MSI notification vector */ irq_enter() atomic_xchg(PIR) handler() handler() handler() pi_clear_on() apic_eoi() irq_exit() process_softirq() Except for the leading MSI, CPU notifications are skipped/coalesced. For MSIs which arrive at a low frequency, the demultiplexing loop does not wait for more interrupts to coalesce. Therefore, there's no additional latency other than the processing time. Signed-off-by: Jacob Pan <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-04-30x86/irq: Factor out handler invocation from common_interrupt()Jacob Pan1-9/+14
Prepare for calling external interrupt handlers directly from the posted MSI demultiplexing loop. Extract the common code from common_interrupt() to avoid code duplication. Signed-off-by: Jacob Pan <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-04-30x86/irq: Set up per host CPU posted interrupt descriptorsJacob Pan4-0/+35
To support posted MSIs, create a posted interrupt descriptor (PID) for each host CPU. Later on, when setting up interrupt affinity, the IOMMU's interrupt remapping table entry (IRTE) will point to the physical address of the matching CPU's PID. Each PID is initialized with the owner CPU's physical APICID as the destination. Originally-by: Thomas Gleixner <[email protected]> Signed-off-by: Jacob Pan <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-04-30x86/irq: Reserve a per CPU IDT vector for posted MSIsJacob Pan1-1/+7
When posted MSI is enabled, all device MSIs are multiplexed into a single notification vector. MSI handlers will be de-multiplexed at run-time by system software without IDT delivery. Signed-off-by: Jacob Pan <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-04-30x86/irq: Add a Kconfig option for posted MSIJacob Pan1-0/+11
This option will be used to support delivering MSIs as posted interrupts. Interrupt remapping is required. Signed-off-by: Jacob Pan <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-04-30x86/irq: Remove bitfields in posted interrupt descriptorJacob Pan3-12/+15
Mixture of bitfields and types is weird and really not intuitive, remove bitfields and use typed data exclusively. Bitfields often result in inferior machine code. Suggested-by: Sean Christopherson <[email protected]> Suggested-by: Thomas Gleixner <[email protected]> Signed-off-by: Jacob Pan <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/all/20240404101735.402feec8@jacob-builder/T/#mf66e34a82a48f4d8e2926b5581eff59a122de53a
2024-04-30x86/irq: Unionize PID.PIR for 64bit access w/o castingJacob Pan1-1/+4
Make the PIR field into u64 such that atomic xchg64 can be used without ugly casting. Suggested-by: Thomas Gleixner <[email protected]> Signed-off-by: Jacob Pan <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-04-30KVM: VMX: Move posted interrupt descriptor out of VMX codeJacob Pan4-93/+91
To prepare native usage of posted interrupts, move the PID declarations out of VMX code such that they can be shared. Signed-off-by: Jacob Pan <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Acked-by: Sean Christopherson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-04-29x86/tsc: Trust initial offset in architectural TSC-adjust MSRsDaniel J Blueman1-4/+2
When the BIOS configures the architectural TSC-adjust MSRs on secondary sockets to correct a constant inter-chassis offset, after Linux brings the cores online, the TSC sync check later resets the core-local MSR to 0, triggering HPET fallback and leading to performance loss. Fix this by unconditionally using the initial adjust values read from the MSRs. Trusting the initial offsets in this architectural mechanism is a better approach than special-casing workarounds for specific platforms. Signed-off-by: Daniel J Blueman <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Steffen Persvold <[email protected]> Reviewed-by: James Cleverdon <[email protected]> Reviewed-by: Dimitri Sivanich <[email protected]> Reviewed-by: Prarit Bhargava <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-04-29Merge tag 'stm32-bus-firewall-for-v6.10-1' of ↵Arnd Bergmann2-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/drivers STM32 Firewall bus for v6.10, round 1 Highlights: --------- Introduce STM32 Firewall framework for STM32MP1x and STM32MP2x platforms. STM32MP1x(ETZPC) and STM32MP2x(RIFSC) Firewall controllers register to the framework to offer firewall services such as access granting. This series of patches is a new approach on the previous STM32 system bus, history is available here: https://lore.kernel.org/lkml/20230127164040.1047583/ The need for such framework arises from the fact that there are now multiple hardware firewalls implemented across multiple products. Drivers are shared between different products, using the same code. When it comes to firewalls, the purpose mostly stays the same: Protect hardware resources. But the implementation differs, and there are multiple types of firewalls: peripheral, memory, ... Some hardware firewall controllers such as the RIFSC implemented on STM32MP2x platforms may require to take ownership of a resource before being able to use it, hence the requirement for firewall services to take/release the ownership of such resources. On the other hand, hardware firewall configurations are becoming more and more complex. These mecanisms prevent platform crashes or other firewall-related incoveniences by denying access to some resources. The stm32 firewall framework offers an API that is defined in firewall controllers drivers to best fit the specificity of each firewall. For every peripherals protected by either the ETZPC or the RIFSC, the firewall framework checks the firewall controlelr registers to see if the peripheral's access is granted to the Linux kernel. If not, the peripheral is configured as secure, the node is marked populated, so that the driver is not probed for that device. The firewall framework relies on the access-controller device tree binding. It is used by peripherals to reference a domain access controller. In this case a firewall controller. The bus uses the ID referenced by the access-controller property to know where to look in the firewall to get the security configuration for the peripheral. This allows a device tree description rather than a hardcoded peripheral table in the bus driver. The STM32 ETZPC device is responsible for filtering accesses based on security level, or co-processor isolation for any resource connected to it. The RIFSC is responsible for filtering accesses based on Compartment ID / security level / privilege level for any resource connected to it. * tag 'stm32-bus-firewall-for-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: bus: stm32_firewall: fix off by one in stm32_firewall_get_firewall() bus: etzpc: introduce ETZPC firewall controller driver bus: rifsc: introduce RIFSC firewall controller driver of: property: fw_devlink: Add support for "access-controller" firewall: introduce stm32_firewall framework dt-bindings: bus: document ETZPC dt-bindings: bus: document RIFSC dt-bindings: treewide: add access-controllers description dt-bindings: document generic access controllers Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29Merge tag 'imx-soc-6.10' of ↵Arnd Bergmann1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/arm i.MX SoC changes for 6.10: - Assign the pmu->dev parent to be the platform device for MMDC driver, so that it doesn't appear directly under /sys/devices/. * tag 'imx-soc-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: imx: Assign parents for mmdc event_source devices Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29Merge tag 'for-netdev' of ↵Jakub Kicinski5-13/+372
https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next Daniel Borkmann says: ==================== pull-request: bpf-next 2024-04-29 We've added 147 non-merge commits during the last 32 day(s) which contain a total of 158 files changed, 9400 insertions(+), 2213 deletions(-). The main changes are: 1) Add an internal-only BPF per-CPU instruction for resolving per-CPU memory addresses and implement support in x86 BPF JIT. This allows inlining per-CPU array and hashmap lookups and the bpf_get_smp_processor_id() helper, from Andrii Nakryiko. 2) Add BPF link support for sk_msg and sk_skb programs, from Yonghong Song. 3) Optimize x86 BPF JIT's emit_mov_imm64, and add support for various atomics in bpf_arena which can be JITed as a single x86 instruction, from Alexei Starovoitov. 4) Add support for passing mark with bpf_fib_lookup helper, from Anton Protopopov. 5) Add a new bpf_wq API for deferring events and refactor sleepable bpf_timer code to keep common code where possible, from Benjamin Tissoires. 6) Fix BPF_PROG_TEST_RUN infra with regards to bpf_dummy_struct_ops programs to check when NULL is passed for non-NULLable parameters, from Eduard Zingerman. 7) Harden the BPF verifier's and/or/xor value tracking, from Harishankar Vishwanathan. 8) Introduce crypto kfuncs to make BPF programs able to utilize the kernel crypto subsystem, from Vadim Fedorenko. 9) Various improvements to the BPF instruction set standardization doc, from Dave Thaler. 10) Extend libbpf APIs to partially consume items from the BPF ringbuffer, from Andrea Righi. 11) Bigger batch of BPF selftests refactoring to use common network helpers and to drop duplicate code, from Geliang Tang. 12) Support bpf_tail_call_static() helper for BPF programs with GCC 13, from Jose E. Marchesi. 13) Add bpf_preempt_{disable,enable}() kfuncs in order to allow a BPF program to have code sections where preemption is disabled, from Kumar Kartikeya Dwivedi. 14) Allow invoking BPF kfuncs from BPF_PROG_TYPE_SYSCALL programs, from David Vernet. 15) Extend the BPF verifier to allow different input maps for a given bpf_for_each_map_elem() helper call in a BPF program, from Philo Lu. 16) Add support for PROBE_MEM32 and bpf_addr_space_cast instructions for riscv64 and arm64 JITs to enable BPF Arena, from Puranjay Mohan. 17) Shut up a false-positive KMSAN splat in interpreter mode by unpoison the stack memory, from Martin KaFai Lau. 18) Improve xsk selftest coverage with new tests on maximum and minimum hardware ring size configurations, from Tushar Vyavahare. 19) Various ReST man pages fixes as well as documentation and bash completion improvements for bpftool, from Rameez Rehman & Quentin Monnet. 20) Fix libbpf with regards to dumping subsequent char arrays, from Quentin Deslandes. * tag 'for-netdev' of https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next: (147 commits) bpf, docs: Clarify PC use in instruction-set.rst bpf_helpers.h: Define bpf_tail_call_static when building with GCC bpf, docs: Add introduction for use in the ISA Internet Draft selftests/bpf: extend BPF_SOCK_OPS_RTT_CB test for srtt and mrtt_us bpf: add mrtt and srtt as BPF_SOCK_OPS_RTT_CB args selftests/bpf: dummy_st_ops should reject 0 for non-nullable params bpf: check bpf_dummy_struct_ops program params for test runs selftests/bpf: do not pass NULL for non-nullable params in dummy_st_ops selftests/bpf: adjust dummy_st_ops_success to detect additional error bpf: mark bpf_dummy_struct_ops.test_1 parameter as nullable selftests/bpf: Add ring_buffer__consume_n test. bpf: Add bpf_guard_preempt() convenience macro selftests: bpf: crypto: add benchmark for crypto functions selftests: bpf: crypto skcipher algo selftests bpf: crypto: add skcipher to bpf crypto bpf: make common crypto API for TC/XDP programs bpf: update the comment for BTF_FIELDS_MAX selftests/bpf: Fix wq test. selftests/bpf: Use make_sockaddr in test_sock_addr selftests/bpf: Use connect_to_addr in test_sock_addr ... ==================== Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-04-29arm64: dts: ti: k3-am625-beagleplay: Fix Ethernet PHY RESET GPIOsRoger Quadros1-2/+6
The RESET GPIO pinmux should be part of MDIO bus node so that they can be in the right state before the PHY can be probed via MDIO bus scan. The GPIO pin should be setup with PIN_INPUT so that input circuitry is enabled in case software wants to check pin status. Without this, incorrect status is shown in /sys/kernel/debug/gpio. Add GPIO reset for the Gigabit Ethernet PHY. As per RTL8211F datasheet, reset assert width is 10ms and PHY registers can be access accessed after 50ms of reset deassert. Fixes: f5a731f0787f ("arm64: dts: ti: Add k3-am625-beagleplay") Signed-off-by: Roger Quadros <[email protected]> Link: https://lore.kernel.org/r/20240305-b4-for-v6-9-am65-beagleplay-ethernet-reset-v2-1-2bf463a7bf13@kernel.org Signed-off-by: Nishanth Menon <[email protected]>
2024-04-29Merge tag 'imx-defconfig-6.10' of ↵Arnd Bergmann2-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/defconfig i.MX defconfig changes for 6.10: - Enable DW HDMI bridge driver for i.MX8M Plus SoC in arm64 defconfig - Enable ONBOAD_USB_DEV driver in imx_v6_v7_defconfig to support USB2514 Hub found on imx6qdl-udoo board * tag 'imx-defconfig-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: imx_v6_v7_defconfig: Update ONBOARD_USB_HUB to ONBOAD_USB_DEV ARM: imx_v6_v7_defconfig: Select CONFIG_USB_ONBOARD_HUB arm64: defconfig: Enable DRM_IMX8MP_DW_HDMI_BRIDGE as module Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29Merge tag 'qcom-arm64-defconfig-for-6.10' of ↵Arnd Bergmann1-0/+8
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/defconfig Qualcomm Arm64 Defconfig updates for v6.10 Ext4 security labels are enabled, as the expectation of setcap being functional is widespread. SC7280 display and GPU clock controllers are enabled, to make available related functionality. The driver for the Novatek display panel found in QCM6490 IDP is enabled. The X1E80100 sound card and reset-gpio drivers are enabled to provide the necessary drivers for this. The regulator driver providing VBUS power on a few different platforms is enabled. ath12k is present on several recent platforms, so this is enabled as well. * tag 'qcom-arm64-defconfig-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: arm64: defconfig: enable REGULATOR_QCOM_USB_VBUS arm64: defconfig: enable ext4 security labels arm64: defconfig: qcom: enable X1E80100 sound card arm64: defconfig: build ath12k as a module arm64: defconfig: Enable sc7280 display and gpu clock controllers arm64: defconfig: enable reset-gpio driver as module arm64: defconfig: enable Novatek NT36672E DSI Panel driver Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29Merge tag 'tegra-for-6.10-arm64-defconfig' of ↵Arnd Bergmann1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/defconfig arm64: tegra: Default configuration updates for v6.10-rc1 Enables the Security Engine driver for the corresponding devices found on Tegra234. * tag 'tegra-for-6.10-arm64-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: defconfig: Enable Tegra Security Engine Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29Merge tag 'sunxi-config-for-6.10-1' of ↵Arnd Bergmann1-0/+1
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/defconfig - add dependency for DRM_SUN8I_DW_HDMI in sunxi defconfig * tag 'sunxi-config-for-6.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: ARM: configs: sunxi: Enable DRM_DW_HDMI Link: https://lore.kernel.org/r/20240426164354.GA101098@jernej-laptop Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Add USB-CGarrett Giordano1-1/+25
The USB-C PD manages plug orientation, power delivery, and our endpoint for the USB interface. Add this node and include its endpoint. Configure USB0 for role-switching and wire it to our USB-C PD endpoint. Signed-off-by: Garrett Giordano <[email protected]> Reviewed-by: Wadim Egorov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Nishanth Menon <[email protected]>
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