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2024-05-28arm64: dts: qcom: sm8450: Add interconnect path to PCIe nodeKrishna chaitanya chundru1-0/+12
Add PCIe-MEM & CPU-PCIe interconnect path to the PCIe nodes. Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krishna chaitanya chundru <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: qcom: sa8775p: mark ethernet devices as DMA-coherentSagar Cheluvegowda1-0/+2
Ethernet devices are cache coherent, mark it as such in the dtsi. Fixes: ff499a0fbb23 ("arm64: dts: qcom: sa8775p: add the first 1Gb ethernet interface") Fixes: e952348a7cc7 ("arm64: dts: qcom: sa8775p: add a node for EMAC1") Signed-off-by: Sagar Cheluvegowda <[email protected]> Link: https://lore.kernel.org/r/20240514-mark_ethernet_devices_dma_coherent-v4-1-04e1198858c5@quicinc.com Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: qcom: msm8998: set qcom,no-msa-ready-indicator for wifiMarc Gonzalez1-0/+1
The ath10k driver waits for an "MSA_READY" indicator to complete initialization. If the indicator is not received, then the device remains unusable. cf. ath10k_qmi_driver_event_work() Several msm8998-based devices are affected by this issue. Oddly, it seems safe to NOT wait for the indicator, and proceed immediately when QMI_EVENT_SERVER_ARRIVE. Jeff Johnson wrote: The feedback I received was "it might be ok to change all ath10k qmi to skip waiting for msa_ready", and it was pointed out that ath11k (and ath12k) do not wait for it. However with so many deployed devices, "might be ok" isn't a strong argument for changing the default behavior. cf. also https://wiki.postmarketos.org/wiki/Qualcomm_Snapdragon_835_(MSM8998)#WLAN Signed-off-by: Marc Gonzalez <[email protected]> Acked-by: Jeff Johnson <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: qcom: sdm632-fairphone-fp3: Enable vibratorLuca Weiss1-0/+4
Enable the vibrator on the PMI632 which is used on this phone. Signed-off-by: Luca Weiss <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: qcom: pmi632: Add vibratorLuca Weiss1-0/+6
Add a node for the vibrator module found inside the PMI632. Signed-off-by: Luca Weiss <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: qcom: Split PMU nodes for heterogeneous CPUsRob Herring (Arm)6-14/+60
Arm heterogeneous configurations should have separate PMU nodes for each CPU uarch as the uarch specific events can be different. The "arm,armv8-pmuv3" compatible is also intended for s/w models rather than specific uarch implementations. All the kryo CPUs are missing PMU compatibles, so they can't be fixed. Signed-off-by: "Rob Herring (Arm)" <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28perf/x86/rapl: Switch to new Intel CPU model definesTony Luck1-45/+45
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Link: https://lore.kernel.org/all/20240520224620.9480-44-tony.luck%40intel.com
2024-05-28x86/boot: Switch to new Intel CPU model definesTony Luck1-1/+1
New CPU #defines encode vendor and family as well as model but boot code doesn't have all the infrastructure to use them. Hard code the one CPU model number used here. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Link: https://lore.kernel.org/all/20240520224620.9480-35-tony.luck%40intel.com
2024-05-28x86/cpu: Switch to new Intel CPU model definesTony Luck2-36/+36
New CPU #defines encode vendor and family as well as model. Update INTEL_CPU_DESC() to work with vendor/family/model. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Link: https://lore.kernel.org/all/20240520224620.9480-34-tony.luck%40intel.com
2024-05-28perf/x86/intel: Switch to new Intel CPU model definesTony Luck1-74/+74
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Link: https://lore.kernel.org/all/20240520224620.9480-32-tony.luck%40intel.com
2024-05-28x86/virt/tdx: Switch to new Intel CPU model definesTony Luck1-4/+4
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Link: https://lore.kernel.org/all/20240520224620.9480-31-tony.luck%40intel.com
2024-05-28x86/PCI: Switch to new Intel CPU model definesTony Luck1-2/+2
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Link: https://lore.kernel.org/all/20240520224620.9480-30-tony.luck%40intel.com
2024-05-28x86/cpu/intel: Switch to new Intel CPU model definesTony Luck1-55/+53
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Link: https://lore.kernel.org/all/20240520224620.9480-29-tony.luck%40intel.com
2024-05-28x86/platform/intel-mid: Switch to new Intel CPU model definesTony Luck1-3/+3
New CPU #defines encode vendor and family as well as model. N.B. Drop Haswell. CPU model 0x3C was included by mistake in upstream code. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Acked-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/all/20240521161002.12866-1-tony.luck%40intel.com
2024-05-29arm64: dts: allwinner: Add cache information to the SoC dtsi for A64Dragan Simic1-5/+32
Add missing cache information to the Allwinner A64 SoC dtsi, to allow the userspace, which includes lscpu(1) that uses the virtual files provided by the kernel under the /sys/devices/system/cpu directory, to display the proper A64 cache information. While there, use a more self-descriptive label for the L2 cache node, which also makes it more consistent with other SoC dtsi files. The cache parameters for the A64 dtsi were obtained and partially derived by hand from the cache size and layout specifications found in the following datasheets and technical reference manuals: - Allwinner A64 datasheet, version 1.1 - ARM Cortex-A53 revision r0p3 TRM, version E For future reference, here's a brief summary of the documentation: - All caches employ the 64-byte cache line length - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction cache and 32 KB of L1 4-way, set-associative data cache - The entire SoC has 512 KB of unified L2 16-way, set-associative cache Signed-off-by: Dragan Simic <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Link: https://lore.kernel.org/r/6a772756c2c677dbdaaab4a2c71a358d8e4b27e9.1714304058.git.dsimic@manjaro.org Signed-off-by: Chen-Yu Tsai <[email protected]>
2024-05-29arm64: dts: allwinner: Correct the model names for Pine64 boardsDragan Simic9-9/+9
Correct the model names of a few Pine64 boards and devices, according to their official names used in the Pine64 wiki and on the official Pine64 website. [1][2][3] This ensures consistency between the officially used names and the names in the source code. [1] https://wiki.pine64.org/wiki/PINE_A64 [2] https://wiki.pine64.org/wiki/PINE_H64 [3] https://pine64.org/devices/ Acked-by: Jernej Skrabec <[email protected]> Cc: Marek Kraus <[email protected]> Signed-off-by: Dragan Simic <[email protected]> Link: https://lore.kernel.org/r/4a988518e0dba5de3ecfc172a0fa2b0653c00d8b.1716768092.git.dsimic@manjaro.org Signed-off-by: Chen-Yu Tsai <[email protected]>
2024-05-29arm64: dts: allwinner: Add cache information to the SoC dtsi for H6Dragan Simic1-0/+37
Add missing cache information to the Allwinner H6 SoC dtsi, to allow the userspace, which includes lscpu(1) that uses the virtual files provided by the kernel under the /sys/devices/system/cpu directory, to display the proper H6 cache information. Adding the cache information to the H6 SoC dtsi also makes the following warning message in the kernel log go away: cacheinfo: Unable to detect cache hierarchy for CPU 0 The cache parameters for the H6 dtsi were obtained and partially derived by hand from the cache size and layout specifications found in the following datasheets and technical reference manuals: - Allwinner H6 V200 datasheet, version 1.1 - ARM Cortex-A53 revision r0p3 TRM, version E For future reference, here's a brief summary of the documentation: - All caches employ the 64-byte cache line length - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction cache and 32 KB of L1 4-way, set-associative data cache - The entire SoC has 512 KB of unified L2 16-way, set-associative cache Signed-off-by: Dragan Simic <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Link: https://lore.kernel.org/r/49abb93000078c692c48c0a65ff677893909361a.1714304071.git.dsimic@manjaro.org Signed-off-by: Chen-Yu Tsai <[email protected]>
2024-05-29ARM: dts: sun50i: Add LRADC nodeJames McGregor1-0/+10
Add a DT node for the Allwinner H616 LRADC describing the base address, interrupt, reset and clock gates. Signed-off-by: James McGregor <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Škrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2024-05-28ARM: dts: qcom: msm8974: Use proper compatible for APCS sysconLuca Weiss1-2/+4
Use the apcs-kpss-global compatible for the APCS global mailbox block found on this SoC. This also resolves a dt-binding checker warning: arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dtb: syscon@f9011000: compatible: 'anyOf' conditional failed, one must be fixed: ['syscon'] is too short 'syscon' is not one of ['allwinner,sun8i-a83t-system-controller', 'allwinner,sun8i-h3-system-controller', 'allwinner,sun8i-v3s-system-controller', 'allwinner,sun50i-a64-system-controller', 'amd,pensando-elba-syscon', 'brcm,cru-clkset', 'freecom,fsg-cs2-system-controller', 'fsl,imx93-aonmix-ns-syscfg', 'fsl,imx93-wakeupmix-syscfg', 'hisilicon,dsa-subctrl', 'hisilicon,hi6220-sramctrl', 'hisilicon,pcie-sas-subctrl', 'hisilicon,peri-subctrl', 'hpe,gxp-sysreg', 'intel,lgm-syscon', 'loongson,ls1b-syscon', 'loongson,ls1c-syscon', 'marvell,armada-3700-usb2-host-misc', 'mediatek,mt8135-pctl-a-syscfg', 'mediatek,mt8135-pctl-b-syscfg', 'mediatek,mt8365-syscfg', 'microchip,lan966x-cpu-syscon', 'microchip,sparx5-cpu-syscon', 'mstar,msc313-pmsleep', 'nuvoton,ma35d1-sys', 'nuvoton,wpcm450-shm', 'rockchip,px30-qos', 'rockchip,rk3036-qos', 'rockchip,rk3066-qos', 'rockchip,rk3128-qos', 'rockchip,rk3228-qos', 'rockchip,rk3288-qos', 'rockchip,rk3368-qos', 'rockchip,rk3399-qos', 'rockchip,rk356 8-qos', 'rockchip,rk3588-qos', 'rockchip,rv1126-qos', 'starfive,jh7100-sysmain', 'ti,am62-usb-phy-ctrl', 'ti,am654-dss-oldi-io-ctrl', 'ti,am654-serdes-ctrl', 'ti,j784s4-pcie-ctrl'] from schema $id: http://devicetree.org/schemas/mfd/syscon.yaml# Signed-off-by: Luca Weiss <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28x86/pconfig: Remove unused MKTME pconfig codeAlison Schofield3-150/+1
Code supporting Intel PCONFIG targets was an early piece of enabling for MKTME (Multi-Key Total Memory Encryption). Since MKTME feature enablement did not follow into the kernel, remove the unused PCONFIG code. Signed-off-by: Alison Schofield <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Acked-by: Kirill A. Shutemov <[email protected]> Acked-by: Kai Huang <[email protected]> Link: https://lore.kernel.org/all/4ddff30d466785b4adb1400f0518783012835141.1715054189.git.alison.schofield%40intel.com
2024-05-28x86/cpu: Remove useless work in detect_tme_early()Alison Schofield1-60/+12
TME (Total Memory Encryption) and MKTME (Multi-Key Total Memory Encryption) BIOS detection were introduced together here [1] and are loosely coupled in the Intel CPU init code. TME is a hardware only feature and its BIOS status is all that needs to be shared with the kernel user: enabled or disabled. The TME algorithm the BIOS is using and whether or not the kernel recognizes that algorithm is useless to the kernel user. MKTME is a hardware feature that requires kernel support. MKTME detection code was added in advance of broader kernel support for MKTME that never followed. So, rather than continuing to spew needless and confusing messages about BIOS MKTME status, remove most of the MKTME pieces from detect_tme_early(). Keep one useful message: alert the user when BIOS enabled MKTME reduces the available physical address bits. Recovery of the MKTME consumed bits requires a reboot with MKTME disabled in BIOS. There is no functional change for the user, only a change in boot messages. Below is one example when both TME and MKTME are enabled in BIOS with AES_XTS_256 which is unknown to the detect tme code. Before: [] x86/tme: enabled by BIOS [] x86/tme: Unknown policy is active: 0x2 [] x86/mktme: No known encryption algorithm is supported: 0x4 [] x86/mktme: enabled by BIOS [] x86/mktme: 127 KeyIDs available After: [] x86/tme: enabled by BIOS [] x86/mktme: BIOS enable: x86_phys_bits reduced by 8 [1] commit cb06d8e3d020 ("x86/tme: Detect if TME and MKTME is activated by BIOS") Signed-off-by: Alison Schofield <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Acked-by: Kirill A. Shutemov <[email protected]> Link: https://lore.kernel.org/all/86dfdf6ced8c9b790f9376bf6c7e22b5608f47c2.1715054189.git.alison.schofield%40intel.com
2024-05-28arm64: dts: qcom: qcs404: Use qcs404-hfpll compatible for hfpllLuca Weiss1-1/+1
Follow the updated bindings and use a QCS404-specific compatible for the HFPLL on this SoC. Signed-off-by: Luca Weiss <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28ARM: dts: qcom: msm8974-hammerhead: Update gpio hog node nameLuca Weiss1-1/+1
Follow the gpio-hog bindings and use otg-hog as node name. Signed-off-by: Luca Weiss <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: qcom: Add Motorola Moto G 2015 (osprey)Martijn Braam2-0/+106
Motorola Moto G 2015 is an msm8916 based smartphone. Supported features: - eMMC and SD; - Buttons; - Touchscreen; - USB; - Fuel Gauge; - Sound. Signed-off-by: Martijn Braam <[email protected]> Signed-off-by: Stephan Gerhold <[email protected]> [Nikita: Use common dtsi] Signed-off-by: Nikita Travkin <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: qcom: Add Motorola Moto E 2015 LTE (surnia)Wiktor Strzębała2-0/+84
Motorola Moto E 2015 LTE is an msm8916 based smartphone. Supported features: - eMMC and SD; - Buttons; - Touchscreen; - USB; - Fuel Gauge; - Sound. Signed-off-by: Wiktor Strzębała <[email protected]> [Valérie: Sound and modem] Co-developed-by: Valérie Roux <[email protected]> Signed-off-by: Valérie Roux <[email protected]> Signed-off-by: Stephan Gerhold <[email protected]> [Nikita: Use common dtsi] Signed-off-by: Nikita Travkin <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: qcom: Add device tree for Motorola Moto G4 Play (harpia)Ruby Iris Juric3-0/+309
Motorola Moto G4 Play is an msm8916 based smartphone. Supported features: - eMMC and SD; - Buttons; - Touchscreen; - USB; - Fuel Gauge; - Sound; - Accelerometer. msm8916 Moto devices share significant portion of the design so the common parts are separated into a common dtsi. Signed-off-by: Ruby Iris Juric <[email protected]> Signed-off-by: Stephan Gerhold <[email protected]> [Nikita: Split up to common dtsi] Signed-off-by: Nikita Travkin <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: qcom: msm8916-samsung-rossa: Add LIS2HH12 accelerometerRaymond Hackley1-0/+8
Core Prime LTE uses ST LIS2HH12 accelerometer. Add support for it. [Stephen: Use common &st_accel definition from common dtsi] Signed-off-by: Stephan Gerhold <[email protected]> Signed-off-by: Raymond Hackley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: qcom: msm8916-samsung-fortuna: Add LSM303C ↵Siddharth Manthan2-0/+41
accelerometer/magnetometer Some Grand Prime use a ST LSM303C accelerometer/magnetometer combo. Add support for it. Signed-off-by: Siddharth Manthan <[email protected]> [Stephan: Move sensors to common dtsi (disabled by default)] Signed-off-by: Stephan Gerhold <[email protected]> [Raymond: Use interrupts-extended] Signed-off-by: Raymond Hackley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: qcom: msm8916-samsung-fortuna: Add BMC150 accelerometer/magnetometerJoe Mason3-0/+60
Some Grand Prime use a Bosch BMC150 accelerometer/magnetometer combo. The chip provides two separate I2C devices for the accelerometer and magnetometer that are already supported by the bmc150-accel and bmc150-magn driver. Signed-off-by: Joe Mason <[email protected]> [Stephan: Move sensors to common dtsi, disabled by default] Signed-off-by: Stephan Gerhold <[email protected]> [Raymond: Add it to grandprimelte. Use interrupts-extended] Signed-off-by: Raymond Hackley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: qcom: pmi8950: add pwm nodeGianluca Boiano1-0/+8
This node is actually found on some msm8953 devices (xiaomi-mido) and allows irled enablement Signed-off-by: Gianluca Boiano <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: rockchip: add rfkill node for M.2 Key E Bluetooth on Rock 5BAlexey Charkov1-0/+7
By default the BT WAKE signal inside the M.2 key E connector on Radxa Rock 5B is driven low, which results in the Bluetooth function being disabled even if the inserted M.2 card supports it. Expose this signal as an RFKILL device so that it can be enabled by the userspace. Tested with an Intel AX210 card, which connects a Bluetooth device over the USB 2.0 bus. Signed-off-by: Alexey Charkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2024-05-28arm64: dts: allwinner: Fix PMIC interrupt numberAndre Przywara1-1/+1
The "r_intc" interrupt controller on the A64 uses a mapping scheme, so the first (and only) NMI interrupt #0 appears as interrupt number 32 (cf. the top comment in drivers/irqchip/irq-sun6i-r.c). Fix that number in the interrupts property to properly forward PMIC interrupts to the CPU. Signed-off-by: Andre Przywara <[email protected]> Fixes: 4d39a8eb07eb ("arm64: dts: allwinner: Add Jide Remix Mini PC support") Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2024-05-28Merge tag 'for-netdev' of ↵Jakub Kicinski3-5/+37
https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next Daniel Borkmann says: ==================== pull-request: bpf-next 2024-05-28 We've added 23 non-merge commits during the last 11 day(s) which contain a total of 45 files changed, 696 insertions(+), 277 deletions(-). The main changes are: 1) Rename skb's mono_delivery_time to tstamp_type for extensibility and add SKB_CLOCK_TAI type support to bpf_skb_set_tstamp(), from Abhishek Chauhan. 2) Add netfilter CT zone ID and direction to bpf_ct_opts so that arbitrary CT zones can be used from XDP/tc BPF netfilter CT helper functions, from Brad Cowie. 3) Several tweaks to the instruction-set.rst IETF doc to address the Last Call review comments, from Dave Thaler. 4) Small batch of riscv64 BPF JIT optimizations in order to emit more compressed instructions to the JITed image for better icache efficiency, from Xiao Wang. 5) Sort bpftool C dump output from BTF, aiming to simplify vmlinux.h diffing and forcing more natural type definitions ordering, from Mykyta Yatsenko. 6) Use DEV_STATS_INC() macro in BPF redirect helpers to silence a syzbot/KCSAN race report for the tx_errors counter, from Jiang Yunshui. 7) Un-constify bpf_func_info in bpftool to fix compilation with LLVM 17+ which started treating const structs as constants and thus breaking full BTF program name resolution, from Ivan Babrou. 8) Fix up BPF program numbers in test_sockmap selftest in order to reduce some of the test-internal array sizes, from Geliang Tang. 9) Small cleanup in Makefile.btf script to use test-ge check for v1.25-only pahole, from Alan Maguire. 10) Fix bpftool's make dependencies for vmlinux.h in order to avoid needless rebuilds in some corner cases, from Artem Savkov. * tag 'for-netdev' of https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next: (23 commits) bpf, net: Use DEV_STAT_INC() bpf, docs: Fix instruction.rst indentation bpf, docs: Clarify call local offset bpf, docs: Add table captions bpf, docs: clarify sign extension of 64-bit use of 32-bit imm bpf, docs: Use RFC 2119 language for ISA requirements bpf, docs: Move sentence about returning R0 to abi.rst bpf: constify member bpf_sysctl_kern:: Table riscv, bpf: Try RVC for reg move within BPF_CMPXCHG JIT riscv, bpf: Use STACK_ALIGN macro for size rounding up riscv, bpf: Optimize zextw insn with Zba extension selftests/bpf: Handle forwarding of UDP CLOCK_TAI packets net: Add additional bit to support clockid_t timestamp type net: Rename mono_delivery_time to tstamp_type for scalabilty selftests/bpf: Update tests for new ct zone opts for nf_conntrack kfuncs net: netfilter: Make ct zone opts configurable for bpf ct helpers selftests/bpf: Fix prog numbers in test_sockmap bpf: Remove unused variable "prev_state" bpftool: Un-const bpf_func_info to fix it for llvm 17 and newer bpf: Fix order of args in call to bpf_map_kvcalloc ... ==================== Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-05-28arm64: dts: qcom: apq8016: Add Schneider HMIBSC board DTSSumit Garg2-0/+492
Add Schneider Electric HMIBSC board DTS. The HMIBSC board is an IIoT Edge Box Core board based on the Qualcomm APQ8016E SoC. Support for Schneider Electric HMIBSC. Features: - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) - 1GiB RAM - 8GiB eMMC, SD slot - WiFi and Bluetooth - 2x Host, 1x Device USB port - HDMI - Discrete TPM2 chip over SPI - USB ethernet adaptors (soldered) Co-developed-by: Jagdish Gediya <[email protected]> Signed-off-by: Jagdish Gediya <[email protected]> Reviewed-by: Caleb Connolly <[email protected]> Reviewed-by: Stephan Gerhold <[email protected]> Signed-off-by: Sumit Garg <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: qcom: msm8996: drop source clock entries from the UFS nodeDmitry Baryshkov1-6/+0
There is no need to mention and/or to touch in any way the intermediate (source) clocks. Drop them from MSM8996 UFSHCD schema, making it follow the example lead by all other platforms. Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: qcom: msm8996: set GCC_UFS_ICE_CORE_CLK freq directlyDmitry Baryshkov1-2/+2
Instead of setting the frequency of the interim UFS_ICE_CORE_CLK_SRC clock, set the frequency of the leaf GCC_UFS_ICE_CORE_CLK clock directly. Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: qcom: msm8996: specify UFS core_clk frequenciesDmitry Baryshkov1-1/+1
Follow the example of other platforms and specify core_clk frequencies in the frequency table in addition to the core_clk_src frequencies. The driver should be setting the leaf frequency instead of some interim clock freq. Suggested-by: Nitin Rawat <[email protected]> Fixes: 57fc67ef0d35 ("arm64: dts: qcom: msm8996: Add ufs related nodes") Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: qcom: msm8996: add fastrpc nodesSrinivas Kandagatla1-0/+57
The ADSP provides fastrpc/compute capabilities. Enable support for the fastrpc on this DSP. Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28arm64: dts: qcom: msm8996: add glink-edge nodesDmitry Baryshkov1-0/+22
MSM8996 provides limited glink support, so add corresponding device tree nodes. For example the following interfaces are provided on db820c: modem: 2080000.remoteproc:glink-edge.LOOPBACK_CTL_MPSS.-1.-1 2080000.remoteproc:glink-edge.glink_ssr.-1.-1 2080000.remoteproc:glink-edge.rpmsg_chrdev.0.0 adsp: 9300000.remoteproc:glink-edge.LOOPBACK_CTL_LPASS.-1.-1 9300000.remoteproc:glink-edge.glink_ssr.-1.-1 9300000.remoteproc:glink-edge.rpmsg_chrdev.0.0 Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-05-28riscv: dts: canaan: Disable I/O devices unless usedGeert Uytterhoeven7-7/+32
It is considered good practice to disable on-SoC devices providing external I/O in the SoC-specific .dtsi, and enable them explicitly in the board-specific DTS files when actually wired-up and used. Hence: - Set the status of I/O devices in k210.dtsi to "disabled", - Override the status of used I/O devices in board-specific DTS files to "okay", - Drop unneeded status overrides in board DTS-specific files for the always-enabled pin controller. On e.g. MAiXBiT, this gets rid of an error message when probing the unused slave-only spi2 controller: dw_spi_mmio 50240000.spi: error -22: problem registering spi host dw_spi_mmio 50240000.spi: probe with driver dw_spi_mmio failed with error -22 which is seen since commit 98d75b9ef282f6b9 ("spi: dw: Drop default number of CS setting"). Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Damien Le Moal <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-05-28riscv: dts: canaan: Clean up serial aliasesGeert Uytterhoeven7-7/+24
The SoC-specific k210.dtsi declares aliases for all four serial ports. However, none of the board-specific DTS files configure pin control for any but the first serial port, so the last three ports are not usable. Move the aliases node from the SoC-specific k210.dtsi to the board-specific DTS files, as these are really board-specific, and retain the sole port that is usable. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Damien Le Moal <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-05-28arm64: defconfig: Enable Renesas R-Car Gen4 PCIe controllerWolfram Sang1-0/+3
Enable both modes, host and endpoint. Also, enable EDMA for performance gain for the endpoint mode. Signed-off-by: Wolfram Sang <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-05-28arm64: dts: renesas: s4sk: Add aliases for I2C busesWolfram Sang1-0/+6
They are numbered like this in the schematics, so keep the names in Linux the same. Signed-off-by: Wolfram Sang <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-05-28arm64: dts: renesas: spider-cpu: Add aliases for I2C busesWolfram Sang1-0/+6
They are numbered like this in the schematics, so keep the names in Linux the same. Signed-off-by: Wolfram Sang <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-05-28arm64: dts: renesas: white-hawk-cpu: Add aliases for I2C busesWolfram Sang1-0/+6
They are numbered like this in the schematics, so keep the names in Linux the same. Signed-off-by: Wolfram Sang <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-05-28arm64: dts: renesas: condor-i: Add I2C EEPROMGeert Uytterhoeven2-8/+6
The I2C EEPROM U197 on Condor is also present on Condor-I, but it was moved to the other side of the bi-directional voltage-level translator on I2C bus zero, and relabeled to U230. Move it to condor-common.dtsi to make it available on Condor-I, too. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/33a1ec9ee8fff7708f699c668d7399fde2b46553.1716455483.git.geert+renesas@glider.be
2024-05-28arm64: dts: renesas: gray-hawk-single: Add aliases for I2C busesWolfram Sang1-0/+4
They are numbered like this in the schematics, so keep the names in Linux the same. Signed-off-by: Wolfram Sang <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-05-28ARM: dts: renesas: r9a06g032: Describe GMAC1Clément Léger1-0/+18
The r9a06g032 SoC of the RZ/N1 family features two GMAC devices named GMAC1/2, that are based on Synopsys cores. GMAC1 is connected to a RGMII/RMII converter that is already described in this device tree. Signed-off-by: Clément Léger <[email protected]> [rgantois: commit log] Reviewed-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Romain Gantois <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-05-28arm64: dts: renesas: white-hawk: ethernet: Describe AVB1 and AVB2Niklas Söderlund1-0/+103
Describe the two Marvell 88Q2110/QFN40 PHYs available on the R-Car V4H White Hawk RAVB/Ethernet(1000Base-T1) sub-board. The two PHYs are wired up on the board by default, there is no need to move any resistors which are needed to access other PHYs available on this sub-board. Signed-off-by: Niklas Söderlund <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-05-28arm64: dts: renesas: r8a779g0: Use MDIO node for all AVB devicesNiklas Söderlund2-15/+14
Switch from defining the PHY inside the AVB node itself and create a dedicated MDIO node for AVB0, the only AVB describing a PHY. This is needed as adding PHYs to AVB1 and AVB2 will require setting MDIO bus parameters and thus requires a dedicated node. Signed-off-by: Niklas Söderlund <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
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