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The vmlinux load address and entry address is calculated in multiple
places:
- arch/mips/Makefile defines load-y from CONFIG_PHYSICAL_START (or
defined by the platform) and passes it to
arch/mips/boot/compressed/Makefile.
- arch/mips/boot/compressed/Makefile calculates kernel entry using nm.
- arch/mips/lasat/image/Makefile calculates both load and entry address
using nm.
Lets combine these in the main Makefile and then pass them as Make
parameters to each of the three boot image Makefiles (in boot/,
boot/compressed, lasat/image/). The boot/ Makefile doesn't currently use
them, but will soon need to for U-Boot image targets.
The existing load-y definition is used in preference to calculating the
load address using nm.
Signed-off-by: James Hogan <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: Florian Fainelli <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/5794/
Signed-off-by: Ralf Baechle <[email protected]>
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Split out the arch/mips/boot/ and arch/mips/boot/compressed/ targets
into boot-y and bootz-y variables. This makes it slightly cleaner to add
new targets.
Signed-off-by: James Hogan <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: Florian Fainelli <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/5793/
Signed-off-by: Ralf Baechle <[email protected]>
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Add symlink to include/dt-bindings from arch/mips/boot/dts/include/ to
match the ones in ARM and Meta architectures so that preprocessed device
tree files can include various useful constant definitions.
See commit c58299a (kbuild: create an "include chroot" for DT bindings)
merged in v3.10-rc1 for details.
MIPS structures it's dts files a little differently to other
architectures, having a separate dts directory for each SoC/platform,
but most of the definitions in the dt-bindings/ directory are common so
for now lets just have a single "include chroot" for all MIPS platforms.
Signed-off-by: James Hogan <[email protected]>
Reviewed-by: Steven. J. Hill <[email protected]>
Cc: Michal Marek <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Ian Campbell <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Pawel Moll <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Acked-by: Stephen Warren <[email protected]>
Patchwork: http://patchwork.linux-mips.org/patch/5745/
Signed-off-by: Ralf Baechle <[email protected]>
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Merge lockref infrastructure code by me and Waiman Long.
I already merged some of the preparatory patches that didn't actually do
any semantic changes earlier, but this merges the actual _reason_ for
those preparatory patches.
The "lockref" structure is a combination "spinlock and reference count"
that allows optimized reference count accesses. In particular, it
guarantees that the reference count will be updated AS IF the spinlock
was held, but using atomic accesses that cover both the reference count
and the spinlock words, we can often do the update without actually
having to take the lock.
This allows us to avoid the nastiest cases of spinlock contention on
large machines under heavy pathname lookup loads. When updating the
dentry reference counts on a large system, we'll still end up with the
cache line bouncing around, but that's much less noticeable than
actually having to spin waiting for the lock.
* lockref:
lockref: implement lockless reference count updates using cmpxchg()
lockref: uninline lockref helper functions
vfs: reimplement d_rcu_to_refcount() using lockref_get_or_lock()
vfs: use lockref_get_not_zero() for optimistic lockless dget_parent()
lockref: add 'lockref_get_or_lock() helper
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The kbldr.h header file required for this was neither committed in the
original submission in a3a0f8c8ed2e2470f4dcd6da95020d41fed84747
"MIPS: PowerTV: Base files for Cisco PowerTV platform"
nor was it ever present in the git tree so this option never worked.
Fixes the following build problem:
arch/mips/powertv/reset.c:25:36: fatal error: asm/mach-powertv/kbldr.h: No such
file or directory
compilation terminated.
Cc: David VomLehn <[email protected]>
Signed-off-by: Markos Chandras <[email protected]>
Acked-by: Steven J. Hill <[email protected]>
Cc: [email protected]
Cc: David VomLehn <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/5801/
Signed-off-by: Ralf Baechle <[email protected]>
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The NR_CPUS_DEFAULT_1 introduced as an aid for the QEMU
platform in 72ede9b18967e7a8a62a88f164f003193f6d891f
"[MIPS] Qemu: Fix Symmetric Uniprocessor support"
which was later removed in
302922e5f6901eb6f29c58539631f71b3d9746b8
"[MIPS] Qemu: Remove platform."
On certain randconfigs it may happen for NR_CPUS to have an
empty value because not all SMP platforms select a suitable
NR_CPUS_DEFAULT_* value. We fix this by restoring the range
of NR_CPUS to 2..64 and drop the NR_CPUS_DEFAULT_{1,2} symbols.
The first one is no longer used and the latter is not needed since
NR_CPUS=2 is now the default value.
Fixes the following problem on a randconfig:
.config:164:warning: symbol value '' invalid for NR_CPUS
Signed-off-by: Markos Chandras <[email protected]>
Acked-by: Steven J. Hill <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/5747/
Signed-off-by: Ralf Baechle <[email protected]>
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Currently the linux.bin target creates both linux.bin and linux.bin.ub.
Add linux.bin.ub as separate target to generate linux.bin.ub.
Signed-off-by: Jason Wu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Extend PVR reg decoding.
Signed-off-by: Michal Simek <[email protected]>
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The main reason that this driver can be used by ARM
and PPC. The part of preparing of move to generic location.
Signed-off-by: Michal Simek <[email protected]>
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Update dates in header and add Xilinx to it.
Signed-off-by: Michal Simek <[email protected]>
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Remove unused headers.
Signed-off-by: Michal Simek <[email protected]>
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The jmr3927_vec txx9_board_vec struct is defined in
txx9/jmr3927/setup.c which is only built if
CONFIG_TOSHIBA_JMR3927 is selected. This patch fixes the following
build problem:
arch/mips/txx9/generic/setup.c: In function 'select_board':
arch/mips/txx9/generic/setup.c:354:20: error:
'jmr3927_vec' undeclared (first use in this function)
arch/mips/txx9/generic/setup.c:354:20: note: each undeclared
identifier is reported only once for each function it appears in
make[3]: *** [arch/mips/txx9/generic/setup.o] Error 1
Signed-off-by: Markos Chandras <[email protected]>
Acked-by: Steven J. Hill <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/5713/
Signed-off-by: Ralf Baechle <[email protected]>
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The pci.c code depends on symbols which are only visible
if CONFIG_PCI is selected.
Also fixes the following problem on loongson allnoconfig:
arch/mips/built-in.o: In function `pcibios_init':
pci.c:(.init.text+0x528):
undefined reference to `register_pci_controller'
arch/mips/built-in.o:(.data+0xc):
undefined reference to `loongson_pci_ops'
Signed-off-by: Markos Chandras <[email protected]>
Acked-by: Steven J. Hill <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/5584/
Signed-off-by: Ralf Baechle <[email protected]>
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Dynamic function tracing was not working on MIPS. When doing dynamic
tracing, the tracer attempts to match up the passed in address with
the one the compiler creates in the mcount tables. The MIPS code was
passing in the return address from the tracing function call, but the
compiler tables were the address of the function call. So they
wouldn't match.
Just subtracting 8 from the return address will give the address of
the function call. Easy enough.
Signed-off-by: Corey Minyard <[email protected]>
[[email protected]: Adjusted code comment and patch Subject.]
Signed-off-by: David Daney <[email protected]>
Cc: [email protected]
Cc: Steven Rostedt <[email protected]>
Signed-off-by: Ralf Baechle <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/5592/
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This is a fix for a bug introduced with commit
447cdf2628b59aa513a42785450b348dced26d8a, submitted as archived here:
http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20080312235002.c717dde3.yoichi_yuasa%40tripeaks.co.jp
regrettably with no further explanation.
The issue is with the CP0 Count register read erratum present on R4000 and
some R4400 processors. If this erratum is present, then a read from this
register that happens around the time it reaches the value stored in the
CP0 Compare register causes a CP0 timer interrupt that is supposed to
happen when the values in the two registers match to be missed. The
implication for the chips affected is the CP0 timer can be used either as
a source of a timer interrupt (a clock event) or as a source of a
high-resolution counter (a clock source), but not both at a time.
The erratum does not affect timer interrupt operation itself, because in
this case the CP0 Count register is only read while the timer interrupt
has already been raised, while high-resolution counter references happen
at random times.
Additionally some systems apparently have issues with the timer interrupt
line being routed externally and not following the usual CP0 Count/Compare
semantics. In this case we don't want to use the R4k clock event.
We've meant to address the erratum and the timer interrupt routing issue
in time_init, however the commit referred to above broke our solution.
What we currently have is we enable the R4k clock source if the R4k clock
event initialization has succeeded (the timer is present and has no timer
interrupt routing issue) or there is no CP0 Count register read erratum.
Which gives the following boolean matrix:
clock event | count erratum => clock source
------------+---------------+--------------
0 | 0 | 1 (OK)
0 | 1 | 0 (bug!) -> no interference, could use
1 | 0 | 1 (OK)
1 | 1 | 1 (bug!) -> can't use, interference
What we want instead is to enable the R4k clock source if there is no CP0
Count register read erratum (obviously) or the R4k clock event
initialization has *failed* -- because in the latter case we won't be
using the timer interrupt anyway, so we don't care about any interference
CP0 Count reads might cause with the interrupt. This corresponds to the
following boolean matrix:
clock event | count erratum => clock source
------------+---------------+--------------
0 | 0 | 1
0 | 1 | 1
1 | 0 | 1
1 | 1 | 0
This is implemented here, effectively reverting the problematic commit,
and a short explanation is given next to code modified so that the
rationale is known to future readers and confusion is prevented from
happening here again.
It is worth noting that mips_clockevent_init returns 0 upon success while
cpu_has_mfc0_count_bug returns 0 upon failure. This is because the former
function returns an error code while the latter returns a boolean value.
To signify the difference I have therefore chosen to compare the result of
the former call explicitly against 0.
Signed-off-by: Maciej W. Rozycki <[email protected]>
Signed-off-by: Ralf Baechle <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/5799/
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Replace the numerical polarity flags with the PWM_POLARITY_INVERTED
symbolic constant.
Signed-off-by: Laurent Pinchart <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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- Use of_iomap
- Use of_property_read_u32
- Fix printk
Signed-off-by: Michal Simek <[email protected]>
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Simplify timer initialization and prepare the driver
for moving to drivers/clocksource folder.
Also remove system-timer property from binding because
the name is too generic.
Signed-off-by: Michal Simek <[email protected]>
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asm/irq.h is included in linux/irq.h
asm/prom.h and linux/init.h is not needed
Signed-off-by: Michal Simek <[email protected]>
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- Use of_iomap
- Use of_property_read_u32
- Fix printk
Signed-off-by: Michal Simek <[email protected]>
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- Move init_IRQ to irq.c
- Use IRQCHIP_DECLARE macro
Signed-off-by: Michal Simek <[email protected]>
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Update dates in header and add Xilinx to it.
Signed-off-by: Michal Simek <[email protected]>
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Trivial.
Signed-off-by: Michal Simek <[email protected]>
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TCR.TBI0 can be used to cause hardware address translation to ignore the
top byte of userspace virtual addresses. Whilst not especially useful in
standard C programs, this can be used by JITs to `tag' pointers with
various pieces of metadata.
This patch enables this bit for AArch64 Linux, and adds a new file to
Documentation/arm64/ which describes some potential caveats when using
tagged virtual addresses.
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Catalin Marinas <[email protected]>
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This was experimental feature which has never been
widely used because it expects GCC behaviour.
Also remove INTC_BASE and TIMER_BASE macros.
Signed-off-by: Michal Simek <[email protected]>
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This patch converts the pci_load_of_ranges function to use the new common
of_pci_range_parser.
Signed-off-by: Andrew Murray <[email protected]>
Signed-off-by: Andrew Murray <[email protected]>
Signed-off-by: Liviu Dudau <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Second UART doesn't have modem interface, so any attempt to use set_mctrl() it
produce unwanted garbage on the line. There's no such 0x100 register offset
for the second UART either.
Signed-off-by: Petr Štetiar <[email protected]>
Cc: Hartley Sweeten <[email protected]>
Signed-off-by: Ryan Mallon <[email protected]>
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This is almost cosmetic: we achieve a bit of consistency with
other clocksource drivers by using the CLOCKSOURCE_OF_DECLARE
macro for the boilerplate code.
Signed-off-by: Ezequiel Garcia <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
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Instead of taking the spinlock, the lockless versions atomically check
that the lock is not taken, and do the reference count update using a
cmpxchg() loop. This is semantically identical to doing the reference
count update protected by the lock, but avoids the "wait for lock"
contention that you get when accesses to the reference count are
contended.
Note that a "lockref" is absolutely _not_ equivalent to an atomic_t.
Even when the lockref reference counts are updated atomically with
cmpxchg, the fact that they also verify the state of the spinlock means
that the lockless updates can never happen while somebody else holds the
spinlock.
So while "lockref_put_or_lock()" looks a lot like just another name for
"atomic_dec_and_lock()", and both optimize to lockless updates, they are
fundamentally different: the decrement done by atomic_dec_and_lock() is
truly independent of any lock (as long as it doesn't decrement to zero),
so a locked region can still see the count change.
The lockref structure, in contrast, really is a *locked* reference
count. If you hold the spinlock, the reference count will be stable and
you can modify the reference count without using atomics, because even
the lockless updates will see and respect the state of the lock.
In order to enable the cmpxchg lockless code, the architecture needs to
do three things:
(1) Make sure that the "arch_spinlock_t" and an "unsigned int" can fit
in an aligned u64, and have a "cmpxchg()" implementation that works
on such a u64 data type.
(2) define a helper function to test for a spinlock being unlocked
("arch_spin_value_unlocked()")
(3) select the "ARCH_USE_CMPXCHG_LOCKREF" config variable in its
Kconfig file.
This enables it for x86-64 (but not 32-bit, we'd need to make sure
cmpxchg() turns into the proper cmpxchg8b in order to enable it for
32-bit mode).
Signed-off-by: Linus Torvalds <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 boot fix from Peter Anvin:
"A single very small boot fix for very large memory systems (> 0.5T)"
* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/mm: Fix boot crash with DEBUG_PAGE_ALLOC=y and more than 512G RAM
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Signed-off-by: Dan Aloni <[email protected]>
Signed-off-by: Catalin Marinas <[email protected]>
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This string has been moved to arch/arm64/kernel/cputable.c.
Signed-off-by: Catalin Marinas <[email protected]>
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Support UART0 debug ll on Hisilicon Hi3620 SoC & Hi3716 SoC.
Signed-off-by: Haojian Zhuang <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Now that we support a timer-backed delay loop, I'm quickly getting sick
and tired of people complaining that their beloved bogomips value has
decreased. You know who you are!
This patch removes the bogomips line from /proc/cpuinfo, based on the
reasoning that any program parsing this is already broken and, as such,
won't be further broken if the field is removed.
Acked-by: Nicolas Pitre <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
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It appears that gcc may put some code in ".text.unlikely" or
".text.hot" sections. Right now those aren't accounted for in unwind
tables. Add them.
I found some docs about this at:
http://gcc.gnu.org/onlinedocs/gcc-4.6.2/gcc.pdf
Without this, if you have slub_debug turned on, you can get messages
that look like this:
unwind: Index not found 7f008c50
Signed-off-by: Doug Anderson <[email protected]>
Acked-by: Mike Frysinger <[email protected]>
Signed-off-by: Russell King <[email protected]>
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The newly introduced function is to be used as .restart callback for
ARMv7-M machines. The used register is architecturally defined, so it
should work for all M-class machines.
Acked-by: Jonathan Austin <[email protected]>
Signed-off-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Section entries are 2MB on LPAE, so the DEBUG_LL virtual address must
have the same offset in the 2MB section as the physical address. This
fixes async external aborts when DEBUG_LL is enabled on Midway.
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Russell King <[email protected]>
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On Cortex-A15 CPUs up to and including r0p4, in certain rare sequences
of code, the loop buffer may deliver incorrect instructions. This
workaround disables the loop buffer to avoid the erratum.
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Use the convenience function instead of __GFP_ZERO.
Signed-off-by: Joe Perches <[email protected]>
Signed-off-by: Peter Zijlstra <[email protected]>
Link: http://lkml.kernel.org/r/f58599ae1a8d7b32d37e9cf283e95fba6452f7f6.1377809875.git.joe@perches.com
Signed-off-by: Ingo Molnar <[email protected]>
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Compared to old atom, Silvermont has offcore and has more events
that support PEBS.
Signed-off-by: Yan, Zheng <[email protected]>
Reviewed-by: Stephane Eranian <[email protected]>
Signed-off-by: Peter Zijlstra <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
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Silvermont (22nm Atom) has two offcore response configuration MSRs,
unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7.
To avoid complicating intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to
define MSR_OFFCORE_RSP_X. So intel_fixup_er() can find the event code
for OFFCORE_RSP_N by x86_pmu.extra_regs[N].event.
Signed-off-by: Yan, Zheng <[email protected]>
Signed-off-by: Peter Zijlstra <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
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For performance reasons, when SMAP is in use, SMAP is left open for an
entire put_user_try { ... } put_user_catch(); block, however, calling
__put_user() in the middle of that block will close SMAP as the
STAC..CLAC constructs intentionally do not nest.
Furthermore, using __put_user() rather than put_user_ex() here is bad
for performance.
Thus, introduce new [compat_]save_altstack_ex() helpers that replace
__[compat_]save_altstack() for x86, being currently the only
architecture which supports put_user_try { ... } put_user_catch().
Reported-by: H. Peter Anvin <[email protected]>
Signed-off-by: Al Viro <[email protected]>
Signed-off-by: H. Peter Anvin <[email protected]>
Cc: <[email protected]> # v3.8+
Link: http://lkml.kernel.org/n/[email protected]
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Add SMAP annotations to csum_partial_copy_to/from_user(). These
functions legitimately access user space and thus need to set the AC
flag.
TODO: add explicit checks that the side with the kernel space pointer
really points into kernel space.
Signed-off-by: H. Peter Anvin <[email protected]>
Link: http://lkml.kernel.org/n/[email protected]
Cc: <[email protected]> # v3.7+
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git://git.linaro.org/people/cdall/linux-kvm-arm into queue
KVM/ARM Updates for Linux 3.12
* tag 'kvm-arm-for-3.12' of git://git.linaro.org/people/cdall/linux-kvm-arm:
ARM: KVM: Add newlines to panic strings
ARM: KVM: Work around older compiler bug
ARM: KVM: Simplify tracepoint text
ARM: KVM: Fix kvm_set_pte assignment
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Two straggling fixes that I had missed as they were posted a couple of
weeks ago, causing problems with interrupts (breaking them completely)
on the CSR SiRF platforms"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
arm: prima2: drop nr_irqs in mach as we moved to linear irqdomain
irqchip: sirf: move from legacy mode to linear irqdomain
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The panic strings are hard to read and on narrow terminals some
characters are simply truncated off the panic message.
Make is slightly prettier with a newline in the Hyp panic strings.
Acked-by: Marc Zyngier <[email protected]>
Signed-off-by: Christoffer Dall <[email protected]>
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Compilers before 4.6 do not behave well with unnamed fields in structure
initializers and therefore produces build errors:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=10676
By refering to the unnamed union using braces, both older and newer
compilers produce the same result.
Acked-by: Marc Zyngier <[email protected]>
Reported-by: Russell King <[email protected]>
Tested-by: Russell King <[email protected]>
Signed-off-by: Christoffer Dall <[email protected]>
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The tracepoint for kvm_guest_fault was extremely long, make it a
slightly bit shorter.
Cc: Sergei Shtylyov <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Signed-off-by: Christoffer Dall <[email protected]>
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THe kvm_set_pte function was actually assigning the entire struct to the
structure member, which should work because the structure only has that
one member, but it is still not very nice.
Acked-by: Marc Zyngier <[email protected]>
Signed-off-by: Christoffer Dall <[email protected]>
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We always use a timer-backed delay loop for arm64, so don't bother
reporting a bogomips value which appears to confuse some people.
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Catalin Marinas <[email protected]>
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