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2019-04-24KVM: arm/arm64: Context-switch ptrauth registersMark Rutland9-18/+238
When pointer authentication is supported, a guest may wish to use it. This patch adds the necessary KVM infrastructure for this to work, with a semi-lazy context switch of the pointer auth state. Pointer authentication feature is only enabled when VHE is built in the kernel and present in the CPU implementation so only VHE code paths are modified. When we schedule a vcpu, we disable guest usage of pointer authentication instructions and accesses to the keys. While these are disabled, we avoid context-switching the keys. When we trap the guest trying to use pointer authentication functionality, we change to eagerly context-switching the keys, and enable the feature. The next time the vcpu is scheduled out/in, we start again. However the host key save is optimized and implemented inside ptrauth instruction/register access trap. Pointer authentication consists of address authentication and generic authentication, and CPUs in a system might have varied support for either. Where support for either feature is not uniform, it is hidden from guests via ID register emulation, as a result of the cpufeature framework in the host. Unfortunately, address authentication and generic authentication cannot be trapped separately, as the architecture provides a single EL2 trap covering both. If we wish to expose one without the other, we cannot prevent a (badly-written) guest from intermittently using a feature which is not uniformly supported (when scheduled on a physical CPU which supports the relevant feature). Hence, this patch expects both type of authentication to be present in a cpu. This switch of key is done from guest enter/exit assembly as preparation for the upcoming in-kernel pointer authentication support. Hence, these key switching routines are not implemented in C code as they may cause pointer authentication key signing error in some situations. Signed-off-by: Mark Rutland <[email protected]> [Only VHE, key switch in full assembly, vcpu_has_ptrauth checks , save host key in ptrauth exception trap] Signed-off-by: Amit Daniel Kachhap <[email protected]> Reviewed-by: Julien Thierry <[email protected]> Cc: Christoffer Dall <[email protected]> Cc: [email protected] [maz: various fixups] Signed-off-by: Marc Zyngier <[email protected]>
2019-04-24s390/mm: fix pxd_bad with folded page tablesMartin Schwidefsky1-14/+19
With git commit d1874a0c2805fcfa9162c972d6b7541e57adb542 "s390/mm: make the pxd_offset functions more robust" and a 2-level page table it can now happen that pgd_bad() gets asked to verify a large segment table entry. If the entry is marked as dirty pgd_bad() will incorrectly return true. Change the pgd_bad(), p4d_bad(), pud_bad() and pmd_bad() functions to first verify the table type, return false if the table level is lower than what the function is suppossed to check, return true if the table level is too high, and otherwise check the relevant region and segment table bits. pmd_bad() has to check against ~SEGMENT_ENTRY_BITS for normal page table pointers or ~SEGMENT_ENTRY_BITS_LARGE for large segment table entries. Same for pud_bad() which has to check against ~_REGION_ENTRY_BITS or ~_REGION_ENTRY_BITS_LARGE. Fixes: d1874a0c2805 ("s390/mm: make the pxd_offset functions more robust") Signed-off-by: Martin Schwidefsky <[email protected]>
2019-04-24s390/kasan: fix strncpy_from_user kasan checksVasily Gorbik1-0/+2
arch/s390/lib/uaccess.c is built without kasan instrumentation. Kasan checks are performed explicitly in copy_from_user/copy_to_user functions. But since those functions could be inlined, calls from files like uaccess.c with instrumentation disabled won't generate kasan reports. This is currently the case with strncpy_from_user function which was revealed by newly added kasan test. Avoid inlining of copy_from_user/copy_to_user when the kernel is built with kasan support to make sure kasan checks are fully functional. Signed-off-by: Vasily Gorbik <[email protected]> Signed-off-by: Martin Schwidefsky <[email protected]>
2019-04-24x86/pci: Clean up usage of X86_DEV_DMA_OPSChristoph Hellwig1-3/+0
We have supported per-device dma_map_ops in generic code for a long time, and this symbol just guards the inclusion of the dma_map_ops registry used for vmd. Stop enabling it for anything but vmd. No change in functionality intended. Signed-off-by: Christoph Hellwig <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Cc: Borislav Petkov <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Thomas Gleixner <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
2019-04-24x86/build: Move _etext to actual end of .textKees Cook1-3/+3
When building x86 with Clang LTO and CFI, CFI jump regions are automatically added to the end of the .text section late in linking. As a result, the _etext position was being labelled before the appended jump regions, causing confusion about where the boundaries of the executable region actually are in the running kernel, and broke at least the fault injection code. This moves the _etext mark to outside (and immediately after) the .text area, as it already the case on other architectures (e.g. arm64, arm). Reported-and-tested-by: Sami Tolvanen <[email protected]> Signed-off-by: Kees Cook <[email protected]> Cc: Borislav Petkov <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Thomas Gleixner <[email protected]> Link: http://lkml.kernel.org/r/20190423183827.GA4012@beast Signed-off-by: Ingo Molnar <[email protected]>
2019-04-24x86/um/vdso: Drop unnecessary cc-ldoptionNick Desaulniers1-1/+1
Towards the goal of removing cc-ldoption, it seems that --hash-style= was added to binutils 2.17.50.0.2 in 2006. The minimal required version of binutils for the kernel according to Documentation/process/changes.rst is 2.20. Suggested-by: Masahiro Yamada <[email protected]> Signed-off-by: Nick Desaulniers <[email protected]> Cc: Borislav Petkov <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Link: http://lkml.kernel.org/r/[email protected] Link: https://gcc.gnu.org/ml/gcc/2007-01/msg01141.html Signed-off-by: Ingo Molnar <[email protected]>
2019-04-24x86/mm: Remove in_nmi() warning from 64-bit implementation of vmalloc_fault()Jiri Kosina1-2/+0
In-NMI warnings have been added to vmalloc_fault() via: ebc8827f75 ("x86: Barf when vmalloc and kmemcheck faults happen in NMI") back in the time when our NMI entry code could not cope with nested NMIs. These days, it's perfectly fine to take a fault in NMI context and we don't have to care about the fact that IRET from the fault handler might cause NMI nesting. This warning has already been removed from 32-bit implementation of vmalloc_fault() in: 6863ea0cda8 ("x86/mm: Remove in_nmi() warning from vmalloc_fault()") but the 64-bit version was omitted. Remove the bogus warning also from 64-bit implementation of vmalloc_fault(). Reported-by: Nicolai Stange <[email protected]> Signed-off-by: Jiri Kosina <[email protected]> Acked-by: Peter Zijlstra (Intel) <[email protected]> Cc: Andy Lutomirski <[email protected]> Cc: Borislav Petkov <[email protected]> Cc: Dave Hansen <[email protected]> Cc: Frederic Weisbecker <[email protected]> Cc: Joerg Roedel <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Thomas Gleixner <[email protected]> Fixes: 6863ea0cda8 ("x86/mm: Remove in_nmi() warning from vmalloc_fault()") Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
2019-04-24x86/uaccess: Dont leak the AC flag into __put_user() argument evaluationPeter Zijlstra1-3/+4
The __put_user() macro evaluates it's @ptr argument inside the __uaccess_begin() / __uaccess_end() region. While this would normally not be expected to be an issue, an UBSAN bug (it ignored -fwrapv, fixed in GCC 8+) would transform the @ptr evaluation for: drivers/gpu/drm/i915/i915_gem_execbuffer.c: if (unlikely(__put_user(offset, &urelocs[r-stack].presumed_offset))) { into a signed-overflow-UB check and trigger the objtool AC validation. Finish this commit: 2a418cf3f5f1 ("x86/uaccess: Don't leak the AC flag into __put_user() value evaluation") and explicitly evaluate all 3 arguments early. Reported-by: Randy Dunlap <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Acked-by: Randy Dunlap <[email protected]> # build-tested Acked-by: Linus Torvalds <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: [email protected] Fixes: 2a418cf3f5f1 ("x86/uaccess: Don't leak the AC flag into __put_user() value evaluation") Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
2019-04-24x86/mm: Fix a crash with kmemleak_scan()Qian Cai1-0/+6
The first kmemleak_scan() call after boot would trigger the crash below because this callpath: kernel_init free_initmem mem_encrypt_free_decrypted_mem free_init_pages unmaps memory inside the .bss when DEBUG_PAGEALLOC=y. kmemleak_init() will register the .data/.bss sections and then kmemleak_scan() will scan those addresses and dereference them looking for pointer references. If free_init_pages() frees and unmaps pages in those sections, kmemleak_scan() will crash if referencing one of those addresses: BUG: unable to handle kernel paging request at ffffffffbd402000 CPU: 12 PID: 325 Comm: kmemleak Not tainted 5.1.0-rc4+ #4 RIP: 0010:scan_block Call Trace: scan_gray_list kmemleak_scan kmemleak_scan_thread kthread ret_from_fork Since kmemleak_free_part() is tolerant to unknown objects (not tracked by kmemleak), it is fine to call it from free_init_pages() even if not all address ranges passed to this function are known to kmemleak. [ bp: Massage. ] Fixes: b3f0907c71e0 ("x86/mm: Add .bss..decrypted section to hold shared variables") Signed-off-by: Qian Cai <[email protected]> Signed-off-by: Borislav Petkov <[email protected]> Reviewed-by: Catalin Marinas <[email protected]> Cc: Andy Lutomirski <[email protected]> Cc: Brijesh Singh <[email protected]> Cc: Dave Hansen <[email protected]> Cc: "H. Peter Anvin" <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: x86-ml <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-04-24Merge tag 'drm-intel-next-2019-04-17' of ↵Dave Airlie1-1/+3
git://anongit.freedesktop.org/drm/drm-intel into drm-next UAPI Changes: - uAPI "Fixes:" patch for the upcoming kernel 5.1, included here too We have an Ack from the media folks (only current user) for this late tweak Cross-subsystem Changes: - ALSA: hda: Fix racy display power access (Takashi, Chris) Driver Changes: - DDI and MIPI-DSI clocks fixes for Icelake (Vandita) - Fix Icelake frequency change/locking (RPS) (Mika) - Temporarily disable ppGTT read-only bit on Icelake (Mika) - Add missing Icelake W/As (Mika) - Enable 12 deep CSB status FIFO on Icelake (Mika) - Inherit more Icelake code for Elkhartlake (Bob, Jani) - Handle catastrophic error on engine reset (Mika) - Shortcut readiness to reset check (Mika) - Regression fix for GEM_BUSY causing us to report a mixed uabi-class request as not busy (Chris) - Revert back to max link rate and lane count on eDP (Jani) - Fix pipe BPP readout for BXT/GLK DSI (Ville) - Set DP min_bpp to 8*3 for non-RGB output formats (Ville) - Enable coarse preemption boundaries for Gen8 (Chris) - Do not enable FEC without DSC (Ville) - Restore correct BXT DDI latency optim setting calculation (Ville) - Always reset context's RING registers to avoid running workload twice during reset (Chris) - Set GPU wedged on driver unload (Janusz) - Consolidate two similar barries from timeline into one (Chris) - Only reset the pinned kernel contexts on resume (Chris) - Wakeref tracking improvements (Chris, Imre) - Lockdep fixes for shrinker interactions (Chris) - Bump ready tasks ahead of busywaits in prep of semaphore use (Chris) - Huge step in splitting display code into fine grained files (Jani) - Refactor the IRQ init/reset macros for code saving (Paulo) - Convert IRQ initialization code to uncore MMIO access (Paulo) - Convert workarounds code to use uncore MMIO access (Chris) - Nuke drm_crtc_state and use intel_atomic_state instead (Manasi) - Update SKL clock-gating WA (Radhakrishna, Ville) - Isolate GuC reset code flow (Chris) - Expose force_dsc_enable through debugfs (Manasi) - Header standalone compile testing framework (Jani) - Code cleanups to reduce driver footprint (Chris) - PSR code fixes and cleanups (Jose) - Sparse and kerneldoc updates (Chris) - Suppress spurious combo PHY B warning (Vile) Signed-off-by: Dave Airlie <[email protected]> From: Joonas Lahtinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-23mips: vdso: drop unnecessary cc-ldoptionNick Desaulniers1-3/+1
Towards the goal of removing cc-ldoption, it seems that --hash-style= was added to binutils 2.17.50.0.2 in 2006. The minimal required version of binutils for the kernel according to Documentation/process/changes.rst is 2.20. --build-id was added in 2.18 according to binutils-gdb/ld/NEWS. Link: https://gcc.gnu.org/ml/gcc/2007-01/msg01141.html Cc: [email protected] Suggested-by: Masahiro Yamada <[email protected]> Signed-off-by: Nick Desaulniers <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: [email protected] Cc: Matt Redfearn <[email protected]> Cc: Joel Stanley <[email protected]> Cc: Hassan Naveed <[email protected]> Cc: [email protected] Cc: [email protected]
2019-04-23arm64: dts: rockchip: fix IO domain voltage setting of APIO5 on rockpro64Katsuhiro Suzuki1-1/+1
This patch fixes IO domain voltage setting that is related to audio_gpio3d4a_ms (bit 1) of GRF_IO_VSEL. This is because RockPro64 schematics P.16 says that regulator supplies 3.0V power to APIO5_VDD. So audio_gpio3d4a_ms bit should be clear (means 3.0V). Power domain map is saying different thing (supplies 1.8V) but I believe P.16 is actual connectings. Fixes: e4f3fb490967 ("arm64: dts: rockchip: add initial dts support for Rockpro64") Cc: [email protected] Suggested-by: Robin Murphy <[email protected]> Signed-off-by: Katsuhiro Suzuki <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2019-04-23Merge tag 'syscalls-5.1' of ↵Linus Torvalds16-1/+65
git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic Pull syscall numbering updates from Arnd Bergmann: "arch: add pidfd and io_uring syscalls everywhere This comes a bit late, but should be in 5.1 anyway: we want the newly added system calls to be synchronized across all architectures in the release. I hope that in the future, any newly added system calls can be added to all architectures at the same time, and tested there while they are in linux-next, avoiding dependencies between the architecture maintainer trees and the tree that contains the new system call" * tag 'syscalls-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: arch: add pidfd and io_uring syscalls everywhere
2019-04-23arm64: dts: db820c: Add sound card supportSrinivas Kandagatla4-0/+286
This patch adds support both digital and analog audio on DB820c. This board has HDMI port and 3.5mm audio jack to support both digital and analog audio respectively. Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2019-04-23asm-generic: provide entirely generic nommu uaccessChristoph Hellwig3-55/+2
Move the code to implement uaccess using memcpy or direct loads and stores to asm-generic/uaccess.h and make it selectable kconfig option. Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
2019-04-23arch: mostly remove <asm/segment.h>Christoph Hellwig23-52/+0
A few architectures use <asm/segment.h> internally, but nothing in common code does. Remove all the empty or almost empty versions of it, including the asm-generic one. Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
2019-04-23asm-generic: don't include <asm/segment.h> from <asm/uaccess.h>Christoph Hellwig1-0/+1
<asm/segment.h> is an odd x86 legacy that we shouldn't force on other architectures. arc used it to bring in mm_context_t, but we can do that inside the arc code easily. Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
2019-04-23arm64: dts: apq8096-db820c: Add HDMI display supportArchit Taneja2-0/+79
The APQ8096 DB820c platform provides HDMI output. The MDSS block on 8x96 supports a direct HDMI out. Populate the MDSS, MDP and HDMI DT nodes. Also, add the HDMI HPD and DDC pinctrl nodes with the bias and driver strength specified for this platform. Signed-off-by: Archit Taneja <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2019-04-23arm64: dts: Add Adreno GPU definitionsJordan Crouse1-0/+86
Add an initial node for the Adreno GPU. Signed-off-by: Vivek Gautam <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2019-04-23arm64: qcom: msm8996.dtsi: Add Display nodesArchit Taneja1-0/+120
Signed-off-by: Archit Taneja <[email protected]> [Removed instances of mmagic clocks; Use qcom,msm8996-smmu-v2 bindings] Signed-off-by: Vivek Gautam <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2019-04-23arm64: dts: msm8996: Add display smmu nodeArchit Taneja1-0/+18
Add device node for display smmu, aka. mdp_smmu. Signed-off-by: Archit Taneja <[email protected]> Signed-off-by: Vivek Gautam <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2019-04-23arm64: dts: msm8996: Add graphics smmu nodeJordan Crouse1-0/+19
Add device node for graphics smmu, aka. adreno_smmu. Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Vivek Gautam <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2019-04-23arm64: dts: sdm845: Add CPU capacity valuesMatthias Kaehlcke1-0/+8
Specify the relative CPU capacity of all SDM845 AP cores. The values were provided by Qualcomm engineers. Signed-off-by: Matthias Kaehlcke <[email protected]> Reviewed-by: Rajendra Nayak <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2019-04-23arm64: dts: sdm845: Add CPU topologyMatthias Kaehlcke1-0/+38
The 8 CPU cores of the SDM845 are organized in two clusters of 4 big ("gold") and 4 little ("silver") cores. Add a cpu-map node to the DT that describes this topology. Signed-off-by: Matthias Kaehlcke <[email protected]> Reviewed-by: Douglas Anderson <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2019-04-23arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYsMatthias Kaehlcke1-4/+6
Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 10nm PHY. Signed-off-by: Matthias Kaehlcke <[email protected]> Reviewed-by: Douglas Anderson <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2019-04-23arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHYMatthias Kaehlcke1-2/+3
Add 'xo_board' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 28nm PHY. Signed-off-by: Matthias Kaehlcke <[email protected]> Reviewed-by: Douglas Anderson <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2019-04-23arm64: dts: qcom: pm8998: Use ADC temperature to temp-alarm nodeMatthias Kaehlcke1-0/+2
The temperature information from the temp-alarm block itself is very coarse ("temperature is above/below trip points"). Provide the driver with the die temperature channel of the ADC on the PMIC for more precise readings. Signed-off-by: Matthias Kaehlcke <[email protected]> Reviewed-by: Douglas Anderson <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2019-04-23powerpc/512x: mark clocks as big endianJonas Gorski1-3/+6
These clocks' registers are accessed as big endian, so mark them as such. Signed-off-by: Jonas Gorski <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-04-23ARM: multi_v7_defconfig: Enable missing drivers for supported ChromebooksEnric Balletbo i Serra1-0/+11
Enable following drivers for merged devices: - Batteries with BQ27XXX chips for Minnie boards. - Elan eKTH I2C touchscreen for Minnie boards. - GPIO charger for all Veyron boards. - Rockchip SARADC driver for all rk3288 boards. - Rockchip eFUSE driver for all rk3288 boards. - TPM security chip for all Veyron boards. - ChromeOS EC userspace interface for all chromebooks boards. - ChromeOS EC light and proximity sensors for some chromebooks. Signed-off-by: Enric Balletbo i Serra <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2019-04-23ARM: rockchip: add missing of_node_put in rockchip_smp_prepare_pmuWen Yang1-0/+1
The call to of_get_next_child returns a node pointer with refcount incremented thus it must be explicitly decremented after the last usage. Detected by coccinelle with the following warnings: ./arch/arm/mach-rockchip/platsmp.c:250:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 241, but without a corresponding object release within this function. ./arch/arm/mach-rockchip/platsmp.c:260:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 241, but without a corresponding object release within this function. ./arch/arm/mach-rockchip/platsmp.c:263:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 241, but without a corresponding object release within this function. Signed-off-by: Wen Yang <[email protected]> Cc: Russell King <[email protected]> Cc: Heiko Stuebner <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2019-04-23arm64: Expose SVE2 features for userspaceDave Martin6-1/+51
This patch provides support for reporting the presence of SVE2 and its optional features to userspace. This will also enable visibility of SVE2 for guests, when KVM support for SVE-enabled guests is available. Signed-off-by: Dave Martin <[email protected]> Signed-off-by: Will Deacon <[email protected]>
2019-04-23arm64: Kconfig: Make CONFIG_COMPAT a menuconfig entryWill Deacon1-55/+58
Make CONFIG_COMPAT a menuconfig entry so that we can place CONFIG_KUSER_HELPERS and CONFIG_ARMV8_DEPRECATED underneath it. Signed-off-by: Will Deacon <[email protected]>
2019-04-23arm64: compat: Add KUSER_HELPERS config optionVincenzo Frascino4-5/+39
When kuser helpers are enabled the kernel maps the relative code at a fixed address (0xffff0000). Making configurable the option to disable them means that the kernel can remove this mapping and any access to this memory area results in a sigfault. Add a KUSER_HELPERS config option that can be used to disable the mapping when it is turned off. This option can be turned off if and only if the applications are designed specifically for the platform and they do not make use of the kuser helpers code. Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Signed-off-by: Vincenzo Frascino <[email protected]> Reviewed-by: Catalin Marinas <[email protected]> [will: Use IS_ENABLED() instead of #ifdef] Signed-off-by: Will Deacon <[email protected]>
2019-04-23arm64: compat: Refactor aarch32_alloc_vdso_pages()Vincenzo Frascino1-26/+26
aarch32_alloc_vdso_pages() needs to be refactored to make it easier to disable kuser helpers. Divide the function in aarch32_alloc_kuser_vdso_page() and aarch32_alloc_sigreturn_vdso_page(). Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Signed-off-by: Vincenzo Frascino <[email protected]> Reviewed-by: Catalin Marinas <[email protected]> [will: Inlined sigpage allocation to simplify error paths] Signed-off-by: Will Deacon <[email protected]>
2019-04-23arm64: compat: Split kuser32Vincenzo Frascino3-57/+50
To make it possible to disable kuser helpers in aarch32 we need to divide the kuser and the sigreturn functionalities. Split the current version of kuser32 in kuser32 (for kuser helpers) and sigreturn32 (for sigreturn helpers). Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Signed-off-by: Vincenzo Frascino <[email protected]> Reviewed-by: Catalin Marinas <[email protected]> Signed-off-by: Will Deacon <[email protected]>
2019-04-23arm64: compat: Alloc separate pages for vectors and sigpageVincenzo Frascino4-34/+93
For AArch32 tasks, we install a special "[vectors]" page that contains the sigreturn trampolines and kuser helpers, which is mapped at a fixed address specified by the kuser helpers ABI. Having the sigreturn trampolines in the same page as the kuser helpers makes it impossible to disable the kuser helpers independently. Follow the Arm implementation, by moving the signal trampolines out of the "[vectors]" page and into their own "[sigpage]". Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Signed-off-by: Vincenzo Frascino <[email protected]> Reviewed-by: Catalin Marinas <[email protected]> [will: tweaked comments and fixed sparse warning] Signed-off-by: Will Deacon <[email protected]>
2019-04-23ARM: 8857/1: efi: enable CP15 DMB instructions before cleaning the cacheArd Biesheuvel1-1/+15
The EFI stub is entered with the caches and MMU enabled by the firmware, and once the stub is ready to hand over to the decompressor, we clean and disable the caches. The cache clean routines use CP15 barrier instructions, which can be disabled via SCTLR. Normally, when using the provided cache handling routines to enable the caches and MMU, this bit is enabled as well. However, but since we entered the stub with the caches already enabled, this routine is not executed before we call the cache clean routines, resulting in undefined instruction exceptions if the firmware never enabled this bit. So set the bit explicitly in the EFI entry code, but do so in a way that guarantees that the resulting code can still run on v6 cores as well (which are guaranteed to have CP15 barriers enabled) Cc: <[email protected]> # v4.9+ Acked-by: Marc Zyngier <[email protected]> Signed-off-by: Ard Biesheuvel <[email protected]> Signed-off-by: Russell King <[email protected]>
2019-04-23ARM: 8856/1: NOMMU: Fix CCR register faulty initialization when MPU is disabledTigran Tadevosyan1-1/+1
When CONFIG_ARM_MPU is not defined, the base address of v7M SCB register is not initialized with correct value. This prevents enabling I/D caches when the L1 cache poilcy is applied in kernel. Fixes: 3c24121039c9da14692eb48f6e39565b28c0f3cf ("ARM: 8756/1: NOMMU: Postpone MPU activation till __after_proc_init") Signed-off-by: Tigran Tadevosyan <[email protected]> Signed-off-by: Vladimir Murzin <[email protected]> Signed-off-by: Russell King <[email protected]>
2019-04-23ARM: fix function graph tracer and unwinder dependenciesRussell King2-4/+4
Naresh Kamboju recently reported that the function-graph tracer crashes on ARM. The function-graph tracer assumes that the kernel is built with frame pointers. We explicitly disabled the function-graph tracer when building Thumb2, since the Thumb2 ABI doesn't have frame pointers. We recently changed the way the unwinder method was selected, which seems to have made it more likely that we can end up with the function- graph tracer enabled but without the kernel built with frame pointers. Fix up the function graph tracer dependencies so the option is not available when we have no possibility of having frame pointers, and adjust the dependencies on the unwinder option to hide the non-frame pointer unwinder options if the function-graph tracer is enabled. Reviewed-by: Masami Hiramatsu <[email protected]> Tested-by: Masami Hiramatsu <[email protected]> Signed-off-by: Russell King <[email protected]>
2019-04-23ARM: 8858/1: vdso: use $(LD) instead of $(CC) to link VDSOMasahiro Yamada1-13/+8
We use $(LD) to link vmlinux, modules, decompressors, etc. VDSO is the only exceptional case where $(CC) is used as the linker driver, but I do not know why we need to do so. VDSO uses a special linker script, and does not link standard libraries at all. I changed the Makefile to use $(LD) rather than $(CC). I confirmed the same vdso.so.raw was still produced. Users will be able to use their favorite linker (e.g. lld instead of of bfd) by passing LD= from the command line. My plan is to rewrite all VDSO Makefiles to use $(LD), then delete cc-ldoption. Signed-off-by: Masahiro Yamada <[email protected]> Reviewed-by: Nick Desaulniers <[email protected]> Signed-off-by: Russell King <[email protected]>
2019-04-23ARM: 8855/1: remove unused <asm/limits.h>Masahiro Yamada1-12/+0
No one includes this. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Russell King <[email protected]>
2019-04-23ARM: 8850/1: use memblocks_presentPeng Fan1-16/+1
arm_memory_present is doing same thing as memblocks_present, so let's use common code memblocks_present instead of platform specific arm_memory_present. Patchwork: https://patchwork.kernel.org/patch/10805693/ Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Russell King <[email protected]>
2019-04-23ARM: 8854/1: drop -mauto-itStefan Agner1-2/+1
The assembler option -mauto-it is no longer a valid option. The last remaining references have been removed from the documentation in July 2009 [0]. The currently supported binutils version is 2.20 (released in September 2009) or higher where gas supports -mimplicit-it=always. Drop the fallback to -mauto-it and use -mimplicit-it=always only. [0] https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=529707530657a333a304c651c808ea630c955223 Signed-off-by: Stefan Agner <[email protected]> Reviewed-by: Nick Desaulniers <[email protected]> Signed-off-by: Russell King <[email protected]>
2019-04-23ARM: 8846/1: warn if divided syntax assembler is usedStefan Agner1-5/+2
Remove the -mno-warn-deprecated assembler flag to make sure the GNU assembler warns in case non-unified syntax is used. Signed-off-by: Stefan Agner <[email protected]> Acked-by: Nicolas Pitre <[email protected]> Reviewed-by: Nick Desaulniers <[email protected]> Signed-off-by: Russell King <[email protected]>
2019-04-23ARM: 8853/1: drop WASM to work around LLVM issueStefan Agner1-2/+2
Currently LLVM's integrated assembler does not recognize .w form of the pld instructions (LLVM Bug 40972 [0]): ./arch/arm/include/asm/processor.h:133:5: error: invalid instruction "pldw.wt%a0 n" ^ <inline asm>:2:1: note: instantiated into assembly here pldw.w [r0] ^ 1 error generated. The W macro for generating wide instructions when targeting Thumb-2 is not strictly required for the preload data instructions (pld, pldw) since they are only available as wide instructions. The GNU assembler works with or without the .w appended when compiling an Thumb-2 kernel. Drop the macro to work around LLVM Bug 40972 issue. [0] https://bugs.llvm.org/show_bug.cgi?id=40972 Signed-off-by: Stefan Agner <[email protected]> Reviewed-by: Nick Desaulniers <[email protected]> Signed-off-by: Russell King <[email protected]>
2019-04-23ARM: 8852/1: uaccess: use unified assembler language syntaxStefan Agner1-1/+2
Convert the conditional infix to a postfix to make sure this inline assembly is unified syntax. Since gcc assumes non-unified syntax when emitting ARM instructions, make sure to define the syntax as unified. This allows to use LLVM's integrated assembler. Additionally, for GCC ".syntax unified" for inline assembly. When compiling non-Thumb2 GCC always emits a ".syntax divided" at the beginning of the inline assembly which makes the assembler fail. Since GCC 5 there is the -masm-syntax-unified GCC option which make GCC assume unified syntax asm and hence emits ".syntax unified" even in ARM mode. However, the option is broken since GCC version 6 (see GCC PR88648 [1]). Work around by adding ".syntax unified" as part of the inline assembly. [0] https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html#index-masm-syntax-unified [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88648 Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Russell King <[email protected]>
2019-04-23ARM: 8851/1: add TUSERCOND() macro for conditional postfixStefan Agner2-3/+6
Unified assembly syntax requires conditionals to be postfixes. TUSER() currently only takes a single argument which then gets appended t (with translation) on every instruction. This fixes a build error when using LLVM's integrated assembler: In file included from kernel/futex.c:72: ./arch/arm/include/asm/futex.h:116:3: error: invalid instruction, did you mean: strt? "2: " TUSER(streq) " %3, [%4]n" ^ <inline asm>:5:4: note: instantiated into assembly here 2: streqt r2, [r4] ^~~~~~ Additionally, for GCC ".syntax unified" for inline assembly. When compiling non-Thumb2 GCC always emits a ".syntax divided" at the beginning of the inline assembly which makes the assembler fail. Since GCC 5 there is the -masm-syntax-unified GCC option which make GCC assume unified syntax asm and hence emits ".syntax unified" even in ARM mode. However, the option is broken since GCC version 6 (see GCC PR88648 [1]). Work around by adding ".syntax unified" as part of the inline assembly. [0] https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html#index-masm-syntax-unified [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88648 Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Russell King <[email protected]>
2019-04-23x86/MCE/AMD: Don't report L1 BTB MCA errors on some family 17h modelsYazen Ghannam3-13/+48
AMD family 17h Models 10h-2Fh may report a high number of L1 BTB MCA errors under certain conditions. The errors are benign and can safely be ignored. However, the high error rate may cause the MCA threshold counter to overflow causing a high rate of thresholding interrupts. In addition, users may see the errors reported through the AMD MCE decoder module, even with the interrupt disabled, due to MCA polling. Clear the "Counter Present" bit in the Instruction Fetch bank's MCA_MISC0 register. This will prevent enabling MCA thresholding on this bank which will prevent the high interrupt rate due to this error. Define an AMD-specific function to filter these errors from the MCE event pool so that they don't get reported during early boot. Rename filter function in EDAC/mce_amd to avoid a naming conflict, while at it. [ bp: Move function prototype to the internal header and massage/cleanup, fix typos. ] Reported-by: Rafał Miłecki <[email protected]> Signed-off-by: Yazen Ghannam <[email protected]> Signed-off-by: Borislav Petkov <[email protected]> Cc: "H. Peter Anvin" <[email protected]> Cc: "[email protected]" <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: James Morse <[email protected]> Cc: Kees Cook <[email protected]> Cc: Mauro Carvalho Chehab <[email protected]> Cc: Pu Wen <[email protected]> Cc: Qiuxu Zhuo <[email protected]> Cc: Shirish S <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Tony Luck <[email protected]> Cc: Vishal Verma <[email protected]> Cc: linux-edac <[email protected]> Cc: x86-ml <[email protected]> Cc: <[email protected]> # 5.0.x: c95b323dcd35: x86/MCE/AMD: Turn off MC4_MISC thresholding on all family 0x15 models Cc: <[email protected]> # 5.0.x: 30aa3d26edb0: x86/MCE/AMD: Carve out the MC4_MISC thresholding quirk Cc: <[email protected]> # 5.0.x: 9308fd407455: x86/MCE: Group AMD function prototypes in <asm/mce.h> Cc: <[email protected]> # 5.0.x Link: https://lkml.kernel.org/r/[email protected]
2019-04-23x86/MCE: Add an MCE-record filtering functionYazen Ghannam3-0/+11
Some systems may report spurious MCA errors. In general, spurious MCA errors may be disabled by clearing a particular bit in MCA_CTL. However, clearing a bit in MCA_CTL may not be recommended for some errors, so the only option is to ignore them. An MCA error is printed and handled after it has been added to the MCE event pool. So an MCA error can be ignored by not adding it to that pool in the first place. Add such a filtering function. [ bp: Move function prototype to the internal header and massage. ] Signed-off-by: Yazen Ghannam <[email protected]> Signed-off-by: Borislav Petkov <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: "[email protected]" <[email protected]> Cc: "H. Peter Anvin" <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Pu Wen <[email protected]> Cc: Qiuxu Zhuo <[email protected]> Cc: "[email protected]" <[email protected]> Cc: Shirish S <[email protected]> Cc: <[email protected]> # 5.0.x Cc: Thomas Gleixner <[email protected]> Cc: Tony Luck <[email protected]> Cc: Vishal Verma <[email protected]> Cc: x86-ml <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-04-23x86/xen: Add "xen_timer_slop" command line optionRyan Thibodeaux1-3/+17
Add a new command-line option "xen_timer_slop=<INT>" that sets the minimum delta of virtual Xen timers. This commit does not change the default timer slop value for virtual Xen timers. Lowering the timer slop value should improve the accuracy of virtual timers (e.g., better process dispatch latency), but it will likely increase the number of virtual timer interrupts (relative to the original slop setting). The original timer slop value has not changed since the introduction of the Xen-aware Linux kernel code. This commit provides users an opportunity to tune timer performance given the refinements to hardware and the Xen event channel processing. It also mirrors a feature in the Xen hypervisor - the "timer_slop" Xen command line option. [boris: updated comment describing TIMER_SLOP] Signed-off-by: Ryan Thibodeaux <[email protected]> Reviewed-by: Boris Ostrovsky <[email protected]> Signed-off-by: Boris Ostrovsky <[email protected]>
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