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2016-05-13MIPS: BCM47xx: Move SPROM driver to drivers/firmware/Rafał Miłecki5-729/+3
Broadcom ARM home routers store SPROM content in NVRAM just like MIPS ones. To share SPROM code we need to move it out of arch/mips/ to some common place. We already have bcm47xx_nvram in firmware path and SPROM should fit there as well. This driver is responsible for parsing SoC configuration data into a struct shared between ssb and bcma buses. This was tested with BCM4706 & BCM5357C0 (BCM47XX) and BCM4708A0 (ARCH_BCM_5301X). Signed-off-by: Rafał Miłecki <[email protected]> Cc: Hauke Mehrtens <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12210/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: ralink: Make reset_control_ops constPhilipp Zabel1-1/+1
The reset_ops structure is never modified. Make it const. Signed-off-by: Philipp Zabel <[email protected]> Acked-by: John Crispin <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12618/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: lantiq: Make reset_control_ops constPhilipp Zabel1-1/+1
The reset_ops structure is never modified. Make it const. Signed-off-by: Philipp Zabel <[email protected]> Acked-by: John Crispin <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12619/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: Octeon: device_tree_init: fill mac addresses when using appended dtbAaro Koskinen1-1/+7
Fill MAC addresses from bootinfo when using appended DTB. Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12590/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: Octeon: device_tree_init: don't fill mac if already setAaro Koskinen1-0/+8
Don't fill MAC address if it's already set. This allows DTB to override the bootinfo. Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12589/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: Octeon: device_tree_init: use separate pass to fill mac addressesAaro Koskinen2-16/+72
Use separate pass to fill MAC addresses. This is needed because we want to do this also for the appended DTB. Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12588/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: Octeon: Use model string from DTB for unknown board typeAaro Koskinen1-2/+10
Use model string from DTB for board type if the board is unknown. This is more informative, e.g. with EdgeRouter Pro the /proc/cpuinfo will display "ubnt,e200 (CN6120p1.1-1000-NSP)" instead of misleading "Unsupported Board". Signed-off-by: Aaro Koskinen <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12582/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: Octeon: Initialize system type string after device tree init.Aaro Koskinen1-4/+2
Initialize system type string after device tree init. Signed-off-by: Aaro Koskinen <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12583/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: Octeon: board_type_to_string: return NULL for unsupported boardAaro Koskinen2-3/+8
Return NULL for unsupported board. Signed-off-by: Aaro Koskinen <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12581/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: OCTEON: Simplify code in octeon_irq_ciu_gpio_set_type()David Daney1-1/+1
Use the trigger type passed in to the function instead of reading it back out of the irq_data. Signed-off-by: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12501/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: OCTEON: Add SMP support for OCTEON cn78xx et al.David Daney3-16/+139
OCTEON chips with the CIU3 interrupt controller use a different IPI mechanism that previous models. Add plat_smp_ops for the cn78xx and probing code to choose between the two types of ops. Signed-off-by: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12499/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: OCTEON: Add support for OCTEON III interrupt controller.David Daney2-1/+668
Add irq_chip support for both IPI and "normal" interrupts of the CIU3 controller. Document the device tree binding for the CIU3. Some functions are non-static as they will be used by follow-on support for MSI-X. Signed-off-by: David Daney <[email protected]> Acked-by: Rob Herring <[email protected]> Cc: Rob Herring <[email protected]> Cc: Pawel Moll <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Ian Campbell <[email protected]> Cc: Kumar Gala <[email protected]> Cc: [email protected] Cc: Thomas Gleixner <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12500/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: OCTEON: Don't attempt to use nonexistent registers on OCTEON III models.David Daney2-17/+30
Attempts to read the nonexistent registers results in bus errors. Either use registers that exist, or don't do the access as appropriate. Signed-off-by: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12502/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: OCTEON: Add model checking support for cn73xx, cnf75xx and cn78xxDavid Daney4-8/+125
Follow on patchs need to be able to distinguish the new models. Signed-off-by: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12498/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: OCTEON: Add register definitions for cn73xx, cnf75xx and cn78xx.David Daney3-16/+748
These new members of the OCTEON III family have some new registers, update some of the definitions for use in follow on patches. Signed-off-by: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12497/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: Select CONFIG_HANDLE_DOMAIN_IRQ and make it work.David Daney2-0/+11
Per the subject, always select HANDLE_DOMAIN_IRQ, and implement set_irq_regs() so that it actually works. Signed-off-by: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12496/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: OCTEON: Remove some code limiting NR_IRQS to 255David Daney1-25/+2
Follow-on patches for OCTEON III will increase the number of irqs to potentially more than 256. Increase the width of the octeon_irq_ciu_to_irq to int to be able to handle this case. Remove the hacky code that verified that u8 would not be overflowed. Signed-off-by: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12495/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: OCTEON: Extend number of supported CPUs past 32David Daney5-8/+125
To support more than 48 CPUs, the bootinfo structure grows a new coremask structure. Add the definition of the structure and add it to struct cvmx_bootinfo. In prom_init(), copy the new coremask data into the sysinfo structure, and use it in smp_setup(). Signed-off-by: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12319/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: OCTEON: Remove dead code from cvmx-sysinfo.David Daney2-97/+5
Get rid of the long unused code. Signed-off-by: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12318/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: Add CPU identifiers and probing for Cavium CN73xx and CNF75xx processors.David Daney2-0/+4
Add new processor identifiers for Cavium CN73xx and CNF75xx processors, and probe for them in cpu-probe.c Signed-off-by: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12311/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: highmem: Turn flush_cache_kmaps into a no-op.Ralf Baechle1-1/+3
It was calling flush_cache_all() which is a no-op since a long time anyway and which was overkill in the old days when it was actually doing something because only the D-cache needs to be flushed, never the I-cache, never the S-cache. Since however highmem on MIPS is still only supported on processors that don't suffer from cache aliases, we could turn flush_cache_kmaps() into a no-op - but for paranoia's sake we rather make it BUG_ON(cpu_has_dc_aliases()). Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: Loongson64: Remove call to flush_cache_all().Ralf Baechle1-1/+0
flush_cache_all() is a nop and loongson 3 is fully coherent. Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: VR41xx: Use __flush_cache_all instead of flush_cache_all.Ralf Baechle1-1/+1
It's probably a good idea to flush caches before reset and by the time this code was written flush_cache_all did actually still do something. Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: MSP71xx: Use __flush_cache_all instead of flush_cache_all.Ralf Baechle1-1/+1
Flushing caches is probably sensible on reset but flush_cache_all has been a no-op for a very long time. Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: Octeon: Use __flush_cache_all instead of flush_cache_all.Ralf Baechle1-1/+1
flush_cache_all will go away. Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: ath79: Use the reset controller to restart OF machinesAlban Bedel1-3/+4
Don't set _machine_restart() on OF machines as the reset driver now provides a system restart handler. Signed-off-by: Alban Bedel <[email protected]> Cc: Felix Fietkau <[email protected]> Cc: Antony Pavlov <[email protected]> Cc: Gabor Juhos <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12235/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: ath79: Add zboot debug serial supportAlban Bedel2-1/+6
Reuse the early printk code to support the serial in zboot. We copy early_printk.c instead of referencing it because we need to build a different object file for the normal kernel and zboot. Signed-off-by: Alban Bedel <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: Alex Smith <[email protected]> Cc: Wu Zhangjin <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12234/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: ath79: Remove the builtin DTB supportAlban Bedel3-19/+0
Now that appended DTB is usable we can drop the builtin DTB support. Signed-off-by: Alban Bedel <[email protected]> Cc: Felix Fietkau <[email protected]> Cc: Antony Pavlov <[email protected]> Cc: Gabor Juhos <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12231/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: ath79: Add support for DTB passed using the UHI boot protocolAlban Bedel1-0/+2
This is needed for bootloader supporting UHI and to support appended DTB. Signed-off-by: Alban Bedel <[email protected]> Cc: Felix Fietkau <[email protected]> Cc: Antony Pavlov <[email protected]> Cc: Gabor Juhos <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12230/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13x86/arch_prctl/64: Restore accidentally removed put_cpu() in ARCH_SET_GSMateusz Guzik1-0/+1
This fixes an oversight in: 731e33e39a5b95 ("Remove FSBASE/GSBASE < 4G optimization") Signed-off-by: Mateusz Guzik <[email protected]> Cc: Alexander Shishkin <[email protected]> Cc: Andy Lutomirski <[email protected]> Cc: Andy Lutomirski <[email protected]> Cc: Arnaldo Carvalho de Melo <[email protected]> Cc: Borislav Petkov <[email protected]> Cc: Brian Gerst <[email protected]> Cc: Denys Vlasenko <[email protected]> Cc: H. Peter Anvin <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Stephane Eranian <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Vince Weaver <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
2016-05-13Merge branch 'kvm-ppc-next' of ↵Paolo Bonzini5-23/+62
git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc into HEAD
2016-05-13ARC: pae: STRICT_MM_TYPECHECKS was brokenVineet Gupta1-0/+4
Signed-off-by: Vineet Gupta <[email protected]>
2016-05-12coredump: get rid of coredump_params->writtenOmar Sandoval1-2/+3
cprm->written is redundant with cprm->file->f_pos, so use that instead. Signed-off-by: Omar Sandoval <[email protected]> Signed-off-by: Al Viro <[email protected]>
2016-05-12Merge tag 'at91-fixes2' of ↵Arnd Bergmann1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into fixes Merge "Second AT91 fix PR for 4.6" from Nicolas Ferre: - fix a regression on the clock subsystem while switching to syscon/regmap due to a stricter check of the register map. * tag 'at91-fixes2' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: ARM: dts: at91: sam9x5: Fix the memory range assigned to the PMC
2016-05-12powerpc/4xx: Device tree update for the 460ex DWC SATAAndy Shevchenko1-3/+12
Device tree update for the Applied micro processor 460ex on-chip SATA to use "dmas" property. Acked-by: Rob Herring <[email protected]> Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Tejun Heo <[email protected]>
2016-05-12arm64: do not enforce strict 16 byte alignment to stack pointerColin Ian King1-3/+0
copy_thread should not be enforcing 16 byte aligment and returning -EINVAL. Other architectures trap misaligned stack access with SIGBUS so arm64 should follow this convention, so remove the strict enforcement check. For example, currently clone(2) fails with -EINVAL when passing a misaligned stack and this gives little clue to what is wrong. Instead, it is arguable that a SIGBUS on the fist access to a misaligned stack allows one to figure out that it is a misaligned stack issue rather than trying to figure out why an unconventional (and undocumented) -EINVAL is being returned. Acked-by: Catalin Marinas <[email protected]> Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Will Deacon <[email protected]>
2016-05-12perf/x86/intel/pt: Generate PMI in the STOP region as wellAlexander Shishkin1-0/+2
Currently, the PT driver always sets the PMI bit one region (page) before the STOP region so that we can wake up the consumer before we run out of room in the buffer and have to disable the event. However, we also need an interrupt in the last output region, so that we actually get to disable the event (if no more room from new data is available at that point), otherwise hardware just quietly refuses to start, but the event is scheduled in and we end up losing trace data till the event gets removed. For a cpu-wide event it is even worse since there may not be any re-scheduling at all and no chance for the ring buffer code to notice that its buffer is filled up and the event needs to be disabled (so that the consumer can re-enable it when it finishes reading the data out). In other words, all the trace data will be lost after the buffer gets filled up. This patch makes PT also generate a PMI when the last output region is full. Reported-by: Markus Metzger <[email protected]> Signed-off-by: Alexander Shishkin <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Cc: <[email protected]> Cc: Arnaldo Carvalho de Melo <[email protected]> Cc: Arnaldo Carvalho de Melo <[email protected]> Cc: Borislav Petkov <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Stephane Eranian <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Vince Weaver <[email protected]> Cc: [email protected] Link: http://lkml.kernel.org/r/1462886313-13660-2-git-send-email-alexander.shishkin@linux.intel.com Signed-off-by: Ingo Molnar <[email protected]>
2016-05-12x86/tsc: Add missing Cherrytrail frequency to the tableJeremy Compostella1-0/+3
Intel Cherrytrail is based on Airmont core so MSR_FSB_FREQ[2:0] = 4 means that the CPU reference clock runs at 80MHz. Add this missing frequency to the table. Signed-off-by: Jeremy Compostella <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2016-05-12x86: Use compat version for preadv2 and pwritev2Dmitry V. Levin1-2/+2
Similar to preadv and pwritev, preadv2 and pwritev2 need compat entries in the 32-bit syscall table. This bug was found by strace test suite. Fixes: 4babf2c5efb7 ("x86: wire up preadv2 and pwritev2") Signed-off-by: Dmitry V. Levin <[email protected]> Acked-by: Christoph Hellwig <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2016-05-12powerpc/powernv/npu: Add PE to PHB's listAlexey Kardashevskiy1-0/+3
Before commit 3e68dc57 "powerpc/powernv: Remove DMA32 PE list", NPU PEs were linked to the NPU PHB via phb->ioda.pe_dma_list; after that fix, the phb->ioda.pe_list is used. During the pe_dma_list removal, list_add_tail(&phb->ioda.pe_dma_list) was removed, however no list_add() was added so does this patch. Fixes: 3e68dc57219a ("powerpc/powernv: Remove DMA32 PE list") Signed-off-by: Alexey Kardashevskiy <[email protected]> Reviewed-by: Gavin Shan <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2016-05-12powerpc/powernv: Fix insufficient memory allocationAlexey Kardashevskiy1-1/+2
The pnv_pci_init_ioda_phb() helper allocates a blob to store auxilary data such PE and M32/M64 segment allocation maps; this single blob has few partitions, size of each is derived from the PE number - phb->ioda.total_pe_num. It was assumed that the minimum PE number is 8, however it is 4 for NPU so the pe_alloc part was missing in the allocated blob. It was invisible till recently as we were not tracking used M64 segments and NPUs do not use M32 segments so the phb->ioda.m32_segmap (which was pointing to the same address as phb->ioda.pe_alloc) has never been written to leaving the pe_alloc memory intact. After commit 401203ac2d "powerpc/powernv: Track M64 segment consumption" the pe_alloc gets corrupted and PE allocation cannot work. This fixes the issue by enforcing the minimum PE number to 8. Fixes: 401203ac2d15 ("powerpc/powernv: Track M64 segment consumption") Signed-off-by: Alexey Kardashevskiy <[email protected]> Reviewed-by: Gavin Shan <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2016-05-12powerpc/iommu: Remove the dependency on EEH struct in DDW mechanismGuilherme G. Piccoli1-12/+12
Commit 39baadbf36ce ("powerpc/eeh: Remove eeh information from pci_dn") changed the pci_dn struct by removing its EEH-related members. As part of this clean-up, DDW mechanism was modified to read the device configuration address from eeh_dev struct. As a consequence, now if we disable EEH mechanism on kernel command-line for example, the DDW mechanism will fail, generating a kernel oops by dereferencing a NULL pointer (which turns to be the eeh_dev pointer). This patch just changes the configuration address calculation on DDW functions to a manual calculation based on pci_dn members instead of using eeh_dev-based address. No functional changes were made. This was tested on pSeries, both in PHyp and qemu guest. Fixes: 39baadbf36ce ("powerpc/eeh: Remove eeh information from pci_dn") Cc: [email protected] # v3.4+ Reviewed-by: Gavin Shan <[email protected]> Signed-off-by: Guilherme G. Piccoli <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2016-05-12Revert "powerpc/eeh: Fix crash in eeh_add_device_early() on Cell"Guilherme G. Piccoli1-1/+1
This reverts commit 89a51df5ab1d38b257300b8ac940bbac3bb0eb9b. The function eeh_add_device_early() is used to perform EEH initialization in devices added later on the system, like in hotplug/DLPAR scenarios. Since the commit 89a51df5ab1d ("powerpc/eeh: Fix crash in eeh_add_device_early() on Cell") a new check was introduced in this function - Cell has no EEH capabilities which led to kernel oops if hotplug was performed, so checking for eeh_enabled() was introduced to avoid the issue. However, in architectures that EEH is present like pSeries or PowerNV, we might reach a case in which no PCI devices are present on boot time and so EEH is not initialized. Then, if a device is added via DLPAR for example, eeh_add_device_early() fails because eeh_enabled() is false, and EEH end up not being enabled at all. This reverts the aforementioned patch since a new verification was introduced by the commit d91dafc02f42 ("powerpc/eeh: Delay probing EEH device during hotplug") and so the original Cell issue does not happen anymore. Cc: [email protected] # v4.1+ Reviewed-by: Gavin Shan <[email protected]> Signed-off-by: Guilherme G. Piccoli <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2016-05-12powerpc/eeh: Drop unnecessary label in eeh_pe_change_owner()Gavin Shan1-4/+1
The label "reset" in eeh_pe_change_owner() is used only for once. No need to keep it and just drop it. No logical changes introduced. Signed-off-by: Gavin Shan <[email protected]> Reviewed-by: David Gibson <[email protected]> Reviewed-by: Russell Currey <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2016-05-12powerpc/eeh: Ignore handlers in eeh_pe_reset_and_recover()Gavin Shan1-7/+1
The function eeh_pe_reset_and_recover() is used to recover EEH error when the passthrough device are transferred to guest and backwards, meaning the device's driver is vfio-pci or none. In both cases, the handlers triggered by eeh_report_reset() and eeh_report_resume() shouldn't be called. This ignores the error handlers from eeh_report_reset() and eeh_report_resume(). Signed-off-by: Gavin Shan <[email protected]> Reviewed-by: Russell Currey <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2016-05-12powerpc/eeh: Restore initial state in eeh_pe_reset_and_recover()Gavin Shan1-0/+23
The function eeh_pe_reset_and_recover() is used to recover EEH error when the passthrou device are transferred to guest and backwards. The content in the device's config space will be lost on PE reset issued in the middle of the recovery. The function saves/restores it before/after the reset. However, config access to some adapters like Broadcom BCM5719 at this point will causes fenced PHB. The config space is always blocked and we save 0xFF's that are restored at late point. The memory BARs are totally corrupted, causing another EEH error upon access to one of the memory BARs. This restores the config space on those adapters like BCM5719 from the content saved to the EEH device when it's populated, to resolve above issue. Fixes: 5cfb20b9 ("powerpc/eeh: Emulate EEH recovery for VFIO devices") Cc: [email protected] #v3.18+ Signed-off-by: Gavin Shan <[email protected]> Reviewed-by: Russell Currey <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2016-05-12powerpc/eeh: Don't report error in eeh_pe_reset_and_recover()Gavin Shan1-3/+0
The function eeh_pe_reset_and_recover() is used to recover EEH error when the passthrough device are transferred to guest and backwards, meaning the device's driver is vfio-pci or none. When the driver is vfio-pci that provides error_detected() error handler only, the handler simply stops the guest and it's not expected behaviour. On the other hand, no error handlers will be called if we don't have a bound driver. This ignores the error handler in eeh_pe_reset_and_recover() that reports the error to device driver to avoid the exceptional behaviour. Fixes: 5cfb20b9 ("powerpc/eeh: Emulate EEH recovery for VFIO devices") Cc: [email protected] #v3.18+ Signed-off-by: Gavin Shan <[email protected]> Reviewed-by: Russell Currey <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2016-05-12Revert "powerpc/powernv: Exclude root bus in pnv_pci_reset_secondary_bus()"Michael Ellerman1-2/+10
This reverts commit c8ceacc22bce95d3a9cff198c9c27a30105a16b8. Gavin says: I missed the fact that it affects the PCI passthrou path as reported by Alexey: When passing GPU (0003:01:00.0) which seats behind the root port, the reset request is routed to skiboot in original code. In skiboot, the link bouncing events are masked during the reset. So we don't see EEH (freeze all) error even link bouncing happens. With the changes included, the reset is done by kernel and the link bouncing events aren't masked by altering content of PHB3 (or P7IOC) specific hardware registers which are invisible to kernel (skiboot hides the hardware specific). It means the link bouncing is seen by the root port and it causes a EEH (freeze all) error. The PCI passthrough on GPU device cannot work. Requested-by: Alexey Kardashevskiy <[email protected]> Requested-by: Gavin Shan <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2016-05-12perf/x86/intel/pt: Generate PMI in the STOP region as wellAlexander Shishkin1-0/+2
Currently, the PT driver always sets the PMI bit one region (page) before the STOP region so that we can wake up the consumer before we run out of room in the buffer and have to disable the event. However, we also need an interrupt in the last output region, so that we actually get to disable the event (if no more room from new data is available at that point), otherwise hardware just quietly refuses to start, but the event is scheduled in and we end up losing trace data till the event gets removed. For a cpu-wide event it is even worse since there may not be any re-scheduling at all and no chance for the ring buffer code to notice that its buffer is filled up and the event needs to be disabled (so that the consumer can re-enable it when it finishes reading the data out). In other words, all the trace data will be lost after the buffer gets filled up. This patch makes PT also generate a PMI when the last output region is full. Reported-by: Markus Metzger <[email protected]> Signed-off-by: Alexander Shishkin <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Cc: Arnaldo Carvalho de Melo <[email protected]> Cc: Arnaldo Carvalho de Melo <[email protected]> Cc: Borislav Petkov <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Stephane Eranian <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Vince Weaver <[email protected]> Cc: [email protected] Link: http://lkml.kernel.org/r/1462886313-13660-2-git-send-email-alexander.shishkin@linux.intel.com Signed-off-by: Ingo Molnar <[email protected]>
2016-05-12Merge branch 'perf/urgent' into perf/core, to pick up fixesIngo Molnar3-2/+9
Signed-off-by: Ingo Molnar <[email protected]>
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