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Instead of using the dev_ops ->stop|start() callbacks for genpd, let's
convert to use genpd's flag field and set it to GENPD_FLAG_PM_CLK.
Signed-off-by: Ulf Hansson <[email protected]>
Acked-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>
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Earlier implementation assumed last instruction is BPF_EXIT.
Since this is no longer a restriction in eBPF, we remove this
limitation.
Per Alexei Starovoitov [1]:
> classic BPF has a restriction that last insn is always BPF_RET.
> eBPF doesn't have BPF_RET instruction and this restriction.
> It has BPF_EXIT insn which can appear anywhere in the program
> one or more times and it doesn't have to be last insn.
[1] https://lkml.org/lkml/2014/11/27/2
Fixes: e54bcde3d69d ("arm64: eBPF JIT compiler")
Acked-by: Alexei Starovoitov <[email protected]>
Signed-off-by: Zi Shen Lim <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
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Two files that get included when building the multi_v7_defconfig target
fail to build when selecting THUMB2_KERNEL for this configuration.
In both cases, we can just build the file as ARM code, as none of its
symbols are exported to modules, so there are no interworking concerns.
In the iwmmxt.S case, add ENDPROC() declarations so the symbols are
annotated as functions, resulting in the linker to emit the appropriate
mode switches.
Acked-by: Nicolas Pitre <[email protected]>
Tested-by: Olof Johansson <[email protected]>
Signed-off-by: Ard Biesheuvel <[email protected]>
Signed-off-by: Russell King <[email protected]>
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This patch just reorders functions/data inside sa1100 irq driver to be
able to merge functions that have the same code after converting to
irqdomains and hwirq. No real code changes.
Signed-off-by: Dmitry Eremin-Solenikov <[email protected]>
Tested-by: Linus Walleij <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Switch internally to using hardware irq numbers (hwirq). In case of GPIO
interrupts, hwirq is equal to GPIO number. In case of system interrupts,
hwirq is equal to interrupt number in the interrupt controller.
Signed-off-by: Dmitry Eremin-Solenikov <[email protected]>
Tested-by: Linus Walleij <[email protected]>
Signed-off-by: Russell King <[email protected]>
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IRQ_GPIO11_27 is a shared IRQ receiving IRQs from "high" GPIOs. It is
still handled by sa1100_normal_chip, so there is no point to exclude it
from "normal" irq domain. The IRQF_VALID flag set by domain map function
will be cleared by irq_set_chained_handler() internally.
Signed-off-by: Dmitry Eremin-Solenikov <[email protected]>
Tested-by: Linus Walleij <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Use irqdomains to manage both system and GPIO interrupts on SA1100 SoC
family. This opens path to further cleanup and unification in sa1100 IRQ
drivers.
Signed-off-by: Dmitry Eremin-Solenikov <[email protected]>
Tested-by: Linus Walleij <[email protected]>
Signed-off-by: Russell King <[email protected]>
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As IRQ0 should not be used (especially in when using irq domains), shift all
virtual IRQ numbers by one.
Signed-off-by: Dmitry Eremin-Solenikov <[email protected]>
Tested-by: Linus Walleij <[email protected]>
Signed-off-by: Russell King <[email protected]>
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In preparation for further changes replace direct IRQ numbers with
pre-defined names. This imposes no real code changes.
Signed-off-by: Dmitry Eremin-Solenikov <[email protected]>
Tested-by: Linus Walleij <[email protected]>
Signed-off-by: Russell King <[email protected]>
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As mach-sa1100 was converted to MULTI_IRQ_HANDLER, drop now-unused
entry-macro.S file.
Signed-off-by: Dmitry Eremin-Solenikov <[email protected]>
Tested-by: Linus Walleij <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Add sa1100_handle_irq implementating handle_irq for sa1100 platform.
It is more or less a translation of old assembly code from assembler to
plain C. Also install this irq handler from sa1100_init_irq().
Signed-off-by: Dmitry Eremin-Solenikov <[email protected]>
Tested-by: Linus Walleij <[email protected]>
Signed-off-by: Russell King <[email protected]>
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If the kernel is running in hypervisor mode or monitor mode we'll
print UK6_32 or UK10_32 if we call into __show_regs(). Let's
update these strings to indicate the new modes that didn't exist
when this code was written.
Signed-off-by: Stephen Boyd <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Signed-off-by: Nicolas Pitre <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Introduce helper functions for pte_mk* functions and it would be
used to change individual bits in ptes at times.
Signed-off-by: Jungseung Lee <[email protected]>
Signed-off-by: Russell King <[email protected]>
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set_memory_* functions have same implementation
except memory attribute.
This patch makes to use common function for these, and pull out
the functions into arch/arm/mm/pageattr.c like arm64 did.
It will reduce code size and enhance the readability.
Signed-off-by: Jungseung Lee <[email protected]>
Signed-off-by: Russell King <[email protected]>
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L1_CACHE_BYTES could be larger than real L1 cache line size.
In that case, flush_pfn_alias() would omit to flush last bytes
as much as L1_CACHE_BYTES - real cache line size.
So fix end address to "to + PAGE_SIZE - 1". The bottom bits of the address
is LINELEN. that is ignored by mcrr.
Signed-off-by: Jungseung Lee <[email protected]>
Signed-off-by: Russell King <[email protected]>
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L1_CACHE_BYTES could be larger value than real L1 cache line size.
In that case, discard_old_kernel_data() would omit to invalidate
last bytes as much as L1_CACHE_BYTES - real cache line size.
So fix end address to "to + PAGE_SIZE -1". The bottom bits
of the address is LINELEN. that is ignored by mcrr.
Signed-off-by: Jungseung Lee <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Modern ARMv7-A/R cores optionally implement below new
hardware feature:
- PXN:
Privileged execute-never(PXN) is a security feature. PXN bit
determines whether the processor can execute software from
the region. This is effective solution against ret2usr attack.
On an implementation that does not include the LPAE, PXN is
optionally supported.
This patch set PXN bit on user page table for preventing
user code execution with privilege mode.
Reviewed-by: Catalin Marinas <[email protected]>
Signed-off-by: Jungseung Lee <[email protected]>
Signed-off-by: Russell King <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD
KVM: s390: Several fixes,cleanups and reworks
Here is a bunch of fixes that deal mostly with architectural compliance:
- interrupt priorities
- interrupt handling
- intruction exit handling
We also provide a helper function for getting the guest visible storage key.
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All functions declared in this file are gone.
Signed-off-by: Arnd Bergmann <[email protected]>
[[email protected]: re-order patches so modify board-dt-sam9]
Signed-off-by: Nicolas Ferre <[email protected]>
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These files were left behind with no reason. Remove them.
Signed-off-by: Nicolas Ferre <[email protected]>
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As AT91 !DT code is now removed, cleanup the PIT clocksource driver.
Signed-off-by: Arnd Bergmann <[email protected]>
[[email protected]: split patch]
Signed-off-by: Nicolas Ferre <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Cc: Boris BREZILLON <[email protected]>
Cc: Daniel Lezcano <[email protected]>
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As putting data which is read mostly together, we can avoid
unnecessary cache line bouncing.
Other architectures, such as ARM and x86, adopted the same idea.
Acked-by: Catalin Marinas <[email protected]>
Signed-off-by: Jungseok Lee <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
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We want those staging fixes in here as well.
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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__get_cpu_var was removed. Update the comments.
Cc: Fenghua Yu <[email protected]>
Signed-off-by: Christoph Lameter <[email protected]>
Signed-off-by: Tony Luck <[email protected]>
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vsys is the core always-on supply of the Marsboard.
Signed-off-by: Romain Perier <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
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As at91rm9200 is now DT only, there is no need to keep old entry point in this
at91rm9200 System Timer (ST) driver.
Signed-off-by: Arnd Bergmann <[email protected]>
[[email protected]: split patch]
Signed-off-by: Nicolas Ferre <[email protected]>
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GPIO and LED drivers were replaced by generic ones for DT boards. These drivers
were remaining: delete them now. Modifications are also done on the
corresponding header files.
Signed-off-by: Arnd Bergmann <[email protected]>
[[email protected]: split patch]
Signed-off-by: Nicolas Ferre <[email protected]>
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The AT91-specific SoC strucutre "struct at91_init_soc" was filled with specific
!DT initilisation functions. Now that we got rid of the !DT board file
description, remove unneeded functions.
Signed-off-by: Arnd Bergmann <[email protected]>
[[email protected]: split patch]
Signed-off-by: Nicolas Ferre <[email protected]>
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An explicit selection option is not needed for board files so now we select the
board from SoC option.
Signed-off-by: Arnd Bergmann <[email protected]>
[[email protected]: remove option's comments; split patch]
Signed-off-by: Nicolas Ferre <[email protected]>
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Memset on a local variable may be removed when it is called just before the
variable goes out of scope. Using memzero_explicit defeats this
optimization. A simplified version of the semantic patch that makes this
change is as follows: (http://coccinelle.lip6.fr/)
// <smpl>
@@
identifier x;
type T;
@@
{
... when any
T x[...];
... when any
when exists
- memset
+ memzero_explicit
(x,
-0,
...)
... when != x
when strict
}
// </smpl>
This change was suggested by Daniel Borkmann <[email protected]>
Signed-off-by: Julia Lawall <[email protected]>
Acked-by: Ard Biesheuvel <[email protected]>
Signed-off-by: Herbert Xu <[email protected]>
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Memset on a local variable may be removed when it is called just before the
variable goes out of scope. Using memzero_explicit defeats this
optimization. A simplified version of the semantic patch that makes this
change is as follows: (http://coccinelle.lip6.fr/)
// <smpl>
@@
identifier x;
type T;
@@
{
... when any
T x[...];
... when any
when exists
- memset
+ memzero_explicit
(x,
-0,
...)
... when != x
when strict
}
// </smpl>
This change was suggested by Daniel Borkmann <[email protected]>
Signed-off-by: Julia Lawall <[email protected]>
Acked-by: Michael Ellerman <[email protected]>
Signed-off-by: Herbert Xu <[email protected]>
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Memset on a local variable may be removed when it is called just before the
variable goes out of scope. Using memzero_explicit defeats this
optimization. A simplified version of the semantic patch that makes this
change is as follows: (http://coccinelle.lip6.fr/)
// <smpl>
@@
identifier x;
type T;
@@
{
... when any
T x[...];
... when any
when exists
- memset
+ memzero_explicit
(x,
-0,
...)
... when != x
when strict
}
// </smpl>
This change was suggested by Daniel Borkmann <[email protected]>
Signed-off-by: Julia Lawall <[email protected]>
Signed-off-by: Herbert Xu <[email protected]>
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Memset on a local variable may be removed when it is called just before the
variable goes out of scope. Using memzero_explicit defeats this
optimization. A simplified version of the semantic patch that makes this
change is as follows: (http://coccinelle.lip6.fr/)
// <smpl>
@@
identifier x;
type T;
@@
{
... when any
T x[...];
... when any
when exists
- memset
+ memzero_explicit
(x,
-0,
...)
... when != x
when strict
}
// </smpl>
This change was suggested by Daniel Borkmann <[email protected]>
Signed-off-by: Julia Lawall <[email protected]>
Signed-off-by: Herbert Xu <[email protected]>
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Drop BP_IABR_TE, which though used, does not do anything useful. Rename
BP_IABR to BP_CIABR. Renumber the flags.
Signed-off-by: Michael Ellerman <[email protected]>
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This patch enables support for hardware instruction breakpoint in xmon
on POWER8 platform with the help of a new register called the CIABR
(Completed Instruction Address Breakpoint Register). With this patch, a
single hardware instruction breakpoint can be added and cleared during
any active xmon debug session. The hardware based instruction breakpoint
mechanism works correctly with the existing TRAP based instruction
breakpoint available on xmon.
There are no powerpc CPU with CPU_FTR_IABR feature any more. This patch
has re-purposed all the existing IABR related code to work with CIABR
register based HW instruction breakpoint.
This has one odd feature, which is that when we hit a breakpoint xmon
doesn't tell us we have hit the breakpoint. This is because xmon is
expecting bp->address == regs->nip. Because CIABR fires on completition
regs->nip points to the instruction after the breakpoint. We could fix
that, but it would then confuse other parts of the xmon code which think
we need to emulate the instruction. [mpe]
Signed-off-by: Michael Ellerman <[email protected]>
Signed-off-by: Anshuman Khandual <[email protected]>
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Merge updates collected & acked by Ben. A few EEH patches from Gavin,
some mm updates from Aneesh and a few odds and ends.
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If we know that user address space has never executed on other cpus
we could use tlbiel.
Signed-off-by: Aneesh Kumar K.V <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
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Rename invalidate_old_hpte to flush_hash_hugepage and use that in
other places.
Signed-off-by: Aneesh Kumar K.V <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
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Limit the number of gigantic hugepages specified by the
hugepages= parameter to MAX_NUMBER_GPAGES.
Signed-off-by: James Yang <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
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A page fault occurred during reading user stack in oprofile backtrace
would lead following calltrace:
WARNING: at linux/kernel/smp.c:210
Modules linked in:
CPU: 5 PID: 736 Comm: sh Tainted: G W 3.14.23-WR7.0.0.0_standard #1
task: c0000000f6208bc0 ti: c00000007c72c000 task.ti: c00000007c72c000
NIP: c0000000000ed6e4 LR: c0000000000ed5b8 CTR: 0000000000000000
REGS: c00000007c72f050 TRAP: 0700 Tainted: G W (3.14.23-WR7.0.0
tandard)
MSR: 0000000080021000 <CE,ME> CR: 48222482 XER: 00000000
SOFTE: 0
GPR00: c0000000000ed5b8 c00000007c72f2d0 c0000000010aa048 0000000000000005
GPR04: c000000000fdb820 c00000007c72f410 0000000000000001 0000000000000005
GPR08: c0000000010b5768 c000000000f8a048 0000000000000001 0000000000000000
GPR12: 0000000048222482 c00000000fffe580 0000000022222222 0000000010129664
GPR16: 0000000010143cc0 0000000000000000 0000000044444444 0000000000000000
GPR20: c00000007c7221d8 c0000000f638e3c8 000003f15a20120d 0000000000000001
GPR24: 000000005a20120d c00000007c722000 c00000007cdedda8 00003fffef23b160
GPR28: 0000000000000001 c00000007c72f410 c000000000fdb820 0000000000000006
NIP [c0000000000ed6e4] .smp_call_function_single+0x18c/0x248
LR [c0000000000ed5b8] .smp_call_function_single+0x60/0x248
Call Trace:
[c00000007c72f2d0] [c0000000000ed5b8] .smp_call_function_single+0x60/0x248 (unreliable)
[c00000007c72f3a0] [c000000000030810] .__flush_tlb_page+0x164/0x1b0
[c00000007c72f460] [c00000000002e054] .ptep_set_access_flags+0xb8/0x168
[c00000007c72f500] [c0000000001ad3d8] .handle_mm_fault+0x4a8/0xbac
[c00000007c72f5e0] [c000000000bb3238] .do_page_fault+0x3b8/0x868
[c00000007c72f810] [c00000000001e1d0] storage_fault_common+0x20/0x44
Exception: 301 at .__copy_tofrom_user_base+0x54/0x5b0
LR = .op_powerpc_backtrace+0x190/0x20c
[c00000007c72fb00] [c000000000a2ec34] .op_powerpc_backtrace+0x204/0x20c (unreliable)
[c00000007c72fbc0] [c000000000a2b5fc] .oprofile_add_ext_sample+0xe8/0x118
[c00000007c72fc70] [c000000000a2eee0] .fsl_emb_handle_interrupt+0x20c/0x27c
[c00000007c72fd30] [c000000000a2e440] .op_handle_interrupt+0x44/0x58
[c00000007c72fdb0] [c000000000016d68] .performance_monitor_exception+0x74/0x90
[c00000007c72fe30] [c00000000001d8b4] exc_0x260_common+0xfc/0x100
performance_monitor_exception() is executed in a context with interrupt
disabled and preemption enabled. When there is a user space page fault
happened, do_page_fault() invoke in_atomic() to decide whether kernel
should handle such page fault. in_atomic() only check preempt_count.
So need call pagefault_disable() to disable preemption before reading
user stack.
Signed-off-by: Jiang Lu <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
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This fixes a bunch of conflicts prior to merging i915 tree.
Linux 3.18-rc7
Conflicts:
drivers/gpu/drm/exynos/exynos_drm_drv.c
drivers/gpu/drm/i915/i915_drv.c
drivers/gpu/drm/i915/intel_pm.c
drivers/gpu/drm/tegra/dc.c
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With smaller hash page table config, we would end up in situation
where we would be replacing hash page table slot frequently. In
such config, we will find the hpte to be not matching, and we
can do that check without holding the hpte lock. We need to
recheck the hpte again after holding lock.
Signed-off-by: Aneesh Kumar K.V <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
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This is what we get in dmesg when booting a pseries guest and
the hypervisor doesn't provide EEH support.
[ 0.166655] EEH functionality not supported
[ 0.166778] eeh_init: Failed to call platform init function (-22)
Since both powernv_eeh_init() and pseries_eeh_init() already complain when
hitting an error, it is not needed to print more (especially such an
uninformative message).
Signed-off-by: Greg Kurz <[email protected]>
Acked-by: Gavin Shan <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
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Cleanup OpalMCE_* definitions/declarations and other related code which
is not used anymore.
Signed-off-by: Mahesh Salgaonkar <[email protected]>
Acked-by: Benjamin Herrrenschmidt <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
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On PowerNV platform, PHB diag-data is dumped after stopping device
drivers. In case of recursive EEH errors, the kernel is usually
crashed before dumping PHB diag-data for the second EEH error. It's
hard to locate the root cause of the second EEH error without PHB
diag-data.
The patch adds one more EEH option "eeh=early_log", which helps
dumping PHB diag-data immediately once frozen PE is detected, in
order to get the PHB diag-data for the second EEH error.
Signed-off-by: Gavin Shan <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
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In PCI passthrou scenario, we need simulate EEH recovery for Emulex
adapters when their ownership changes, as we did in commit 5cfb20b96
("powerpc/eeh: Emulate EEH recovery for VFIO devices"). Broadcom
BCM5719 adpaters are facing same problem and needs same cure.
Reported-by: Rajeshkumar Subramanian <[email protected]>
Signed-off-by: Gavin Shan <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
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The patch introduces additional flag EEH_PE_RESET to indicate the
corresponding PE is under reset. In turn, the PE retrieval bakcend
on PowerNV platform can return unfrozen state for the EEH core to
moving forward. Flag EEH_PE_CFG_BLOCKED isn't the correct one for
the purpose.
In PCI passthrou case, the problem is more worse: Guest doesn't
recover 6th EEH error. The PE is left in isolated (frozen) and
config blocked state on Broadcom adapters. We can't retrieve the
PE's state correctly any more, even from the host side via sysfs
/sys/bus/pci/devices/xxx/eeh_pe_state.
Reported-by: Rajeshkumar Subramanian <[email protected]>
Signed-off-by: Gavin Shan <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
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The patch refactors eeh_reset_pe() in order for:
* Varied return values for different failure cases.
* Replace pr_err() with pr_warn() and print function name.
* Coding style cleanup.
Signed-off-by: Gavin Shan <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
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IRQ support for Broadcom's bus-axi driver bcma was merged into John
Linville's wireless tree and will show up in 3.19. This patch makes use
of this feature in the DTS file for the the BCM5301X SoCs. I left the
PCIe controller out, because this still needs some discussion.
Signed-off-by: Hauke Mehrtens <[email protected]>
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