aboutsummaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)AuthorFilesLines
2014-12-05ARM: omap2plus_defconfig: enable XHCIFelipe Balbi1-0/+1
AM437x devices have a DWC3 IP inside of them. The host side implementation of DWC3 is XHCI compliant. By enabling XHCI driver, we get the USB host port on AM437x Starter Kit working out of the box. Signed-off-by: Felipe Balbi <[email protected]> Signed-off-by: Tony Lindgren <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
2014-12-05ARM: omap2plus_defconfig: enable AM33XX SoC soundFelipe Balbi1-0/+2
Without this, sound on AM437x Starter Kit will not work. Signed-off-by: Felipe Balbi <[email protected]> Signed-off-by: Tony Lindgren <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
2014-12-05ARM: omap2plus_defconfig: enable EDT FT5X06 touchscreenFelipe Balbi1-0/+1
AM437x Starter Kit ships with EDT FT5306 touchscreen device. By enabling the driver we make sure touchscreen will work out of the box. Signed-off-by: Felipe Balbi <[email protected]> Signed-off-by: Tony Lindgren <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
2014-12-05ARM: omap2plus_defconfig: remove unwanted ethernet driversFelipe Balbi1-0/+16
None of these drivers are known to be used on any platform supported by omap2plus_defconfig, by removing them we get a slight smaller kernel. Signed-off-by: Felipe Balbi <[email protected]> Signed-off-by: Tony Lindgren <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
2014-12-05Merge branch 'devel-stable' into for-nextRussell King14-56/+393
2014-12-05Merge branches 'fixes', 'misc', 'pm' and 'sa1100' into for-nextRussell King70-779/+1027
2014-12-05ARM: 8243/1: sa1100: add a clock alias for sa1111 pcmcia deviceDmitry Eremin-Solenikov1-0/+2
SA-1111 uses internal MMIO space offsets as a device name, so device name for sa1111 pcmcia is 1800 (PCMCIA is at offset 0x1800). Signed-off-by: Dmitry Eremin-Solenikov <[email protected]> Signed-off-by: Russell King <[email protected]>
2014-12-05ARM: 8242/1: sa1100: add cpu clockDmitry Eremin-Solenikov1-7/+34
Both SA1100 framebuffer and PCMCIA drivers require knowledge of cpu frequency to correctly program timings. Currently they receive timing information by calling cpufreq_get(0). However if cpu frequency driver is not enabled (e.g. due to unsupported DRAM chip/board on sa1110) cpufreq_get(0) returns 0, causing incorrect timings to be programmed. Add cpu clock returning cpu frequency, to be used by sa11x0 fb and pcmcia drivers. Signed-off-by: Dmitry Eremin-Solenikov <[email protected]> Signed-off-by: Russell King <[email protected]>
2014-12-05KVM: cpuid: recompute CPUID 0xD.0:EBX,ECXRadim Krčmář1-0/+2
We reused host EBX and ECX, but KVM might not support all features; emulated XSAVE size should be smaller. EBX depends on unknown XCR0, so we default to ECX. SDM CPUID (EAX = 0DH, ECX = 0): EBX Bits 31-00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) required by enabled features in XCR0. May be different than ECX if some features at the end of the XSAVE save area are not enabled. ECX Bit 31-00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) of the XSAVE/XRSTOR save area required by all supported features in the processor, i.e all the valid bit fields in XCR0. Signed-off-by: Radim Krčmář <[email protected]> Tested-by: Wanpeng Li <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2014-12-05kvm: vmx: add nested virtualization support for xsavesWanpeng Li1-1/+22
Add nested virtualization support for xsaves. Signed-off-by: Wanpeng Li <[email protected]> Reviewed-by: Radim Krčmář <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2014-12-05kvm: vmx: add MSR logic for XSAVESWanpeng Li2-1/+29
Add logic to get/set the XSS model-specific register. Signed-off-by: Wanpeng Li <[email protected]> Reviewed-by: Radim Krčmář <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2014-12-05kvm: x86: handle XSAVES vmcs and vmexitWanpeng Li3-1/+28
Initialize the XSS exit bitmap. It is zero so there should be no XSAVES or XRSTORS exits. Signed-off-by: Wanpeng Li <[email protected]> Reviewed-by: Radim Krčmář <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2014-12-05KVM: cpuid: mask more bits in leaf 0xd and subleavesPaolo Bonzini1-2/+8
- EAX=0Dh, ECX=1: output registers EBX/ECX/EDX are reserved. - EAX=0Dh, ECX>1: output register ECX bit 0 is clear for all the CPUID leaves we support, because variable "supported" comes from XCR0 and not XSS. Bits above 0 are reserved, so ECX is overall zero. Output register EDX is reserved. Source: Intel Architecture Instruction Set Extensions Programming Reference, ref. number 319433-022 Reviewed-by: Radim Krčmář <[email protected]> Tested-by: Wanpeng Li <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2014-12-05KVM: cpuid: set CPUID(EAX=0xd,ECX=1).EBX correctlyPaolo Bonzini1-6/+16
This is the size of the XSAVES area. This starts providing guest support for XSAVES (with no support yet for supervisor states, i.e. XSS == 0 always in guests for now). Wanpeng Li suggested testing XSAVEC as well as XSAVES, since in practice no real processor exists that only has one of them, and there is no other way for userspace programs to compute the area of the XSAVEC save area. CPUID(EAX=0xd,ECX=1).EBX provides an upper bound. Suggested-by: Radim Krčmář <[email protected]> Reviewed-by: Radim Krčmář <[email protected]> Tested-by: Wanpeng Li <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2014-12-05kvm: x86: Add kvm_x86_ops hook that enables XSAVES for guestWanpeng Li5-1/+17
Expose the XSAVES feature to the guest if the kvm_x86_ops say it is available. Signed-off-by: Wanpeng Li <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2014-12-05KVM: x86: use F() macro throughout cpuid.cPaolo Bonzini1-7/+7
For code that deals with cpuid, this makes things a bit more readable. Signed-off-by: Paolo Bonzini <[email protected]>
2014-12-05KVM: x86: support XSAVES usage in the hostPaolo Bonzini1-7/+83
Userspace is expecting non-compacted format for KVM_GET_XSAVE, but struct xsave_struct might be using the compacted format. Convert in order to preserve userspace ABI. Likewise, userspace is passing non-compacted format for KVM_SET_XSAVE but the kernel will pass it to XRSTORS, and we need to convert back. Fixes: f31a9f7c71691569359fa7fb8b0acaa44bce0324 Cc: Fenghua Yu <[email protected]> Cc: [email protected] Cc: H. Peter Anvin <[email protected]> Tested-by: Nadav Amit <[email protected]> Reviewed-by: Radim Krčmář <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2014-12-05x86: export get_xsave_addrPaolo Bonzini1-0/+1
get_xsave_addr is the API to access XSAVE states, and KVM would like to use it. Export it. Cc: [email protected] Cc: [email protected] Cc: H. Peter Anvin <[email protected]> Acked-by: Thomas Gleixner <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2014-12-05Merge tag 'kvm-s390-next-20141204' of ↵Paolo Bonzini1-15/+18
git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD KVM: s390: Fixups for kvm/next (3.19) Here we have two fixups of the latest interrupt rework and one architectural fixup.
2014-12-05arm64: remove the unnecessary arm64_swiotlb_init()Ding Tianhong1-1/+0
The commit 3690951fc6d42f3a0903987677d0e592c49dd8db (arm64: Use swiotlb late initialisation) switches the DMA mapping code to swiotlb_tlb_late_init_with_default_size(), the arm64_swiotlb_init() will not used anymore, so remove this function. Signed-off-by: Ding Tianhong <[email protected]> Signed-off-by: Will Deacon <[email protected]>
2014-12-04Revert "ARM: dts: rockchip: temporarily disable smp on rk3288"Olof Johansson1-0/+1
We now have the physical-timers patches lined up as a dependency in this same branch, so we can revert the temporary disablement. This reverts commit b77d43943ea83997c6c37b8831d1561981d499c5. Signed-off-by: Olof Johansson <[email protected]>
2014-12-04Merge branch 'clocksource/physical-timers' into next/dtOlof Johansson2-0/+18
These are a pre-req to get rk3288 SMP to work with some firmwares, so merge it in here as well as in next/drivers. * clocksource/physical-timers: clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers clocksource: arch_timer: Fix code to use physical timers when requested
2014-12-04Merge branch 'clocksource/physical-timers' into next/driversOlof Johansson2-0/+18
* clocksource/physical-timers: clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers clocksource: arch_timer: Fix code to use physical timers when requested
2014-12-04clocksource: arch_timer: Fix code to use physical timers when requestedSonny Rao2-0/+18
This is a bug fix for using physical arch timers when the arch_timer_use_virtual boolean is false. It restores the arch_counter_get_cntpct() function after removal in 0d651e4e "clocksource: arch_timer: use virtual counters" We need this on certain ARMv7 systems which are architected like this: * The firmware doesn't know and doesn't care about hypervisor mode and we don't want to add the complexity of hypervisor there. * The firmware isn't involved in SMP bringup or resume. * The ARCH timer come up with an uninitialized offset between the virtual and physical counters. Each core gets a different random offset. * The device boots in "Secure SVC" mode. * Nothing has touched the reset value of CNTHCTL.PL1PCEN or CNTHCTL.PL1PCTEN (both default to 1 at reset) One example of such as system is RK3288 where it is much simpler to use the physical counter since there's nobody managing the offset and each time a core goes down and comes back up it will get reinitialized to some other random value. Fixes: 0d651e4e65e9 ("clocksource: arch_timer: use virtual counters") Cc: [email protected] Signed-off-by: Sonny Rao <[email protected]> Acked-by: Catalin Marinas <[email protected]> Acked-by: Daniel Lezcano <[email protected]> Signed-off-by: Olof Johansson <[email protected]>
2014-12-04ARM: imx6: fix bogus use of irq_get_irq_dataMarc Zyngier3-17/+26
The imx6 PM code seems to be quite creative in its use of irq_data, using something that is very much a hardware interrupt number where we expect a virtual one. Yes, it worked so far, but that's only luck, and it will definitely explode in 3.19. Fix it by using a pair of helper functions that deal with the actual hardware. Tested-by: Fabio Estevam <[email protected]> Acked-by: Philipp Zabel <[email protected]> Acked-by: Shawn Guo <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Signed-off-by: Olof Johansson <[email protected]>
2014-12-04ARM: imx: irq: fix buggy usage of irq_data irq fieldMarc Zyngier1-9/+9
mach-imx directly references to the irq field in struct irq_data, and uses this to directly poke hardware register. But irq is the *virtual* irq number, something that has nothing to do with the actual HW irq (stored in the hwirq field). And once we put the stacked domain code in action, the whole thing explodes, as these two values are *very* different. Just replacing all instances of irq with hwirq fixes the issue. Tested-by: Fabio Estevam <[email protected]> Acked-by: Shawn Guo <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Signed-off-by: Olof Johansson <[email protected]>
2014-12-04Merge tag 'bcm5301x-dt-2014-12-04' of https://github.com/hauke/linux into ↵Olof Johansson8-1/+375
next/dt Merge "ARM: BCM5301X: DT changes for v3.19 #2" from Hauke Mehrtens: ARM: BCM5301X: dts updates This adds the IRQ number to the main dts file and some new dts files for newly added devices. Signed-off-by: Hauke Mehrtens <[email protected]> * tag 'bcm5301x-dt-2014-12-04' of https://github.com/hauke/linux: ARM: BCM5301X: Add DT for Buffalo WZR-600DHP2 ARM: BCM5301X: Add DT for Asus RT-N18U ARM: BCM5301X: Add DT for Buffalo WZR-1750DHP ARM: BCM5301X: Add DT for Netgear R6300 V2 ARM: BCM5301X: Add buttons for Netgear R6250 ARM: BCM5301X: Add IRQs to Broadcom's bus-axi in DTS file Signed-off-by: Olof Johansson <[email protected]>
2014-12-04ARM: multi_v7_defconfig: enable MAX77686 PMIC drivers for exynos4412-prime ↵Tyler Baker1-0/+4
based SoCs This patch enables the MAX77686 PMIC drivers in the multi_v7_defconfig used on exynos4412-prime family of SoCs [1]. The exynos4412-prime based boards are producing the following runtime errors only on the multi_v7_defconfig [2]: kern.err: deviceless supply vdd_arm not found, using dummy regulator kern.err: exynos-cpufreq exynos-cpufreq: failed to set cpu voltage to 1287500 kern.err: cpufreq: __target_index: Failed to change cpu frequency: -22 I reviewed the exynos_defconfig, which does not produce these runtime errors. It was obvious that the exynos_defconfig has the PMIC drivers enabled, whereas the multi_v7_defconfig does not. This patch has been tested on a odroid-u2 and a odroid-u3 board. It has resolved the runtime errors. Therefore, I purpose we enabled these drivers in the multi_v7_defconfig. [1] http://www.hardkernel.com/main/products/prdt_info.php?g_code=G135270682824 [2] http://storage.armcloud.us/kernel-ci/mainline/v3.18-rc7-48-g7cc78f8/arm-multi_v7_defconfig/lab-tbaker-00/boot-exynos4412-odroidu3.html Signed-off-by: Tyler Baker <[email protected]> Signed-off-by: Olof Johansson <[email protected]>
2014-12-05powerpc/book3s: Fix partial invalidation of TLBs in MCE code.Mahesh Salgaonkar1-2/+2
The existing MCE code calls flush_tlb hook with IS=0 (single page) resulting in partial invalidation of TLBs which is not right. This patch fixes that by passing IS=0xc00 to invalidate whole TLB for successful recovery from TLB and ERAT errors. Cc: [email protected] Signed-off-by: Mahesh Salgaonkar <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2014-12-05powerpc/mm: don't do tlbie for updatepp request with NO HPTE faultAneesh Kumar K.V15-55/+85
upatepp can get called for a nohpte fault when we find from the linux page table that the translation was hashed before. In that case we are sure that there is no existing translation, hence we could avoid doing tlbie. We could possibly race with a parallel fault filling the TLB. But that should be ok because updatepp is only ever relaxing permissions. We also look at linux pte permission bits when filling hash pte permission bits. We also hold the linux pte busy bits while inserting/updating a hashpte entry, hence a paralle update of linux pte is not possible. On the other hand mprotect involves ptep_modify_prot_start which cause a hpte invalidate and not updatepp. Performance number: We use randbox_access_bench written by Anton. Kernel with THP disabled and smaller hash page table size. 86.60% random_access_b [kernel.kallsyms] [k] .native_hpte_updatepp 2.10% random_access_b random_access_bench [.] doit 1.99% random_access_b [kernel.kallsyms] [k] .do_raw_spin_lock 1.85% random_access_b [kernel.kallsyms] [k] .native_hpte_insert 1.26% random_access_b [kernel.kallsyms] [k] .native_flush_hash_range 1.18% random_access_b [kernel.kallsyms] [k] .__delay 0.69% random_access_b [kernel.kallsyms] [k] .native_hpte_remove 0.37% random_access_b [kernel.kallsyms] [k] .clear_user_page 0.34% random_access_b [kernel.kallsyms] [k] .__hash_page_64K 0.32% random_access_b [kernel.kallsyms] [k] fast_exception_return 0.30% random_access_b [kernel.kallsyms] [k] .hash_page_mm With Fix: 27.54% random_access_b random_access_bench [.] doit 22.90% random_access_b [kernel.kallsyms] [k] .native_hpte_insert 5.76% random_access_b [kernel.kallsyms] [k] .native_hpte_remove 5.20% random_access_b [kernel.kallsyms] [k] fast_exception_return 5.12% random_access_b [kernel.kallsyms] [k] .__hash_page_64K 4.80% random_access_b [kernel.kallsyms] [k] .hash_page_mm 3.31% random_access_b [kernel.kallsyms] [k] data_access_common 1.84% random_access_b [kernel.kallsyms] [k] .trace_hardirqs_on_caller Signed-off-by: Aneesh Kumar K.V <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2014-12-04ARM: BCM5301X: Add DT for Buffalo WZR-600DHP2Rafał Miłecki2-1/+59
Signed-off-by: Rafał Miłecki <[email protected]> Signed-off-by: Hauke Mehrtens <[email protected]>
2014-12-04ARM: BCM5301X: Add DT for Asus RT-N18URafał Miłecki3-1/+106
Signed-off-by: Rafał Miłecki <[email protected]> Signed-off-by: Hauke Mehrtens <[email protected]>
2014-12-04ARM: BCM5301X: Add DT for Buffalo WZR-1750DHPRafał Miłecki2-0/+65
Signed-off-by: Rafał Miłecki <[email protected]> Signed-off-by: Hauke Mehrtens <[email protected]>
2014-12-04ARM: BCM5301X: Add DT for Netgear R6300 V2Rafał Miłecki2-1/+87
Signed-off-by: Rafał Miłecki <[email protected]> Signed-off-by: Hauke Mehrtens <[email protected]>
2014-12-04ARM: BCM5301X: Add buttons for Netgear R6250Rafał Miłecki2-0/+26
Signed-off-by: Rafał Miłecki <[email protected]> Signed-off-by: Hauke Mehrtens <[email protected]>
2014-12-04Merge tag 'at91-cleanup5' of ↵Arnd Bergmann16-1703/+5
git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/cleanup Pull "Fifth batch of cleanup/SoC for 3.19" from Nicolas Ferre: - removal of now dead code and AT91-specific driver - removal of !DT initialization in some core AT91 drivers - simplification of Kconfig DT board file selection: now automatic * tag 'at91-cleanup5' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: ARM: at91: remove unused board.h file ARM: at91: remove unneeded header files ARM: at91/clocksource: remove !DT PIT initializations ARM: at91: at91rm9200 ST initialization is now DT only ARM: at91: remove old AT91-specific drivers ARM: at91: cleanup initilisation code by removing dead code ARM: at91/Kconfig: select board files automatically Signed-off-by: Arnd Bergmann <[email protected]>
2014-12-04Merge tag 'at91-defconfig' of ↵Arnd Bergmann2-1/+8
git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/defconfig Pull "First batch of defconfigs for AT91 / 3.19:" from Nicolas Ferre: - use NEON for all C-A5, neon code handles the !NEON case - add new XDMA driver - add some useful drivers as we only have a single defconfig for all AT91SAM9/RM9200 * tag 'at91-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: ARM: at91/defconfig: add DM9000 to at91_dt ARM: at91/defconfig: add QT1070 to at91_dt ARM: at91/defconfig: add TCB PWM driver selection ARM: at91/defconfig: add the XDMA driver ARM: at91: sama5: update defconfig Signed-off-by: Arnd Bergmann <[email protected]>
2014-12-04[media] arm: omap2: rx51-peripherals: fix build warningFelipe Balbi1-0/+2
commit 68a3c0433077 ([media] ARM: OMAP2: RX-51: update si4713 platform data) updated board-rx51-peripherals.c so that si4713 could be easily used on DT boot, but it ended up introducing a build warning whenever si4713 isn't enabled. This patches fixes that warning: arch/arm/mach-omap2/board-rx51-peripherals.c:1000:36: warning: \ ‘rx51_si4713_platform_data’ defined but not used [-Wunused-variable] static struct si4713_platform_data rx51_si4713_platform_data = { Cc: Sebastian Reichel <[email protected]> Cc: Tony Lindgren <[email protected]> Cc: Hans Verkuil <[email protected]> Signed-off-by: Felipe Balbi <[email protected]> Signed-off-by: Mauro Carvalho Chehab <[email protected]>
2014-12-04Merge tag 'v3.19-rockchip-dts4' of ↵Arnd Bergmann6-7/+128
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt Pull "last dts changes for 3.19" from Jason Cooper: - rk3288 thermal driver that got accepted into the thermal tree - mmc fifo sizes for Cortex-A9 SoCs - labels for the leds on the RadxaRock - core system supply for the Marsboard * tag 'v3.19-rockchip-dts4' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: Add input voltage supply regulators in pmic for Marsboard ARM: dts: rockchip: set FIFO size for SDMMC, SDIO and EMMC on rk3066 and rk3188 ARM: dts: rockchip: add label property for leds on Radxa Rock ARM: dts: rockchip: enable thermal on rk3288-evb board ARM: dts: rockchip: add main thermal info to rk3288 ARM: dts: rockchip: add RK3288 Thermal data Signed-off-by: Arnd Bergmann <[email protected]>
2014-12-04ARM: at91/defconfig: add DM9000 to at91_dtNicolas Ferre1-0/+1
This chip is present on at91sam9261ek board: add it to the at91_dt_defconfig. Signed-off-by: Nicolas Ferre <[email protected]>
2014-12-04ARM: at91/defconfig: add QT1070 to at91_dtNicolas Ferre1-0/+1
As this touch button driver is used on at91sam9x5ek, it's better to enable it. Signed-off-by: Nicolas Ferre <[email protected]>
2014-12-04ARM: at91/defconfig: add TCB PWM driver selectionNicolas Ferre2-0/+2
This is the selection of the new PWM driver using TC Blocks. This driver is useful so we enable it in both sama5 and at91_dt defconfig files. Signed-off-by: Nicolas Ferre <[email protected]>
2014-12-04ARM: at91/defconfig: add the XDMA driverNicolas Ferre1-0/+1
Add the Atmel eXtended DMA Controller driver option. This driver is first used on SAMA5D4 SoCs and only relevant in sama5_defconfig file. Signed-off-by: Nicolas Ferre <[email protected]>
2014-12-04ARM: at91: sama5: update defconfigLudovic Desroches1-1/+3
Add neon support for sama5d4 and large blocks/files support. Signed-off-by: Ludovic Desroches <[email protected]> Acked-by: Alexandre Belloni <[email protected]> Signed-off-by: Nicolas Ferre <[email protected]>
2014-12-04ARM: mvebu: use the cpufreq-dt platform_data for independent clocksThomas Petazzoni1-1/+7
This commit adjusts the registration of the cpufreq-dt driver in the mvebu platform to indicate to the cpufreq driver that the platform has independent clocks for each CPU. Signed-off-by: Thomas Petazzoni <[email protected]> Acked-by: Jason Cooper <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
2014-12-04Merge tag 'tegra-for-3.19-dt' of ↵Arnd Bergmann10-61/+71
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt2 Pull "ARM: tegra: Device tree changes for v3.19" from Thierry Reding: The bulk of these changes add memory controller nodes for Tegra30, Tegra114 and Tegra124. The memory controller implements an IOMMU that the display controllers are attached to. This allows them to scan out physically non-contiguous framebuffers and removes one of the primary users of CMA. The only other change adds a new MIPI pad control bank to the pin controller on Tegra124. The corresponding driver patch for this went into v3.18 as: 3ccc11f6b82c pinctrl: tegra: Add MIPI pad control * tag 'tegra-for-3.19-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: Enable IOMMU for display controllers on Tegra124 ARM: tegra: Enable IOMMU for display controllers on Tegra114 ARM: tegra: Enable IOMMU for display controllers on Tegra30 ARM: tegra: Add memory controller support for Tegra124 ARM: tegra: Add memory controller support for Tegra114 ARM: tegra: Add memory controller support for Tegra30 ARM: tegra: Add APB_MISC_GP as a MIPI pad control bank These additional commits are merged as dependencies: memory: Add NVIDIA Tegra memory controller support of: Add NVIDIA Tegra memory controller binding ARM: tegra: Move AHB Kconfig to drivers/amba amba: Add Kconfig file clk: tegra: Implement memory-controller clock powerpc/iommu: Rename iommu_[un]map_sg functions iommu: Improve error handling when setting bus iommu iommu: Do more input validation in iommu_map_sg() iommu: Add iommu_map_sg() function Signed-off-by: Arnd Bergmann <[email protected]>
2014-12-04Merge tag 'tegra-for-3.19-iommu' of ↵Arnd Bergmann7-37/+28
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers Pull "ARM: tegra: IOMMU support for v3.19" from Thierry Reding: This adds the driver pieces required for IOMMU support on Tegra30, Tegra114 and Tegra124. * tag 'tegra-for-3.19-iommu' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: Add NVIDIA Tegra memory controller support of: Add NVIDIA Tegra memory controller binding ARM: tegra: Move AHB Kconfig to drivers/amba amba: Add Kconfig file clk: tegra: Implement memory-controller clock powerpc/iommu: Rename iommu_[un]map_sg functions iommu: Improve error handling when setting bus iommu iommu: Do more input validation in iommu_map_sg() iommu: Add iommu_map_sg() function Signed-off-by: Arnd Bergmann <[email protected]>
2014-12-04arm64: amd-seattle: Fix PCI bus range due to SMMU limitationSuravee Suthikulpanit1-1/+1
Since PCIe is using SMMUv1 which only supports 15-bit stream ID, only 7-bit PCI bus id is used to specify stream ID. Therefore, we only limit the PCI bus range to 0x7f. Signed-off-by: Suravee Suthikulpanit <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
2014-12-04Merge tag 'zynq-cleanup-for-3.19' of https://github.com/Xilinx/linux-xlnx ↵Arnd Bergmann3-17/+0
into next/cleanup Pull "arm: Xilinx Zynq cleanup patches for v3.19" from Michal Simek: - Remove unused file and declaration * tag 'zynq-cleanup-for-3.19' of https://github.com/Xilinx/linux-xlnx: ARM: zynq: Remove secondary_startup() declaration from header ARM: zynq: Actually remove hotplug.c Signed-off-by: Arnd Bergmann <[email protected]>
2014-12-04Merge tag 'zynq-dt-for-3.19' of https://github.com/Xilinx/linux-xlnx into ↵Arnd Bergmann7-2/+70
next/dt Pull "arm: Xilinx Zynq dt patches for v3.19" from Michal Simek: - Declare Digilent and vendor - Add Zybo board support - Fix VDMA documentation to be align with the driver * tag 'zynq-dt-for-3.19' of https://github.com/Xilinx/linux-xlnx: arm: dts: zynq: Add Digilent ZYBO board arm: dts: zynq: Move crystal freq. to board level doc: dt: vendor-prefixes: Add Digilent Inc Documentation: devicetree: Fix Xilinx VDMA specification Signed-off-by: Arnd Bergmann <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.