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2024-09-11LoongArch: Revert qspinlock to test-and-set simple lock on VMBibo Mao6-2/+64
Similar with x86, when VM is detected, revert to a simple test-and-set lock to avoid the horrors of queue preemption. Tested on 3C5000 Dual-way machine with 32 cores and 2 numa nodes, test case is kcbench on kernel mainline 6.10, the detailed command is "kcbench --src /root/src/linux" Performance on host machine kernel compile time performance impact Original 150.29 seconds With patch 150.19 seconds almost no impact Performance on virtual machine: 1. 1 VM with 32 vCPUs and 2 numa node, numa node pinned kernel compile time performance impact Original 170.87 seconds With patch 171.73 seconds almost no impact 2. 2 VMs, each VM with 32 vCPUs and 2 numa node, numa node pinned kernel compile time performance impact Original 2362.04 seconds With patch 354.73 seconds +565% Signed-off-by: Bibo Mao <[email protected]> Signed-off-by: Huacai Chen <[email protected]>
2024-09-11cpufreq: amd-pstate: Merge amd_pstate_highest_perf_set() into ↵Mario Limonciello1-0/+16
amd_get_boost_ratio_numerator() The special case in amd_pstate_highest_perf_set() is the value used for calculating the boost numerator. Merge this into amd_get_boost_ratio_numerator() and then use that to calculate boost ratio. This allows dropping more special casing of the highest perf value. Reviewed-by: Gautham R. Shenoy <[email protected]> Signed-off-by: Mario Limonciello <[email protected]>
2024-09-11x86/amd: Detect preferred cores in amd_get_boost_ratio_numerator()Mario Limonciello1-10/+83
AMD systems that support preferred cores will use "166" as their numerator for max frequency calculations instead of "255". Add a function for detecting preferred cores by looking at the highest perf value on all cores. If preferred cores are enabled return 166 and if disabled the value in the highest perf register. As the function will be called multiple times, cache the values for the boost numerator and if preferred cores will be enabled in global variables. Reviewed-by: Gautham R. Shenoy <[email protected]> Signed-off-by: Mario Limonciello <[email protected]>
2024-09-11x86/amd: Move amd_get_highest_perf() out of amd-pstateMario Limonciello1-0/+30
amd_pstate_get_highest_perf() is a helper used to get the highest perf value on AMD systems. It's used in amd-pstate as part of preferred core handling, but applicable for acpi-cpufreq as well. Move it out to cppc handling code as amd_get_highest_perf(). Reviewed-by: Perry Yuan <[email protected]> Reviewed-by: Gautham R. Shenoy <[email protected]> Signed-off-by: Mario Limonciello <[email protected]>
2024-09-11ACPI: CPPC: Adjust debug messages in amd_set_max_freq_ratio() to warnMario Limonciello1-3/+3
If the boost ratio isn't calculated properly for the system for any reason this can cause other problems that are non-obvious. Raise all messages to warn instead. Suggested-by: Perry Yuan <[email protected]> Reviewed-by: Perry Yuan <[email protected]> Reviewed-by: Gautham R. Shenoy <[email protected]> Signed-off-by: Mario Limonciello <[email protected]>
2024-09-11ACPI: CPPC: Drop check for non zero perf ratioMario Limonciello1-6/+1
perf_ratio is a u64 and SCHED_CAPACITY_SCALE is a large number. Shifting by one will never have a zero value. Drop the check. Suggested-by: Gautham R. Shenoy <[email protected]> Reviewed-by: Gautham R. Shenoy <[email protected]> Signed-off-by: Mario Limonciello <[email protected]>
2024-09-11x86/amd: Rename amd_get_highest_perf() to amd_get_boost_ratio_numerator()Mario Limonciello2-15/+32
The function name is ambiguous because it returns an intermediate value for calculating maximum frequency rather than the CPPC 'Highest Perf' register. Rename the function to clarify its use and allow the function to return errors. Adjust the consumer in acpi-cpufreq to catch errors. Reviewed-by: Gautham R. Shenoy <[email protected]> Signed-off-by: Mario Limonciello <[email protected]>
2024-09-11x86/amd: Move amd_get_highest_perf() from amd.c to cppc.cMario Limonciello2-16/+16
To prepare to let amd_get_highest_perf() detect preferred cores it will require CPPC functions. Move amd_get_highest_perf() to cppc.c to prepare for 'preferred core detection' rework. No functional changes intended. Reviewed-by: Perry Yuan <[email protected]> Reviewed-by: Gautham R. Shenoy <[email protected]> Signed-off-by: Mario Limonciello <[email protected]>
2024-09-11platform/x86: intel_scu_ipc: Move intel_scu_ipc.h out of arch/x86/include/asmMika Westerberg3-70/+3
This is a platform/x86 library that is mostly being used by other drivers not directly under arch/x86 anyway (with the exception of the Intel MID setup code) so it makes sense that it lives under the platform_data/x86/ directory instead. No functional changes intended. Suggested-by: Andy Shevchenko <[email protected]> Signed-off-by: Mika Westerberg <[email protected]> Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Hans de Goede <[email protected]>
2024-09-11Merge tag 'v6.11-next-defconfig' of ↵Arnd Bergmann1-0/+2
https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/defconfig mt8365: - Enable audio handled by the SoC and the PMIC codec. * tag 'v6.11-next-defconfig' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: arm64: defconfig: enable mt8365 sound Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-09-11Merge tag 'riscv-config-for-v6.12' of ↵Arnd Bergmann1-0/+7
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/defconfig RISC-V config for v6.12 Two patches, enabling clock and pinctrl support in defconfig for Sopghgo devices. Signed-off-by: Conor Dooley <[email protected]> * tag 'riscv-config-for-v6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: defconfig: Enable pinctrl support for CV18XX Series SoC riscv: defconfig: sophgo: enable clks for sg2042 Link: https://lore.kernel.org/r/20240910-annex-ravage-07d63041a7c5@spud Signed-off-by: Arnd Bergmann <[email protected]>
2024-09-11Merge tag 'riscv-soc-fixes-for-v6.11-final' of ↵Arnd Bergmann1-0/+6
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes RISC-V soc fixes for v6.11-final StarFive: A fix to return one of the clocks on the JH7110 from 1 GHz to 1.5 GHz Signed-off-by: Conor Dooley <[email protected]> * tag 'riscv-soc-fixes-for-v6.11-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz Link: https://lore.kernel.org/r/20240909-hybrid-groovy-601a33b5b309@spud Signed-off-by: Arnd Bergmann <[email protected]>
2024-09-11arm64: dts: allwinner: h5: NanoPi NEO Plus2: Use regulators for pioKryštof Černý1-0/+12
Pin controllers pio and r_pio will have proper regulators assigned. Signed-off-by: Kryštof Černý <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Link: https://lore.kernel.org/r/[email protected] [[email protected]: Make "h5" lowercase to match most commits] Signed-off-by: Chen-Yu Tsai <[email protected]>
2024-09-11Merge tag 'arm-soc/for-6.12/devicetree-arm64' of ↵Arnd Bergmann4-1/+349
https://github.com/Broadcom/stblinux into soc/dt This pull request contains Broadcom ARM64 SoCs Device Tree changes for 6.12, please pull the following: - Andrea adds a minimal Device Tree for the Raspberry Pi 5 (2712) - Stefan adjusts the bcm2837/bcm2712 bcm2836-l1-intc node name to conform to the binding changes * tag 'arm-soc/for-6.12/devicetree-arm64' of https://github.com/Broadcom/stblinux: ARM: dts: bcm2837/bcm2712: adjust local intc node names arm64: dts: broadcom: Add minimal support for Raspberry Pi 5 Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-09-11Merge tag 'v6.11-next-dts64' of ↵Arnd Bergmann20-63/+1066
https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt mt63xx: - add ADC node to the different PMICs mt7981: - Add SPI controller nodes. mt8183: - use referenced label for DSI endpoint. - disable soc_data efuse node, which does not has any cell definde (kukui). - fix the regulator tree (kukui). - fix potential deadlock by removing not needed clock in the MFG async power domain. - add DPI node. mt8186: - fix opp-supported-hw mask for GPU. - add lvts thermal sensor node. - add thermal zones. - fix reserved memory region of ADSP firmware (corsola). - add power domain to DPI node. - add SVS node. - fix internal display by disabling the external display temporarily (corsola). mt8188: - add thermal sensor for the AP. - add thermal zones. mt8195: - fix pull resistance for hdmi pins (cherry). - remove keyboard backlight node (cherry), this is detected through ChromeOS EC communication. - fix warning in mdp3 driver by providing a phandel to the SCP. - fix probe error of the USB controller by disabeling USB3 on the controller (cherry). - assign per default both phys to the USB controller (cherry). - fix binding validation by re-ordering the dp_intf clocks. mt8365: - add AFE audio controller. - add AFE and audio codec support (evk). mt8395: - fix probe error of the USB controller by disabeling USB3 on the controller (radax-nio-12l). - assign per default both phys to the USB controller (genio, kontron, radax). * tag 'v6.11-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: (25 commits) arm64: dts: mediatek: add audio support for mt8365-evk arm64: dts: mediatek: add afe support for mt8365 SoC arm64: dts: mediatek: mt8186-corsola: Disable DPI display interface arm64: dts: mediatek: mt8186: Add svs node arm64: dts: mediatek: mt8186: Add power domain for DPI arm64: dts: mediatek: mt8195: Correct clock order for dp_intf* arm64: dts: mt8183: add dpi node to mt8183 arm64: dts: mediatek: mt8186-corsola: Update ADSP reserved memory region arm64: dts: mediatek: mt8183: Remove clock from mfg_async power domain arm64: dts: mt8183-kukui: clean up regulator tree arm64: dts: mediatek: mt7981: add SPI controllers arm64: dts: mediatek: mt8183-kukui: Disable unused efuse at 8000000 arm64: dts: mediatek: mt8188: add default thermal zones arm64: dts: mediatek: mt8188: add lvts definitions arm64: dts: mediatek: mt8186: add default thermal zones arm64: dts: mediatek: mt8186: add lvts definitions arm64: dts: mediatek: mt8195: Assign USB 3.0 PHY to xhci1 by default arm64: dts: mediatek: mt8395-nio-12l: Mark USB 3.0 on xhci1 as disabled arm64: dts: mediatek: mt8195-cherry: Mark USB 3.0 on xhci1 as disabled arm64: dts: mediatek: mt8195: Add SCP phandle to MDP3 DMA controller ... Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-09-11Merge tag 'aspeed-6.12-devicetree' of ↵Arnd Bergmann31-311/+8936
https://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into soc/dt ASPEED device tree updates for 6.12 - New machines * IBM P11 AST2600 BMC machines, named Blueridge and Fuji * Meta's Catalina AST2600 BMC - Updates to harma, minerva, mtmitchell, mtjade, system1, SPC621D8HM3 - Various changes to the dtsi to keep the YAML checker happy * tag 'aspeed-6.12-devicetree' of https://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: (52 commits) ARM: dts: aspeed: catalina: Update io expander line names ARM: dts: aspeed: catalina: Add pdb cpld io expander ARM: dts: aspeed: harma: Remove pca9546 ARM: dts: aspeed: harma: Fix spi-gpio dtb_check warnings ARM: dts: aspeed: harma: Enable mctp controller ARM: dts: aspeed: harma: Add temperature device ARM: dts: aspeed: harma: Add fru device ARM: dts: aspeed: harma: Remove multi-host property ARM: dts: aspeed: harma: Add power monitor xdp710 ARM: dts: aspeed: harma: Add ina238 ARM: dts: aspeed: harma: Add sgpio name ARM: dts: aspeed: harma: Add VR devices ARM: dts: aspeed: harma: Revise hsc chip ARM: dts: aspeed-g6: Drop cells properties from ethernet nodes ARM: dts: aspeed-g6: Use generic 'ethernet' for ftgmac100 nodes ARM: dts: aspeed: Clean up AST2500 pinctrl properties ARM: dts: aspeed: Remove undocumented XDMA nodes ARM: dts: aspeed: Specify required properties for sram node ARM: dts: aspeed: Specify correct generic compatible for CVIC ARM: dts: aspeed: Fix coprocessor interrupt controller node name ... Link: https://lore.kernel.org/r/CACPK8XeGDUrbJ-OaxqQBR=aVVYyrKGnvT1ZKXO0vPHpsjQ_i9g@mail.gmail.com Signed-off-by: Arnd Bergmann <[email protected]>
2024-09-11Merge tag 'v6.12-rockchip-dts32-2' of ↵Arnd Bergmann2-0/+407
https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt More pwm, i2s and i2c nodes for the RV1126 soc. * tag 'v6.12-rockchip-dts32-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: Add pwm node for RV1126 ARM: dts: rockchip: Add i2s0 node for RV1126 ARM: dts: rockchip: Add i2c3 node for RV1126 Link: https://lore.kernel.org/r/1862312.dTVjPilprF@diego Signed-off-by: Arnd Bergmann <[email protected]>
2024-09-11Merge tag 'v6.12-rockchip-dts64-2' of ↵Arnd Bergmann10-21/+2213
https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt New boards the Odroid-M2 and GameForce Ace, CAN on rk3568, RGA2 on rk3588 and some non-critical dts cleanups. * tag 'v6.12-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: add CAN0 and CAN1 interfaces to mecsbc board arm64: dts: rockchip: add CAN-FD controller nodes to rk3568 arm64: dts: rockchip: remove duplicate nodes from dts for ROCK 4SE arm64: dts: rockchip: Add GameForce Ace dt-bindings: arm: rockchip: Add GameForce Ace arm64: dts: rockchip: rk3588s fix sdio pins to pull up arm64: dts: rockchip: Add RGA2 support to rk3588 arm64: dts: rockchip: Add missing tshut props to tsadc on quartz64-b arm64: dts: rockchip: Add Hardkernel ODROID-M2 dt-bindings: arm: rockchip: Add Hardkernel ODROID-M2 arm64: dts: rockchip: drop hp-pin-name property from audio card on nanopc-t6 Link: https://lore.kernel.org/r/11663608.jrtcCam0TZ@diego Signed-off-by: Arnd Bergmann <[email protected]>
2024-09-11Merge tag 'arm-soc/for-6.12/devicetree' of ↵Arnd Bergmann6-663/+411
https://github.com/Broadcom/stblinux into soc/dt This pull request contains Broadcom SoCs Device Tree changes for 6.12, please pull the following: - Krzysztof documents the AVS monitor binding present on 2711 (Raspberry Pi 4) - Rafal updates the Broadcom Northstar DTS files to use the recent NVMEM binding - Artur factors the nodes between the BCM21664 and BCM23550 SoCs since they are nearly identical - Stefan converts the bcm2835-system-timer and bcm2836-l1-intc to a YAML binding syntax * tag 'arm-soc/for-6.12/devicetree' of https://github.com/Broadcom/stblinux: dt-bindings: interrupt-controller: convert bcm2836-l1-intc to yaml dt-bindings: timer: convert bcm2835-system-timer bindings to YAML ARM: dts: bcm-mobile: Split out nodes used by both BCM21664 and BCM23550 ARM: dts: broadcom: bcm21664: Move chosen node into Garnet DTS ARM: dts: broadcom: convert NVMEM content to layout syntax dt-bindings: soc: bcm: document brcm,bcm2711-avs-monitor Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-09-11Merge tag 'dt-cleanup-6.12' of ↵Arnd Bergmann5-7/+7
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt Minor improvements in ARM DTS for v6.12 1. Realview: correct unit addresses (e.g. drop when not valid). 2. Nuvoton: correct node name to match bindings. * tag 'dt-cleanup-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt: ARM: dts: nuvoton: wpcm450: align LED and GPIO keys node name with bindings arm: dts: realview: Add/drop missing/spurious unit-addreses Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-09-11Merge tag 'dt64-cleanup-6.12' of ↵Arnd Bergmann10-40/+37
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt Minor improvements in ARM64 DTS for v6.12 1. APM: correct node name to match bindings. 2. Spreadtrum: correct node names to match bindings, order properties to match DTS coding style and put SPDX identifier at top of the file as expected usually. * tag 'dt64-cleanup-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt: arm64: dts: sprd: move/add SPDX license to top of the file arm64: dts: sprd: reorder clock-names after clocks arm64: dts: sprd: rename SDHCI and fuel gauge nodes to match bindings arm64: dts: apm: storm: Rename menetphy@3 to ethernet-phy@3 Signed-off-by: Arnd Bergmann <[email protected]>
2024-09-11Merge v6.11-rc7 into drm-nextSimona Vetter69-250/+502
Thomas needs 5a498d4d06d6 ("drm/fbdev-dma: Only install deferred I/O if necessary") in drm-misc, so start the backmerge cascade. Signed-off-by: Simona Vetter <[email protected]>
2024-09-10riscv: Disable preemption while handling PR_RISCV_CTX_SW_FENCEI_OFFCharlie Jenkins1-6/+6
The icache will be flushed in switch_to() if force_icache_flush is true, or in flush_icache_deferred() if icache_stale_mask is set. Between setting force_icache_flush to false and calculating the new icache_stale_mask, preemption needs to be disabled. There are two reasons for this: 1. If CPU migration happens between force_icache_flush = false, and the icache_stale_mask is set, an icache flush will not be emitted. 2. smp_processor_id() is used in set_icache_stale_mask() to mark the current CPU as not needing another flush since a flush will have happened either by userspace or by the kernel when performing the migration. smp_processor_id() is currently called twice with preemption enabled which causes a race condition. It allows icache_stale_mask to be populated with inconsistent CPU ids. Resolve these two issues by setting the icache_stale_mask before setting force_icache_flush to false, and using get_cpu()/put_cpu() to obtain the smp_processor_id(). Signed-off-by: Charlie Jenkins <[email protected]> Fixes: 6b9391b581fd ("riscv: Include riscv_set_icache_flush_ctx prctl") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
2024-09-10KVM: arm64: Register ptdump with debugfs on guest creationSebastian Ene5-0/+293
While arch/*/mem/ptdump handles the kernel pagetable dumping code, introduce KVM/ptdump to show the guest stage-2 pagetables. The separation is necessary because most of the definitions from the stage-2 pagetable reside in the KVM path and we will be invoking functionality specific to KVM. Introduce the PTDUMP_STAGE2_DEBUGFS config. When a guest is created, register a new file entry under the guest debugfs dir which allows userspace to show the contents of the guest stage-2 pagetables when accessed. [maz: moved function prototypes from kvm_host.h to kvm_mmu.h] Signed-off-by: Sebastian Ene <[email protected]> Reviewed-by: Vincent Donnefort <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Marc Zyngier <[email protected]>
2024-09-10arm64: ptdump: Don't override the level when operating on the stage-2 tablesSebastian Ene1-2/+2
Ptdump uses the init_mm structure directly to dump the kernel pagetables. When ptdump is called on the stage-2 pagetables, this mm argument is not used. Prevent the level from being overwritten by checking the argument against NULL. Signed-off-by: Sebastian Ene <[email protected]> Acked-by: Will Deacon <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Marc Zyngier <[email protected]>
2024-09-10arm64: ptdump: Use the ptdump description from a local contextSebastian Ene2-5/+9
Rename the attributes description array to allow the parsing method to use the description from a local context. To be able to do this, store a pointer to the description array in the state structure. This will allow for the later introduced callers (stage_2 ptdump) to specify their own page table description format to the ptdump parser. Signed-off-by: Sebastian Ene <[email protected]> Acked-by: Will Deacon <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Marc Zyngier <[email protected]>
2024-09-10arm64: ptdump: Expose the attribute parsing functionalitySebastian Ene2-45/+52
Reuse the descriptor parsing functionality to keep the same output format as the original ptdump code. In order for this to happen, move the state tracking objects into a common header. [maz: Fixed note_page() stub as suggested by Will] Signed-off-by: Sebastian Ene <[email protected]> Acked-by: Will Deacon <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Marc Zyngier <[email protected]>
2024-09-10KVM: arm64: Add memory length checks and remove inline in do_ffa_mem_xferSnehal Koukuntla1-6/+15
When we share memory through FF-A and the description of the buffers exceeds the size of the mapped buffer, the fragmentation API is used. The fragmentation API allows specifying chunks of descriptors in subsequent FF-A fragment calls and no upper limit has been established for this. The entire memory region transferred is identified by a handle which can be used to reclaim the transferred memory. To be able to reclaim the memory, the description of the buffers has to fit in the ffa_desc_buf. Add a bounds check on the FF-A sharing path to prevent the memory reclaim from failing. Also do_ffa_mem_xfer() does not need __always_inline, except for the BUILD_BUG_ON() aspect, which gets moved to a macro. [maz: fixed the BUILD_BUG_ON() breakage with LLVM, thanks to Wei-Lin Chang for the timely report] Fixes: 634d90cf0ac65 ("KVM: arm64: Handle FFA_MEM_LEND calls from the host") Cc: [email protected] Reviewed-by: Sebastian Ene <[email protected]> Signed-off-by: Snehal Koukuntla <[email protected]> Reviewed-by: Oliver Upton <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Marc Zyngier <[email protected]>
2024-09-10arm64: esr: Define ESR_ELx_EC_* constants as ULAnastasia Belova1-44/+44
Add explicit casting to prevent expantion of 32th bit of u32 into highest half of u64 in several places. For example, in inject_abt64: ESR_ELx_EC_DABT_LOW << ESR_ELx_EC_SHIFT = 0x24 << 26. This operation's result is int with 1 in 32th bit. While casting this value into u64 (esr is u64) 1 fills 32 highest bits. Found by Linux Verification Center (linuxtesting.org) with SVACE. Cc: <[email protected]> Fixes: aa8eff9bfbd5 ("arm64: KVM: fault injection into a guest") Signed-off-by: Anastasia Belova <[email protected]> Acked-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/stable/20240910085016.32120-1-abelova%40astralinux.ru Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Will Deacon <[email protected]>
2024-09-10arm64: pkeys: remove redundant WARNJoey Gouly1-2/+0
FEAT_PAN3 is present if FEAT_S1POE is, this WARN() was to represent that. However execute_only_pkey() is always called by mmap(), even on a CPU without POE support. Rather than making the WARN() conditional, just delete it. Reported-by: Naresh Kamboju <[email protected]> Link: https://lore.kernel.org/linux-arm-kernel/CA+G9fYvarKEPN3u1Ogw2pcw4h6r3OMzg+5qJpYkAXRunAEF_0Q@mail.gmail.com/ Signed-off-by: Joey Gouly <[email protected]> Cc: Will Deacon <[email protected]> Cc: Catalin Marinas <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Will Deacon <[email protected]>
2024-09-10KVM: arm64: Move pagetable definitions to common headerSebastian Ene2-42/+42
In preparation for using the stage-2 definitions in ptdump, move some of these macros in the common header. Signed-off-by: Sebastian Ene <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Marc Zyngier <[email protected]>
2024-09-10Merge tag 'arm-soc/for-6.12/soc' of https://github.com/Broadcom/stblinux ↵Arnd Bergmann1-0/+1
into soc/arm This pull request contains Broadcom 32-bit SoC changes for 6.12, please pull the following: - Florian enables the ARM GICv3 driver since newer STB chips make use of a GIC-600 controller * tag 'arm-soc/for-6.12/soc' of https://github.com/Broadcom/stblinux: ARM: bcm: Select ARM_GIC_V3 for ARCH_BRCMSTB
2024-09-10Merge tag 'mvebu-arm-6.12-1' of ↵Arnd Bergmann10-12/+15
https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/arm mvebu arm for 6.12 (part 1) Fix a few warning error with W=1 Switch orion5x to new sys-off handler API * tag 'mvebu-arm-6.12-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: ARM: dove: Drop a write-only variable ARM: orion5x: Switch to new sys-off handler API ARM: mvebu: Warn about memory chunks too small for DDR training Signed-off-by: Arnd Bergmann <[email protected]>
2024-09-10xen: add capability to remap non-RAM pages to different PFNsJuergen Gross2-0/+66
When running as a Xen PV dom0 it can happen that the kernel is being loaded to a guest physical address conflicting with the host memory map. In order to be able to resolve this conflict, add the capability to remap non-RAM areas to different guest PFNs. A function to use this remapping information for other purposes than doing the remap will be added when needed. As the number of conflicts should be rather low (currently only machines with max. 1 conflict are known), save the remap data in a small statically allocated array. Signed-off-by: Juergen Gross <[email protected]> Reviewed-by: Jan Beulich <[email protected]> Signed-off-by: Juergen Gross <[email protected]>
2024-09-10Merge branch 'linus' into timers/coreThomas Gleixner189-700/+1170
To update with the latest fixes.
2024-09-10Merge branch 'perf/urgent' into perf/core, to pick up fixesIngo Molnar1-5/+42
Signed-off-by: Ingo Molnar <[email protected]>
2024-09-10perf/x86/intel: Allow to setup LBR for counting event for BPFKan Liang1-2/+6
The BPF subsystem may capture LBR data on a counting event. However, the current implementation assumes that LBR can/should only be used with sampling events. For instance, retsnoop tool ([0]) makes an extensive use of this functionality and sets up perf event as follows: struct perf_event_attr attr; memset(&attr, 0, sizeof(attr)); attr.size = sizeof(attr); attr.type = PERF_TYPE_HARDWARE; attr.config = PERF_COUNT_HW_CPU_CYCLES; attr.sample_type = PERF_SAMPLE_BRANCH_STACK; attr.branch_sample_type = PERF_SAMPLE_BRANCH_KERNEL; To limit the LBR for a sampling event is to avoid unnecessary branch stack setup for a counting event in the sample read. Because LBR is only read in the sampling event's overflow. Although in most cases LBR is used in sampling, there is no HW limit to bind LBR to the sampling mode. Allow an LBR setup for a counting event unless in the sample read mode. Fixes: 85846b27072d ("perf/x86: Add PERF_X86_EVENT_NEEDS_BRANCH_STACK flag") Closes: https://lore.kernel.org/lkml/[email protected]/ Reported-by: Andrii Nakryiko <[email protected]> Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Acked-by: Andrii Nakryiko <[email protected]> Tested-by: Andrii Nakryiko <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected]
2024-09-10perf/x86/intel/cstate: Clean up cpumask and hotplugKan Liang1-137/+5
There are three cstate PMUs with different scopes, core, die and module. The scopes are supported by the generic perf_event subsystem now. Set the scope for each PMU and remove all the cpumask and hotplug codes. Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-09-10xen: move max_pfn in xen_memory_setup() out of function scopeJuergen Gross1-26/+26
Instead of having max_pfn as a local variable of xen_memory_setup(), make it a static variable in setup.c instead. This avoids having to pass it to subfunctions, which will be needed in more cases in future. Rename it to ini_nr_pages, as the value denotes the currently usable number of memory pages as passed from the hypervisor at boot time. Signed-off-by: Juergen Gross <[email protected]> Tested-by: Marek Marczykowski-Górecki <[email protected]> Reviewed-by: Jan Beulich <[email protected]> Signed-off-by: Juergen Gross <[email protected]>
2024-09-10xen: move checks for e820 conflicts further upJuergen Gross1-22/+22
Move the checks for e820 memory map conflicts using the xen_chk_is_e820_usable() helper further up in order to prepare resolving some of the possible conflicts by doing some e820 map modifications, which must happen before evaluating the RAM layout. Signed-off-by: Juergen Gross <[email protected]> Tested-by: Marek Marczykowski-Górecki <[email protected]> Reviewed-by: Jan Beulich <[email protected]> Signed-off-by: Juergen Gross <[email protected]>
2024-09-10xen: introduce generic helper checking for memory map conflictsJuergen Gross3-11/+31
When booting as a Xen PV dom0 the memory layout of the dom0 is modified to match that of the host, as this requires less changes in the kernel for supporting Xen. There are some cases, though, which are problematic, as it is the Xen hypervisor selecting the kernel's load address plus some other data, which might conflict with the host's memory map. These conflicts are detected at boot time and result in a boot error. In order to support handling at least some of these conflicts in future, introduce a generic helper function which will later gain the ability to adapt the memory layout when possible. Add the missing check for the xen_start_info area. Note that possible p2m map and initrd memory conflicts are handled already by copying the data to memory areas not conflicting with the memory map. The initial stack allocated by Xen doesn't need to be checked, as early boot code is switching to the statically allocated initial kernel stack. Initial page tables and the kernel itself will be handled later. Signed-off-by: Juergen Gross <[email protected]> Tested-by: Marek Marczykowski-Górecki <[email protected]> Reviewed-by: Jan Beulich <[email protected]> Signed-off-by: Juergen Gross <[email protected]>
2024-09-10xen: use correct end address of kernel for conflict checkingJuergen Gross1-1/+1
When running as a Xen PV dom0 the kernel is loaded by the hypervisor using a different memory map than that of the host. In order to minimize the required changes in the kernel, the kernel adapts its memory map to that of the host. In order to do that it is checking for conflicts of its load address with the host memory map. Unfortunately the tested memory range does not include the .brk area, which might result in crashes or memory corruption when this area does conflict with the memory map of the host. Fix the test by using the _end label instead of __bss_stop. Fixes: 808fdb71936c ("xen: check for kernel memory conflicting with memory layout") Signed-off-by: Juergen Gross <[email protected]> Tested-by: Marek Marczykowski-Górecki <[email protected]> Reviewed-by: Jan Beulich <[email protected]> Signed-off-by: Juergen Gross <[email protected]>
2024-09-10powerpc: Switch back to struct platform_driver::remove()Uwe Kleine-König7-7/+7
After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all pwm drivers to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. Signed-off-by: Uwe Kleine-König <[email protected]> Signed-off-by: Michael Ellerman <[email protected]> Link: https://msgid.link/[email protected]
2024-09-10powerpc/pseries/eeh: Fix pseries_eeh_err_injectNarayana Murty N3-5/+44
VFIO_EEH_PE_INJECT_ERR ioctl is currently failing on pseries due to missing implementation of err_inject eeh_ops for pseries. This patch implements pseries_eeh_err_inject in eeh_ops/pseries eeh_ops. Implements support for injecting MMIO load/store error for testing from user space. The check on PCI error type (bus type) code is moved to platform code, since the eeh_pe_inject_err can be allowed to more error types depending on platform requirement. Removal of the check for 'type' in eeh_pe_inject_err() doesn't impact PowerNV as pnv_eeh_err_inject() already has an equivalent check in place. Signed-off-by: Narayana Murty N <[email protected]> Reviewed-by: Vaibhav Jain <[email protected]> Signed-off-by: Michael Ellerman <[email protected]> Link: https://msgid.link/[email protected]
2024-09-09treewide: correct the typo 'retun'WangYuli1-1/+1
There are some spelling mistakes of 'retun' in comments which should be instead of 'return'. Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: WangYuli <[email protected]> Signed-off-by: Andrew Morton <[email protected]>
2024-09-09mm: pass vm_flags to generic_get_unmapped_area()Mark Brown1-2/+2
In preparation for using vm_flags to ensure guard pages for shadow stacks supply them as an argument to generic_get_unmapped_area(). The only user outside of the core code is the PowerPC book3s64 implementation which is trivially wrapping the generic implementation in the radix_enabled() case. No functional changes. Link: https://lkml.kernel.org/r/20240904-mm-generic-shadow-stack-guard-v2-2-a46b8b6dc0ed@kernel.org Signed-off-by: Mark Brown <[email protected]> Acked-by: Lorenzo Stoakes <[email protected]> Reviewed-by: Liam R. Howlett <[email protected]> Acked-by: Michael Ellerman <[email protected]> Cc: Alexander Gordeev <[email protected]> Cc: Andreas Larsson <[email protected]> Cc: Borislav Petkov <[email protected]> Cc: Christian Borntraeger <[email protected]> Cc: Christophe Leroy <[email protected]> Cc: Chris Zankel <[email protected]> Cc: Dave Hansen <[email protected]> Cc: David S. Miller <[email protected]> Cc: "Edgecombe, Rick P" <[email protected]> Cc: Gerald Schaefer <[email protected]> Cc: Guo Ren <[email protected]> Cc: Heiko Carstens <[email protected]> Cc: Helge Deller <[email protected]> Cc: "H. Peter Anvin" <[email protected]> Cc: Huacai Chen <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Ivan Kokshaysky <[email protected]> Cc: James Bottomley <[email protected]> Cc: John Paul Adrian Glaubitz <[email protected]> Cc: Matt Turner <[email protected]> Cc: Max Filippov <[email protected]> Cc: Naveen N Rao <[email protected]> Cc: Nicholas Piggin <[email protected]> Cc: Richard Henderson <[email protected]> Cc: Rich Felker <[email protected]> Cc: Russell King <[email protected]> Cc: Sven Schnelle <[email protected]> Cc: Thomas Bogendoerfer <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Vasily Gorbik <[email protected]> Cc: Vineet Gupta <[email protected]> Cc: Vlastimil Babka <[email protected]> Cc: WANG Xuerui <[email protected]> Cc: Yoshinori Sato <[email protected]> Signed-off-by: Andrew Morton <[email protected]>
2024-09-09mm: make arch_get_unmapped_area() take vm_flags by defaultMark Brown16-42/+36
Patch series "mm: Care about shadow stack guard gap when getting an unmapped area", v2. As covered in the commit log for c44357c2e76b ("x86/mm: care about shadow stack guard gap during placement") our current mmap() implementation does not take care to ensure that a new mapping isn't placed with existing mappings inside it's own guard gaps. This is particularly important for shadow stacks since if two shadow stacks end up getting placed adjacent to each other then they can overflow into each other which weakens the protection offered by the feature. On x86 there is a custom arch_get_unmapped_area() which was updated by the above commit to cover this case by specifying a start_gap for allocations with VM_SHADOW_STACK. Both arm64 and RISC-V have equivalent features and use the generic implementation of arch_get_unmapped_area() so let's make the equivalent change there so they also don't get shadow stack pages placed without guard pages. The arm64 and RISC-V shadow stack implementations are currently on the list: https://lore.kernel.org/r/20240829-arm64-gcs-v12-0-42fec94743 https://lore.kernel.org/lkml/[email protected]/ Given the addition of the use of vm_flags in the generic implementation we also simplify the set of possibilities that have to be dealt with in the core code by making arch_get_unmapped_area() take vm_flags as standard. This is a bit invasive since the prototype change touches quite a few architectures but since the parameter is ignored the change is straightforward, the simplification for the generic code seems worth it. This patch (of 3): When we introduced arch_get_unmapped_area_vmflags() in 961148704acd ("mm: introduce arch_get_unmapped_area_vmflags()") we did so as part of properly supporting guard pages for shadow stacks on x86_64, which uses a custom arch_get_unmapped_area(). Equivalent features are also present on both arm64 and RISC-V, both of which use the generic implementation of arch_get_unmapped_area() and will require equivalent modification there. Rather than continue to deal with having two versions of the functions let's bite the bullet and have all implementations of arch_get_unmapped_area() take vm_flags as a parameter. The new parameter is currently ignored by all implementations other than x86. The only caller that doesn't have a vm_flags available is mm_get_unmapped_area(), as for the x86 implementation and the wrapper used on other architectures this is modified to supply no flags. No functional changes. Link: https://lkml.kernel.org/r/20240904-mm-generic-shadow-stack-guard-v2-0-a46b8b6dc0ed@kernel.org Link: https://lkml.kernel.org/r/20240904-mm-generic-shadow-stack-guard-v2-1-a46b8b6dc0ed@kernel.org Signed-off-by: Mark Brown <[email protected]> Acked-by: Lorenzo Stoakes <[email protected]> Reviewed-by: Liam R. Howlett <[email protected]> Acked-by: Helge Deller <[email protected]> [parisc] Cc: Alexander Gordeev <[email protected]> Cc: Andreas Larsson <[email protected]> Cc: Borislav Petkov <[email protected]> Cc: Christian Borntraeger <[email protected]> Cc: Christophe Leroy <[email protected]> Cc: Chris Zankel <[email protected]> Cc: Dave Hansen <[email protected]> Cc: David S. Miller <[email protected]> Cc: "Edgecombe, Rick P" <[email protected]> Cc: Gerald Schaefer <[email protected]> Cc: Guo Ren <[email protected]> Cc: Heiko Carstens <[email protected]> Cc: "H. Peter Anvin" <[email protected]> Cc: Huacai Chen <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Ivan Kokshaysky <[email protected]> Cc: James Bottomley <[email protected]> Cc: John Paul Adrian Glaubitz <[email protected]> Cc: Matt Turner <[email protected]> Cc: Max Filippov <[email protected]> Cc: Michael Ellerman <[email protected]> Cc: Naveen N Rao <[email protected]> Cc: Nicholas Piggin <[email protected]> Cc: Richard Henderson <[email protected]> Cc: Rich Felker <[email protected]> Cc: Russell King <[email protected]> Cc: Sven Schnelle <[email protected]> Cc: Thomas Bogendoerfer <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Vasily Gorbik <[email protected]> Cc: Vineet Gupta <[email protected]> Cc: Vlastimil Babka <[email protected]> Cc: WANG Xuerui <[email protected]> Cc: Yoshinori Sato <[email protected]> Signed-off-by: Andrew Morton <[email protected]>
2024-09-10RISC-V: configs: enable I2C_DESIGNWARE_CORE with I2C_DESIGNWARE_PLATFORMHeikki Krogerus3-0/+3
The dependency handling of the Synopsys DesignWare I2C adapter drivers is going to be changed so that the glue drivers for the PCI and platform buses depend on I2C_DESIGNWARE_CORE. Cc: Paul Walmsley <[email protected]> Cc: Palmer Dabbelt <[email protected]> Cc: Albert Ou <[email protected]> Cc: [email protected] Signed-off-by: Heikki Krogerus <[email protected]> Acked-by: Jarkko Nikula <[email protected]> Signed-off-by: Andi Shyti <[email protected]>
2024-09-10mips: configs: enable I2C_DESIGNWARE_CORE with I2C_DESIGNWARE_PLATFORMHeikki Krogerus1-0/+1
The dependency handling of the Synopsys DesignWare I2C adapter drivers is going to be changed so that the glue drivers for the PCI and platform buses depend on I2C_DESIGNWARE_CORE. Cc: Alexandre Belloni <[email protected]> Cc: [email protected] Cc: Thomas Bogendoerfer <[email protected]> Cc: [email protected] Signed-off-by: Heikki Krogerus <[email protected]> Acked-by: Jarkko Nikula <[email protected]> Signed-off-by: Andi Shyti <[email protected]>
2024-09-10arm64: defconfig: enable I2C_DESIGNWARE_CORE with I2C_DESIGNWARE_PLATFORMHeikki Krogerus1-0/+1
The dependency handling of the Synopsys DesignWare I2C adapter drivers is going to be changed so that the glue drivers for the PCI and platform buses depend on I2C_DESIGNWARE_CORE. Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Cc: [email protected] Signed-off-by: Heikki Krogerus <[email protected]> Acked-by: Jarkko Nikula <[email protected]> Signed-off-by: Andi Shyti <[email protected]>