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2020-11-30arm64: dts: meson-axg: add PCIe nodesNeil Armstrong1-0/+61
This adds the nodes for the : - AXG PCIe PHY, using the shared analog PCIe/MIPI DSI PHY - 2x AXG PCIe controllers Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Kevin Hilman <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-11-30arm64: dts: meson-axg: add MIPI DSI PHY nodesNeil Armstrong1-0/+19
This adds the nodes for : - MIPI DSI+PCIe analog phy - MIPI D-PHY Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Kevin Hilman <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-11-30arm64: dts: meson-axg: add PWRC nodeNeil Armstrong1-0/+42
This adds the power controller PWRC node and the corresponding ethernet power domain. Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Kevin Hilman <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-11-30arm64: dts: meson: enable rtc node on Khadas VIM1/VIM2 boardsChristian Hewitt2-4/+2
Enable the rtc node on VIM1/VIM2 boards so users can simply attach a power cell and use the on-board RTC without modifying the device-tree. Cold boot with no cell attached is gracefully handled: VIM2:~ # dmesg | grep rtc [ 7.716150] rtc-hym8563 1-0051: no valid clock/calendar values available [ 7.716957] rtc-hym8563 1-0051: registered as rtc0 [ 7.729850] rtc-hym8563 1-0051: no valid clock/calendar values available [ 7.729877] rtc-hym8563 1-0051: hctosys: unable to read the hardware clock [ 8.126768] rtc-hym8563 1-0051: no valid clock/calendar values available Warm boot (and any boot with cell attached) recalls stored values resulting in consistently faster (re)boot times: VIM2:~ # dmesg | grep rtc [ 7.441671] rtc-hym8563 1-0051: registered as rtc0 [ 7.442663] rtc-hym8563 1-0051: setting system clock to 2020-11-16T05:49:59 UTC (1605505799) Suggested-by: Artem Lapkin <[email protected]> Signed-off-by: Christian Hewitt <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Kevin Hilman <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-12-01net: Add SO_BUSY_POLL_BUDGET socket optionBjörn Töpel4-0/+4
This option lets a user set a per socket NAPI budget for busy-polling. If the options is not set, it will use the default of 8. Signed-off-by: Björn Töpel <[email protected]> Signed-off-by: Daniel Borkmann <[email protected]> Reviewed-by: Jakub Kicinski <[email protected]> Link: https://lore.kernel.org/bpf/[email protected]
2020-12-01net: Introduce preferred busy-pollingBjörn Töpel4-0/+8
The existing busy-polling mode, enabled by the SO_BUSY_POLL socket option or system-wide using the /proc/sys/net/core/busy_read knob, is an opportunistic. That means that if the NAPI context is not scheduled, it will poll it. If, after busy-polling, the budget is exceeded the busy-polling logic will schedule the NAPI onto the regular softirq handling. One implication of the behavior above is that a busy/heavy loaded NAPI context will never enter/allow for busy-polling. Some applications prefer that most NAPI processing would be done by busy-polling. This series adds a new socket option, SO_PREFER_BUSY_POLL, that works in concert with the napi_defer_hard_irqs and gro_flush_timeout knobs. The napi_defer_hard_irqs and gro_flush_timeout knobs were introduced in commit 6f8b12d661d0 ("net: napi: add hard irqs deferral feature"), and allows for a user to defer interrupts to be enabled and instead schedule the NAPI context from a watchdog timer. When a user enables the SO_PREFER_BUSY_POLL, again with the other knobs enabled, and the NAPI context is being processed by a softirq, the softirq NAPI processing will exit early to allow the busy-polling to be performed. If the application stops performing busy-polling via a system call, the watchdog timer defined by gro_flush_timeout will timeout, and regular softirq handling will resume. In summary; Heavy traffic applications that prefer busy-polling over softirq processing should use this option. Example usage: $ echo 2 | sudo tee /sys/class/net/ens785f1/napi_defer_hard_irqs $ echo 200000 | sudo tee /sys/class/net/ens785f1/gro_flush_timeout Note that the timeout should be larger than the userspace processing window, otherwise the watchdog will timeout and fall back to regular softirq processing. Enable the SO_BUSY_POLL/SO_PREFER_BUSY_POLL options on your socket. Signed-off-by: Björn Töpel <[email protected]> Signed-off-by: Daniel Borkmann <[email protected]> Reviewed-by: Jakub Kicinski <[email protected]> Link: https://lore.kernel.org/bpf/[email protected]
2020-11-30arm64: defconfig: Enable RTC_DRV_HYM8563Jagan Teki1-0/+1
RTC HYM8563 used in the ARM64 Rockchip SoC's SDIO power sequence enablement. Enable it as module. Signed-off-by: Jagan Teki <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2020-11-30signal/parisc: Remove parisc specific definition of __ARCH_UAPI_SA_FLAGSEric W. Biederman1-2/+0
Randy Dunlap wrote: > On 11/27/20 10:43 AM, Randy Dunlap wrote: > > > on parisc, _SA_SIGGFAULT is undefined and causing build errors. > > > > commit 23acdc76f1798b090bb9dcc90671cd29d929834e > > Author: Peter Collingbourne <[email protected]> > > Date: Thu Nov 12 18:53:34 2020 -0800 > > > > signal: clear non-uapi flag bits when passing/returning sa_flags > > > > > > > > _SA_SIGGFAULT is not used or defined anywhere else in the > > kernel source tree. > > > Here is the build error (although it should be obvious): > > ../kernel/signal.c: In function 'do_sigaction': > ../arch/parisc/include/asm/signal.h:24:30: error: '_SA_SIGGFAULT' undeclared (first use in this function) > 24 | #define __ARCH_UAPI_SA_FLAGS _SA_SIGGFAULT > | ^~~~~~~~~~~~~ Stephen Rothwell pointed out: > _SA_SIGGFAULT was removed by commit > > 41f5a81c07cd ("parisc: Drop HP-UX specific fcntl and signal flags") > > which was added to Linus' tree in v5.10-rc1. Solve this by removing the the parisc specific definition of __ARCH_UAPI_SA_FLAGS that was just added. Reported-by: Randy Dunlap <[email protected]> Acked-by: Randy Dunlap <[email protected]> # build-tested Fixes: 23acdc76f179 ("signal: clear non-uapi flag bits when passing/returning sa_flags") Signed-off-by: "Eric W. Biederman" <[email protected]>
2020-11-30arm64: mte: Fix typo in macro definitionVincenzo Frascino1-1/+1
UL in the definition of SYS_TFSR_EL1_TF1 was misspelled causing compilation issues when trying to implement in kernel MTE async mode. Fix the macro correcting the typo. Note: MTE async mode will be introduced with a future series. Fixes: c058b1c4a5ea ("arm64: mte: system register definitions") Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Signed-off-by: Vincenzo Frascino <[email protected]> Acked-by: Catalin Marinas <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Will Deacon <[email protected]>
2020-11-30arm64: dts: qcom: c630: Define eDP bridge and panelBjorn Andersson1-0/+100
The Lenovo Yoga C630 drives the Boe NV133FHM-N61 eDP display from DSI using a TI SN65DSI86 bridge chip on I2C 10. Define the bridge and eDP panel and enable the display blocks. Tested-by: Steev Klimaszewski <[email protected]> Acked-by: Shawn Guo <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-11-30arm64: dts: qcom: c630: Fix pinctrl pins propertiesBjorn Andersson1-4/+4
The "pins" property takes an array of pin _names_, not pin numbers. Fix this. Tested-by: Steev Klimaszewski <[email protected]> Fixes: 44acee207844 ("arm64: dts: qcom: Add Lenovo Yoga C630") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-11-30arm64: dts: qcom: c630: Polish i2c-hid devicesBjorn Andersson1-13/+18
The numbering of the i2c busses differs from ACPI and a number of typos was made in the original patch. Further more the irq flags for the various resources was not correct and i2c3 only has one of the two client devices active in any one device. Also label the various devices, for easier comparison with the ACPI tables. Tested-by: Steev Klimaszewski <[email protected]> Fixes: 44acee207844 ("arm64: dts: qcom: Add Lenovo Yoga C630") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-11-30arm64: dts: qcom: sc7180: Add lpass cpu node for I2S driverAjit Pandey1-0/+69
Add the I2S controller node to sc7180 dtsi. Add pinmux for primary and secondary I2S. Reviewed-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Ajit Pandey <[email protected]> Signed-off-by: Cheng-Yi Chiang <[email protected]> Signed-off-by: V Sujith Kumar Reddy <[email protected]> Signed-off-by: Srinivasa Rao Mandadapu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-11-30arm64: dts: ipq6018: Add the QPIC peripheral nodesKathiravan T2-0/+57
Add the QPIC BAM and QPIC NAND controller support and enable the same in board DTS file. Co-developed-by: Anusha Canchi Ramachandra Rao <[email protected]> Signed-off-by: Anusha Canchi Ramachandra Rao <[email protected]> Signed-off-by: Kathiravan T <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-11-30arm64: dts: sdm845: Add interconnect properties for QUPGeorgi Djakov1-0/+160
Add the interconnects DT property to describe the ports for GENI QUPs on the sdm845 platform. Signed-off-by: Georgi Djakov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-11-30arm64: dts: qcom: c630: Expose LID eventsBjorn Andersson1-0/+39
The LID state can be read from GPIO 124 and the "tablet mode" from GPIO 95, expose these to the system using gpio-keys and mark the falling edge of the LID state as a wakeup-source - to wake the system from suspend. Tested-by: Steev Klimaszewski <[email protected]> Acked-by: Shawn Guo <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-11-30arm64: dts: qcom: c630: Re-enable apps_smmuBjorn Andersson1-5/+0
Re-enable the apps_smmu now that the arm-smmu driver supports stream mapping handoff from firmware. Tested-by: Steev Klimaszewski <[email protected]> Acked-by: Shawn Guo <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-11-30Merge tag 'aspeed-5.11-soc' of ↵Arnd Bergmann3-0/+15
git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into arm/drivers ASPEED soc driver updates for 5.11 New drivers: - SoC info driver to expose revision information New features: - AST2600 support for the LPC control driver. This includes setting the LPC2AHB bridge up in a backwards compatible manner. Cleanups: - LPC control - Kconfig - Bindings updates for AST2600 strings * tag 'aspeed-5.11-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed: soc: aspeed: Enable drivers with ARCH_ASPEED soc: aspeed: Fix a reference leak in aspeed_socinfo_init() soc: aspeed: remove unneeded semicolon soc: aspeed-lpc-ctrl: Fix driver name soc: aspeed-lpc-ctrl: Fix whitespace soc: aspeed-lpc-ctrl: LPC to AHB mapping on ast2600 soc: aspeed-lpc-ctrl: Fail probe of lpc-ctrl if reserved memory is not aligned soc: aspeed: lpc: Add AST2600 compatible strings dt-bindings: aspeed-lpc: Add AST2600 compatible strings ARM: dts: aspeed: Add silicon id node soc: aspeed: Add soc info driver dt-bindings: aspeed: Add silicon id node to SCU soc: aspeed: Improve kconfig Link: https://lore.kernel.org/r/CACPK8Xe=9ezhyWRMqVOEQr7SU1YoYfVBGGdGzjmE4SiBr--vJQ@mail.gmail.com Signed-off-by: Arnd Bergmann <[email protected]>
2020-11-30dts: qcom: sdm845: Add dt entries to support crypto engine.Thara Gopinath1-0/+30
Add crypto engine (CE) and CE BAM related nodes and definitions to "sdm845.dtsi". Signed-off-by: Thara Gopinath <[email protected]> Link: https://lore.kernel.org/r/[email protected] [bjorn: Replaced RPMH_CE_CLK constant, for now] Signed-off-by: Bjorn Andersson <[email protected]>
2020-11-30arm64: dts: rockchip: add isp and sensors for ScarletEddie Cai1-0/+74
Enable ISP and camera sensor ov2685 and ov5695 for Scarlet Chromebook Verified with: make ARCH=arm64 dtbs_check Signed-off-by: Shunqian Zheng <[email protected]> Signed-off-by: Eddie Cai <[email protected]> Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Helen Koike <[email protected]> Reviewed-by: Tomasz Figa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2020-11-30arm64: dts: rockchip: add isp0 node for rk3399Shunqian Zheng1-0/+26
RK3399 has two ISPs, but only isp0 was tested. Add isp0 node in rk3399 dtsi Verified with: make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/media/rockchip-isp1.yaml Signed-off-by: Shunqian Zheng <[email protected]> Signed-off-by: Jacob Chen <[email protected]> Signed-off-by: Helen Koike <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2020-11-30KVM: arm64: Advertise ID_AA64PFR0_EL1.CSV3=1 if the CPUs are Meltdown-safeMarc Zyngier3-5/+18
Cores that predate the introduction of ID_AA64PFR0_EL1.CSV3 to the ARMv8 architecture have this field set to 0, even of some of them are not affected by the vulnerability. The kernel maintains a list of unaffected cores (A53, A55 and a few others) so that it doesn't impose an expensive mitigation uncessarily. As we do for CSV2, let's expose the CSV3 property to guests that run on HW that is effectively not vulnerable. This can be reset to zero by writing to the ID register from userspace, ensuring that VMs can be migrated despite the new property being set. Reported-by: Will Deacon <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2020-11-30arm64: dts: armada-3720-turris-mox: add 3W power capability to SFP cageMarek Behún1-0/+1
Add maximum-power-milliwatt = 3000 to SFP node of Turris MOX. Signed-off-by: Marek Behún <[email protected]> Fixes: 7109d817db2e ("arm64: dts: marvell: add DTS for Turris Mox") Cc: Gregory CLEMENT <[email protected]> Cc: Andrew Lunn <[email protected]> Cc: Rob Herring <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Gregory CLEMENT <[email protected]>
2020-11-30arm64: dts: marvell: keep SMMU disabled by default for Armada 7040 and 8040Tomasz Nowicki2-8/+0
FW has to configure devices' StreamIDs so that SMMU is able to lookup context and do proper translation later on. For Armada 7040 & 8040 and publicly available FW, most of the devices are configured properly, but some like ap_sdhci0, PCIe, NIC still remain unassigned which results in SMMU faults about unmatched StreamID (assuming ARM_SMMU_DISABLE_BYPASS_BY_DEFAUL=y). Since there is dependency on custom FW let SMMU be disabled by default. People who still willing to use SMMU need to enable manually and use ARM_SMMU_DISABLE_BYPASS_BY_DEFAUL=n (or via kernel command line) with extra caution. Fixes: 83a3545d9c37 ("arm64: dts: marvell: add SMMU support") Cc: <[email protected]> # 5.9+ Signed-off-by: Tomasz Nowicki <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2020-11-30arm64: dts: mcbin-singleshot: add heartbeat LEDTomasz Maciej Nowak1-0/+22
With board revision 1.3, SolidRun moved the power LED to the middle of the board. In old place of power LED a GPIO controllable heartbeat LED was added. This commit only touches Single Shot variant, since only this variant is all revision 1.3. Reported-by: Alexandra Alth <[email protected]> Signed-off-by: Tomasz Maciej Nowak <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2020-11-30arm64: dts: marvell: cp11x: Harmonize xHCI DT nodes nameSerge Semin1-2/+2
In accordance with the Generic xHCI bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "generic-xhci"-compatible nodes are correctly named. Signed-off-by: Serge Semin <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2020-11-30arm64: dts: freescale: update calibration table for TMU moduleYuantian Tang3-101/+112
Update the calibration table to make the temperature more accurate. Three platforms have been updated: ls1012a, ls1043a and ls1046a. Signed-off-by: Yuantian Tang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: freescale: sl28: combine SPI MTD partitionsMichael Walle1-11/+1
The upstream port, doesn't really follow the vendor partitioning. The bootloader partition has one U-Boot FIT image containing all needed bits and pieces. Even today the bootloader is already larger than the current "bootloader" partition. Thus, fold all the partitions into one and keep the environment one. The latter is still valid. We keep the failsafe partitions because the first half of the SPI flash is preinstalled by the vendor and immutable. Fixes: 815364d0424e ("arm64: dts: freescale: add Kontron sl28 support") Signed-off-by: Michael Walle <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: ls1028a: add optee nodeMichael Walle1-0/+8
Add the optee node which can either be enabled by a specific board or by the bootloader. Signed-off-by: Michael Walle <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: ls1028a: fix FlexSPI clock inputMichael Walle1-1/+1
On the LS1028A the FlexSPI clock is connected to the first HWA output, see Figure 7 "Clock subsystem block diagram". Fixes: c77fae5ba09a ("arm64: dts: ls1028a: Add FlexSPI support") Signed-off-by: Michael Walle <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: ls1028a: fix ENETC PTP clock inputMichael Walle1-1/+1
On the LS1028A the ENETC reference clock is connected to 4th HWA output, see Figure 7 "Clock subsystem block diagram". The PHC may run with a wrong frequency. ptp_qoriq_auto_config() will read the clock speed of the clock given in the device tree. It is likely that, on the reference board this wasn't noticed because both clocks have the same frequency. But this must not be always the case. Fix it. Fixes: 49401003e260 ("arm64: dts: fsl: ls1028a: add ENETC 1588 timer node") Signed-off-by: Michael Walle <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: imx: Fix imx8mm-kontron-n801x-s.dtb targetNathan Chancellor1-1/+1
While running 'make dtbs_install', the following error occurs: make[3]: *** No rule to make target 'rootfs/freescale/imx8mm-kontron-n801x-s.dts', needed by '__dtbs_install'. It should be .dtb, not .dts. Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards") Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Nathan Chancellor <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: imx8mn-evk: add IR supportJoakim Zhang1-0/+14
Add IR support on i.MX8MN EVK board. Signed-off-by: Joakim Zhang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: imx8mm-evk: add IR supportJoakim Zhang1-0/+14
Add IR support on i.MX8MM EVK board. Signed-off-by: Joakim Zhang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: imx8mq-evk: add linux,autosuspend-period property for IRJoakim Zhang1-0/+1
Add linux,autosuspend-period property for IR, details please refer to: commit ff1c9223b7b8 ("media: rc: gpio-ir-recv: add QoS support for cpuidle system") Signed-off-by: Joakim Zhang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: imx8mp-evk: add CAN supportJoakim Zhang2-0/+92
Add CAN device node and pinctrl on i.MX8MP evk board. Signed-off-by: Joakim Zhang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: imx8mq-evk: Add spdif sound card supportShengjiu Wang2-0/+86
There are two spdif IP on imx8mq, spdif1 is for normal spdif device, spdif2 is for HDMI ARC interface. Enable these spdif sound card in this patch. Signed-off-by: Shengjiu Wang <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: imx8mq: Configure clock rate for audio pllsShengjiu Wang1-3/+17
Configure clock rate for audio plls. audio pll1 is used as parent clock for clocks that is multiple of 8kHz. audio pll2 is used as parent clock for clocks that is multiple of 11kHz. Signed-off-by: Shengjiu Wang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: layerscape: Add PCIe EP node for ls1088aXiaowei Bao1-0/+31
Add PCIe EP node for ls1088a to support EP mode. Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Reviewed-by: Andrew Murray <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: lx2160ardb: add nodes for the AQR107 PHYsIoana Ciornei1-0/+32
Annotate the EMDIO1 node and describe the 2 AQR107 PHYs found on the LX2160ARDB board. Also, add the necessary phy-handles for DPMACs 3 and 4 to their associated PHY. Signed-off-by: Ioana Ciornei <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: lx2160a: add PCS MDIO and PCS PHY nodesIoana Ciornei1-18/+270
Add PCS MDIO nodes for the internal MDIO buses on the LX2160A, along with their internal PCS PHYs, which will be used when the DPMAC is in TYPE_PHY mode. Also, rename the dpmac@x nodes to ethernet@x in order to be compliant with the naming convention used by ethernet controllers. Signed-off-by: Ioana Ciornei <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: ls208xa: add PCS MDIO and PCS PHY nodesIoana Ciornei2-16/+272
Add PCS MDIO nodes for the internal MDIO buses on the LS208x SoCs, along with their internal PCS PHYs which will be used when the DPMAC object is in TYPE_PHY mode. Also, rename the dpmac@x nodes to ethernet@x in order to be compliant with the naming convention used by ethernet controllers. Signed-off-by: Ioana Ciornei <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: ls2088ardb: add PHY nodes for the AQR405 PHYsIoana Ciornei1-0/+44
Annotate the EMDIO2 node and describe the other 4 10GBASER PHYs found on the LS2088ARDB board. Also, add phy-handles for DPMACs 5-8 to their associated PHY. Signed-off-by: Ioana Ciornei <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: ls2088ardb: add PHY nodes for the CS4340 PHYsIoana Ciornei1-0/+44
Annotate the EMDIO1 node and describe the 4 10GBASER PHYs found on the LS2088ARDB board. Also, add phy-handles for DPMACs 1-4 to their associated PHY. Signed-off-by: Ioana Ciornei <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: ls208xa: add the external MDIO nodesIoana Ciornei1-0/+18
Add the external MDIO device nodes found in the WRIOP global memory region. This is needed for management of external PHYs. Signed-off-by: Ioana Ciornei <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: ls1088ardb: add necessary DTS nodes for DPMAC2Ioana Ciornei2-0/+32
Annotate the external MDIO2 node and describe the 10GBASER PHY found on the LS1088ARDB board and add a phy-handle for DPMAC2 to link it. Also, add the internal PCS MDIO node for the internal MDIO buses found on the LS1088A SoC along with its internal PCS PHY and link the corresponding DPMAC to the PCS through the pcs-handle. Signed-off-by: Ioana Ciornei <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: ls1088ardb: add QSGMII PHY nodesIoana Ciornei2-10/+160
Annotate the external MDIO1 node and describe the 8 QSGMII PHYs found on the LS1088ARDB board and add phy-handles for DPMACs 3-10 to its associated PHY. Also, add the internal PCS MDIO nodes for the internal MDIO buses found on the LS1088A SoC along with their internal PCS PHY and link the corresponding DPMAC to the PCS through the pcs-handle. Also, rename the dpmac@x nodes to ethernet@x in order to be compliant with the naming convention used by ethernet controllers. Signed-off-by: Ioana Ciornei <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: ls1088a: add external MDIO device nodesIoana Ciornei1-0/+18
Add the external MDIO device nodes found in the WRIOP global memory region. This is needed for management of external PHYs. Signed-off-by: Ioana Ciornei <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: lx2160a: add device tree for lx2162aqds boardMeenakshi Aggarwal2-0/+335
Add device tree support for LX2162AQDS board. LX2162A has same die as of LX2160A with different packaging. Signed-off-by: Ioana Ciornei <[email protected]> Signed-off-by: Kuldeep Singh <[email protected]> Signed-off-by: Meenakshi Aggarwal <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-30arm64: dts: imx8mm-beacon-som: Fix whitespace issueAdam Ford1-148/+148
The pinmux subnodes are indented too much. This patch does nothing more than remove an extra tab. There are no functional changes. Signed-off-by: Adam Ford <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
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