aboutsummaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)AuthorFilesLines
2015-02-17MIPS: asm: futex: Set the appropriate ISA level for MIPS R6Markos Chandras1-4/+4
MIPS R6 changed the opcodes for LL/SC instructions so we need to set the appropriate ISA level. Cc: Matthew Fortune <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2015-02-17MIPS: asm: bitops: Update ISA constraints for MIPS R6 supportMarkos Chandras1-15/+15
MIPS R6 changed the opcodes for LL/SC instructions so we need to set the correct ISA level. Cc: Matthew Fortune <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2015-02-17MIPS: asm: atomic: Update ISA constraints for MIPS R6 supportMarkos Chandras1-6/+6
MIPS R6 changed the opcodes for LL/SC instructions so we need to set the correct ISA level. Cc: Matthew Fortune <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2015-02-17MIPS: asm: cmpxchg: Update ISA constraints for MIPS R6 supportMarkos Chandras1-5/+5
MIPS R6 changed the opcodes for LL/SC instructions so we need to set the correct ISA. Cc: Matthew Fortune <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2015-02-17MIPS: Use the new "ZC" constraint for MIPS R6Markos Chandras1-1/+6
GCC versions supporting MIPS R6 use the ZC constraint to enforce a 9-bit offset for MIPS R6. We will use that for all MIPS R6 LL/SC instructions. Cc: Matthew Fortune <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2015-02-17MIPS: asm: Rename GCC_OFF12_ASM to GCC_OFF_SMALL_ASMMarkos Chandras9-93/+93
The GCC_OFF12_ASM macro is used for 12-bit immediate constrains but we will also use it for 9-bit constrains on MIPS R6 so we rename it to something more appropriate. Cc: Maciej W. Rozycki <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2015-02-17MIPS: asm: spram: Add new symbol for MIPS scratch pad storageMarkos Chandras3-3/+8
MIPS R6, just like MIPS R2, have scratch pad storage, so add a new symbol which is selected by MIPS R2 and R6. Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00389.html Cc: Maciej W. Rozycki <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2015-02-17MIPS: asm: r4kcache: Add MIPS R6 cache unroll functionsMarkos Chandras1-2/+148
MIPS R6 changed the 'cache' instruction opcode and reduced the offset field to 8 bits. This means we now have to adjust the base register every 256 bytes and as a result of which we can no longer use the previous cache functions. Signed-off-by: Markos Chandras <[email protected]>
2015-02-17MIPS: asm: irqflags: Add MIPS R6 related definitionsMarkos Chandras2-4/+5
Add the MIPS R6 related definitions to the IRQ related macros Signed-off-by: Markos Chandras <[email protected]>
2015-02-17MIPS: asm: hazards: Add MIPSR6 definitionsMarkos Chandras1-4/+5
Add the MIPSR6 related definitions to MIPS hazards Signed-off-by: Markos Chandras <[email protected]>
2015-02-17MIPS: asm: cpu: Add MIPSR6 ISA definitionsLeonid Yegoshin2-6/+20
Add MIPS R6 to the ISA definitions Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2015-02-17MIPS: Use generic checksum functions for MIPS R6Markos Chandras5-0/+14
The following instructions have been removed from MIPS R6 ulw, ulh, swl, lwr, lwl, swr. However, all of them are used in the MIPS specific checksum implementation. As a result of which, we will use the generic checksum on MIPS R6 Signed-off-by: Markos Chandras <[email protected]>
2015-02-17MIPS: asm: asmmacro: Replace "add" instructions with "addu"Markos Chandras1-2/+2
The "add" instruction is actually a macro in binutils and depending on the size of the immediate it can expand to an "addi" instruction. However, the "addi" instruction traps on overflows which is not something we want on address calculation. Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00121.html Cc: Paul Burton <[email protected]> Cc: Maciej W. Rozycki <[email protected]> Cc: <[email protected]> # v3.15+ Signed-off-by: Markos Chandras <[email protected]>
2015-02-17MIPS: asm: asmmacro: Add MIPS R6 support to the simple EI/DI variantsLeonid Yegoshin1-1/+1
EI/DI instructions are available in MIPS R6 so add the needed definitions. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2015-02-17MIPS: asm: stackframe: Do not preserve the HI/LO registers on MIPS R6Leonid Yegoshin1-4/+4
The HI/LO registers have been removed from MIPS R6. Instructions such as MULT and DIV have been replaced with a new pair of instructions for the HI/LO operations for example: MULT -> MUL, MUH DIV -> DIV, MOD So we avoid preserving the pre-R6 HI/LO registers in MIPS R6 Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2015-02-17MIPS: asm: module: define MODULE_PROC_FAMILY for MIPS R6Leonid Yegoshin1-0/+4
Define the MODULE_PROC_FAMILY for the MIPS R6 ISA. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2015-02-17MIPS: asm: compiler: Add new macros to set ISA and arch asm annotationsMarkos Chandras1-0/+13
There are certain places where the code uses .set mips32 or .set mips64 or .set arch=r4000. In preparation of MIPS R6 support, and in order to use as less #ifdefs as possible, we define new macros to set similar annotations for MIPS R6. Signed-off-by: Markos Chandras <[email protected]>
2015-02-17parisc: Remove unused functionRickard Strandqvist1-3/+0
Remove the function smp_send_start() that is not used anywhere. This was partially found by using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist <[email protected]> Signed-off-by: Helge Deller <[email protected]>
2015-02-17parisc: macro whitespace fixesMichael S. Tsirkin1-58/+58
While working on arch/parisc/include/asm/uaccess.h, I noticed that some macros within this header are made harder to read because they violate a coding style rule: space is missing after comma. Fix it up. Signed-off-by: Michael S. Tsirkin <[email protected]> Signed-off-by: Helge Deller <[email protected]>
2015-02-16powerpc: drop _PAGE_FILE and pte_file()-related helpersKirill A. Shutemov11-26/+4
We've replaced remap_file_pages(2) implementation with emulation. Nobody creates non-linear mapping anymore. Signed-off-by: Kirill A. Shutemov <[email protected]> Cc: Benjamin Herrenschmidt <[email protected]> Cc: Paul Mackerras <[email protected]> Cc: Michael Ellerman <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2015-02-16arm: dts: zynq: update isl9305 compatible string to use isil vendor prefixArnaud Ebalard1-1/+1
"isil" and "isl" prefixes are used at various locations inside the kernel to reference Intersil corporation. This patch is part of a series fixing those locations were "isl" is used in compatible strings to use the now expected "isil" prefix instead (NASDAQ symbol for Intersil and most used version). Note: isl9305 is an I2C device so the patch does not in fact currently depend on the introduction of "isil"-based compatible string in isl9305 driver (provided by another patch) because I2C core does not check the prefix yet. Signed-off-by: Arnaud Ebalard <[email protected]> Cc: Rob Herring <[email protected]> Cc: Pawel Moll <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Ian Campbell <[email protected]> Cc: Kumar Gala <[email protected]> Cc: Russell King <[email protected]> Cc: Stephen Warren <[email protected]> Cc: Thierry Reding <[email protected]> Cc: Alexandre Courbot <[email protected]> Cc: Uwe Kleine-Knig <[email protected]> Cc: Alessandro Zummo <[email protected]> Cc: Peter Huewe <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Mark Brown <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: Darshana Padmadas <[email protected]> Cc: Grant Likely <[email protected]> Cc: Rob Landley <[email protected]> Cc: Jason Cooper <[email protected]> Cc: Guenter Roeck <[email protected]> Cc: Jason Gunthorpe <[email protected]> Cc: Uwe Kleine-König <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2015-02-16Merge branch 'timers-core-for-linus' of ↵Linus Torvalds2-0/+6
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull clocksource updates from Ingo Molnar: "The main change in this tree is the addition of various new SoC clocksource/clockevents drivers: Conexant Digicolor SoCs, rockchip rk3288 board, asm9260 for MIPS and versatile AB/PB boards" * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: dts: versatile: Add sysregs node clocksource: versatile: Adapt for Versatile AB and PB boards dt/bindings: Add binding for Versatile system registers clocksource: Driver for Conexant Digicolor SoC timer clocksource: devicetree: Document Conexant Digicolor timer binding clockevents: rockchip: Add rockchip timer for rk3288 ARM: clocksource: Add asm9260_timer driver clocksource: marco: Rename marco to atlas7 clocksource: sirf: Remove unused variable
2015-02-16Merge branch 'perf-core-for-linus' of ↵Linus Torvalds32-116/+231
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 perf updates from Ingo Molnar: "This series tightens up RDPMC permissions: currently even highly sandboxed x86 execution environments (such as seccomp) have permission to execute RDPMC, which may leak various perf events / PMU state such as timing information and other CPU execution details. This 'all is allowed' RDPMC mode is still preserved as the (non-default) /sys/devices/cpu/rdpmc=2 setting. The new default is that RDPMC access is only allowed if a perf event is mmap-ed (which is needed to correctly interpret RDPMC counter values in any case). As a side effect of these changes CR4 handling is cleaned up in the x86 code and a shadow copy of the CR4 value is added. The extra CR4 manipulation adds ~ <50ns to the context switch cost between rdpmc-capable and rdpmc-non-capable mms" * 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/x86: Add /sys/devices/cpu/rdpmc=2 to allow rdpmc for all tasks perf/x86: Only allow rdpmc if a perf_event is mapped perf: Pass the event to arch_perf_update_userpage() perf: Add pmu callbacks to track event mapping and unmapping x86: Add a comment clarifying LDT context switching x86: Store a per-cpu shadow copy of CR4 x86: Clean up cr4 manipulation
2015-02-16Merge tag 'arc-3.20-rc1' of ↵Linus Torvalds7-29/+47
git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC updates from Vineet Gupta: "Some fixes, nothing too exciting this time as well..." * tag 'arc-3.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: fix page address calculation if PAGE_OFFSET != LINUX_LINK_BASE ARC: Fix earlycon build breakage ARC: Dynamically determine BASE_BAUD from DeviceTree arc: Remove unused prepare_to_copy() ARC: use ACCESS_ONCE in cmpxchg loop ARC: add some more comments to ret_from_fork ARC: fix /proc/cpuinfo for offline cpus
2015-02-16Merge branch 'for-next' of ↵Linus Torvalds3-40/+5
git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu Pull m68knommu fixes from Greg Ungerer: "Nothing big, only a small collection of minor cleanups/fixes" * 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: arch: m68k: 68360: config: Remove unused function m68knommu: fix irq handler types in 68360/commproc.c m68k: remove check for CONFIG_BSEIP
2015-02-16parisc/uaccess: fix sparse errorsMichael S. Tsirkin1-1/+1
virtio wants to read bitwise types from userspace using get_user. At the moment this triggers sparse errors, since the value is passed through an integer. Fix that up using __force. Signed-off-by: Michael S. Tsirkin <[email protected]> Acked-by: Helge Deller <[email protected]> Signed-off-by: Helge Deller <[email protected]>
2015-02-16parisc: hpux - Remove HPUX syscall numbersHelge Deller1-478/+0
Signed-off-by: Helge Deller <[email protected]>
2015-02-16parisc: hpux - Remove hpux gateway pageHelge Deller5-108/+4
Drop code to create HP-UX gateway page and syscall entry code. Signed-off-by: Helge Deller <[email protected]>
2015-02-16parisc: hpux - Delete files in hpux subdirectoryHelge Deller7-2135/+0
Signed-off-by: Helge Deller <[email protected]>
2015-02-16parisc: hpux - Do not compile hpux subdirectoryHelge Deller1-1/+0
Signed-off-by: Helge Deller <[email protected]>
2015-02-16parisc: hpux - Drop support for HP-UX binariesHelge Deller1-4/+0
This patch series drops the support for 32bit HP-UX binaries. The HP-UX compat layer has always been incomplete and it's unlikely that someone will ever implement it. Furthermore those two commits which enhance the compatibility of Linux on parisc to other architectures: f5a408d: parisc: Make EWOULDBLOCK be equal to EAGAIN on parisc 1f25df2: parisc: Reduce SIGRTMIN from 37 to 32 to behave like other Linux architectures basically make it impossible to implement the HP-UX support correctly. Signed-off-by: Helge Deller <[email protected]>
2015-02-16parisc: Add error checks when building up signal trampoline handlerHelge Deller1-14/+15
Add checks if the userspace trampoline code was correctly generated by the signal trampoline generation code. In addition only flush caches as needed and fix the old flushing code which didn't flushed all generated instructions. Signed-off-by: Helge Deller <[email protected]>
2015-02-16parisc: Wire up execveat syscallHelge Deller2-1/+3
Signed-off-by: Helge Deller <[email protected]>
2015-02-16ARM: dts: add I2C device nodes for Broadcom CygnusRay Jui1-0/+20
Add I2C device nodes and its properties in bcm-cygnus.dtsi but keep them disabled there. Individual I2C devices can be enabled in board specific dts file when I2C slave devices are enabled in the future Signed-off-by: Ray Jui <[email protected]> Reviewed-by: Scott Branden <[email protected]> Reviewed-by: Kevin Cernekee <[email protected]> Signed-off-by: Florian Fainelli <[email protected]>
2015-02-16ARM: dts: BCM63xx: fix L2 cache propertiesFlorian Fainelli1-2/+3
The L2 cache properties were completely off with respect to what the hardware is configured for. Fix the cache-size, cache-line-size and cache-sets to reflect the L2 cache controller we have: 512KB, 16 ways and 32 bytes per cache-line. Fixes: 46d4bca0445a0 ("ARM: BCM63XX: add BCM63138 minimal Device Tree") Signed-off-by: Florian Fainelli <[email protected]>
2015-02-16MIPS: mm: Add MIPS R6 instruction encodingsLeonid Yegoshin2-3/+38
MIPS R6 defines new opcodes for ll, sc, cache and pref instructions so we need to take these into consideration in the micro-assembler. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2015-02-16nios2: add kgdb supportLey Foon Tan5-1/+277
Signed-off-by: Ley Foon Tan <[email protected]>
2015-02-16MIPS: mm: uasm: Add signed 9-bit immediate related macrosLeonid Yegoshin1-1/+12
MIPS R6 redefines several instructions and reduces the immediate field to 9-bits so add related macros for the microassembler. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2015-02-16MIPS: Add build support for the MIPS R6 ISALeonid Yegoshin2-4/+45
Add build support for the latest revision (R6) of the MIPS ISA. microMIPS is not yet supported. Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00386.html Cc: Maciej W. Rozycki <[email protected]> Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2015-02-16MIPS: Add MIPS generic QEMU probe supportLeonid Yegoshin1-0/+5
Add a case in cpu_probe_mips for the MIPS generic QEMU processor ID. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2015-02-16MIPS: Add cases for CPU_QEMU_GENERICLeonid Yegoshin7-0/+13
Add a CPU_QEMU_GENERIC case to various switch statements. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2015-02-16MIPS: Add generic QEMU PRid and cpu type identifiersLeonid Yegoshin1-0/+3
Latest versions of QEMU added support for mips32r6-generic and mips64r6-generic cpu types so add related definitions in preparation of MIPS R6 support. This is also used for QEMU R2 generic cpus. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2015-02-16MIPS: HTW: Prevent accidental HTW start due to nested htw_{start, stop}Markos Chandras4-8/+32
activate_mm() and switch_mm() call get_new_mmu_context() which in turn can enable the HTW before the entryhi is changed with the new ASID. Since the latter will enable the HTW in local_flush_tlb_all(), then there is a small timing window where the HTW is running with the new ASID but with an old pgd since the TLBMISS_HANDLER_SETUP_PGD hasn't assigned a new one yet. In order to prevent that, we introduce a simple htw counter to avoid starting HTW accidentally due to nested htw_{start,stop}() sequences. Moreover, since various IPI calls can enforce TLB flushing operations on a different core, such an operation may interrupt another htw_{stop,start} in progress leading inconsistent updates of the htw_seq variable. In order to avoid that, we disable the interrupts whenever we update that variable. Signed-off-by: Markos Chandras <[email protected]> Cc: <[email protected]> # 3.17+ Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/9118/ Signed-off-by: Ralf Baechle <[email protected]>
2015-02-16MIPS: Makefile: Move the ASEs checks after setting the core's CFLAGSMarkos Chandras1-18/+17
We need to check the ASEs support against the core's CFLAGS instead of depending to the default -march option from the toolchain. Signed-off-by: Markos Chandras <[email protected]> Cc: Maciej W. Rozycki <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/9180/ Signed-off-by: Ralf Baechle <[email protected]>
2015-02-16MIPS: asm: pgtable: Prevent HTW race when updating PTEsMarkos Chandras1-10/+4
Whenever we modify a page table entry, we need to ensure that the HTW will not fetch a stable entry. And for that to happen we need to ensure that HTW is stopped before we modify the said entry otherwise the HTW may already be in the process of reading that entry and fetching the old information. As a result of which, we replace the htw_reset() calls with htw_{stop,start} in more appropriate places. This also removes the remaining users of htw_reset() and as a result we drop that macro Signed-off-by: Markos Chandras <[email protected]> Cc: <[email protected]> # 3.17+ Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/9116/ Signed-off-by: Ralf Baechle <[email protected]>
2015-02-16MIPS: asm: pgtable: Add c0 hazards on HTW start/stop sequencesMarkos Chandras1-4/+6
When we use htw_{start,stop}() outside of htw_reset(), we need to ensure that c0 changes have been propagated properly before we attempt to continue with subsequence memory operations. Signed-off-by: Markos Chandras <[email protected]> Cc: <[email protected]> # 3.17+ Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/9114/ Signed-off-by: Ralf Baechle <[email protected]>
2015-02-16MIPS: mm: Add debug information for userland SIGSEGV signals.Markos Chandras2-9/+21
Commit 41c594ab65fc ("[MIPS] MT: Improved multithreading support.") removed useful debug information for userland segmentation faults. This patch bring this back along with the ability to determine the name of the object file where the EPC and RA registers point at. Furthermore, we select the SYSCTL_EXCEPTION_TRACE symbol for MIPS which is the de facto solution to turn userland exception logging on and off via the /proc/sys/debug/exception-trace file. Signed-off-by: Markos Chandras <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/9089/ Signed-off-by: Ralf Baechle <[email protected]>
2015-02-15Merge tag 'cris-for-3.20' of ↵Linus Torvalds6-76/+111
git://git.kernel.org/pub/scm/linux/kernel/git/jesper/cris Pull CRIS changes from Jesper Nilsson. * tag 'cris-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jesper/cris: CRIS: Whitespace cleanup CRIS: macro whitespace fixes in uaccess.h CRIS: uaccess: fix sparse errors CRISv32: Remove unnecessary KERN_INFO from sync_serial CRIS: Fix missing NR_CPUS in menuconfig CRISv32: Avoid warning of unused variable CRIS: Avoid warning in cris mm/fault.c CRIS: Export csum_partial_copy_nocheck
2015-02-15Merge branch 'bfin_rotary' into nextDmitry Torokhov230-1020/+1715
Merge bfin_rotary driver changes from Sonic Zhang.
2015-02-15Input: bfin_rotary - use generic IO functionsSonic Zhang4-0/+20
Instead of using arch-specific accessors remap rotary register physical address into kernel space in probe and use standard readw and writew to access rotary MMRs. Signed-off-by: Sonic Zhang <[email protected]> Signed-off-by: Dmitry Torokhov <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.