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2017-08-31powerpc/powernv: Use kernel crash path for machine checksNicholas Piggin5-7/+59
There are quite a few machine check exceptions that can be caused by kernel bugs. To make debugging easier, use the kernel crash path in cases of synchronous machine checks that occur in kernel mode, if that would not result in the machine going straight to panic or crash dump. There is a downside here that die()ing the process in kernel mode can still leave the system unstable. panic_on_oops will always force the system to fail-stop, so systems where that behaviour is important will still do the right thing. As a test, when triggering an i-side 0111b error (ifetch from foreign address) in kernel mode process context on POWER9, the kernel currently dies quickly like this: Severe Machine check interrupt [Not recovered] NIP [ffff000000000000]: 0xffff000000000000 Initiator: CPU Error type: Real address [Instruction fetch (foreign)] [ 127.426651616,0] OPAL: Reboot requested due to Platform error. Effective[ 127.426693712,3] OPAL: Reboot requested due to Platform error. address: ffff000000000000 opal: Reboot type 1 not supported Kernel panic - not syncing: PowerNV Unrecovered Machine Check CPU: 56 PID: 4425 Comm: syscall Tainted: G M 4.12.0-rc1-13857-ga4700a261072-dirty #35 Call Trace: [ 128.017988928,4] IPMI: BUG: Dropping ESEL on the floor due to buggy/mising code in OPAL for this BMC Rebooting in 10 seconds.. Trying to free IRQ 496 from IRQ context! After this patch, the process is killed and the kernel continues with this message, which gives enough information to identify the offending branch (i.e., with CFAR): Severe Machine check interrupt [Not recovered] NIP [ffff000000000000]: 0xffff000000000000 Initiator: CPU Error type: Real address [Instruction fetch (foreign)] Effective address: ffff000000000000 Oops: Machine check, sig: 7 [#1] SMP NR_CPUS=2048 NUMA PowerNV Modules linked in: iptable_mangle ipt_MASQUERADE nf_nat_masquerade_ipv4 ... CPU: 22 PID: 4436 Comm: syscall Tainted: G M 4.12.0-rc1-13857-ga4700a261072-dirty #36 task: c000000932300000 task.stack: c000000932380000 NIP: ffff000000000000 LR: 00000000217706a4 CTR: ffff000000000000 REGS: c00000000fc8fd80 TRAP: 0200 Tainted: G M (4.12.0-rc1-13857-ga4700a261072-dirty) MSR: 90000000001c1003 <SF,HV,ME,RI,LE> CR: 24000484 XER: 20000000 CFAR: c000000000004c80 DAR: 0000000021770a90 DSISR: 0a000000 SOFTE: 1 GPR00: 0000000000001ebe 00007fffce4818b0 0000000021797f00 0000000000000000 GPR04: 00007fff8007ac24 0000000044000484 0000000000004000 00007fff801405e8 GPR08: 900000000280f033 0000000024000484 0000000000000000 0000000000000030 GPR12: 9000000000001003 00007fff801bc370 0000000000000000 0000000000000000 GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 GPR20: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 GPR24: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 GPR28: 00007fff801b0000 0000000000000000 00000000217707a0 00007fffce481918 NIP [ffff000000000000] 0xffff000000000000 LR [00000000217706a4] 0x217706a4 Call Trace: Instruction dump: XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Signed-off-by: Nicholas Piggin <[email protected]> Reviewed-by: Mahesh Salgaonkar <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2017-08-31powerpc/powernv: Flush console before platform error rebootNicholas Piggin4-58/+57
Unrecovered MCE and HMI errors are sent through a special restart OPAL call to log the platform error. The downside is that they don't go through normal Linux crash paths, so they don't give much information to the Linux console. Change this by providing a special crash function which does some of the console flushing from the panic() path before calling firmware to reboot. The downside of this is a little more code to execute before reaching the firmware reboot. However in practice, it's critical to get the Linux console messages output in order to debug a problem. So this is a desirable tradeoff. Note on the implementation: It is difficult to plumb a custom reboot handler into the panic path, because panic does a little bit too much work. For example, it will try to delay with the timebase, but that may be corrupted in some cases resulting in a hang without reaching the platform reboot. Another problem is that panic can invoke the crash dump code which is not what we want in the case of a hardware platform error. Long-term the best solution will be to rework the panic path so it can be suitable for this kind of panic, but for now we just duplicate a bit of the code. Signed-off-by: Nicholas Piggin <[email protected]> Reviewed-by: Mahesh Salgaonkar <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2017-08-31powerpc: Do not send system reset request through the oops pathNicholas Piggin1-16/+31
A system reset is a request to crash / debug the system rather than necessarily caused by encountering a BUG. So there is no need to serialize all CPUs behind the die lock, adding taints to all subsequent traces beyond the first, breaking console locks, etc. The system reset is NMI context which has its own printk buffers to prevent output being interleaved. Then it's better to have all secondaries print out their debug as quickly as possible and the primary will flush out all printk buffers during panic(). So remove the 0x100 path from die, and move it into system_reset. Name the crash/dump reasons "System Reset". This gives "not tained" traces when crashing an untainted kernel. It also gives the panic reason as "System Reset" as opposed to "Fatal exception in interrupt" (or "die oops" for fadump). Signed-off-by: Nicholas Piggin <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2017-08-31powerpc/pseries/le: Work around a firmware quirkNicholas Piggin1-0/+15
Some PowerVM firmware when delivering a system reset interrupt to a little endian OS will mess up SRR registers. They are byteswapped, and SRR1 is incorrect. An example from a crash: NIP: 14dd0900000000c0 MSR: 1000000200000080 It's possible to detect this pattern in SRR1 (that would never happen in normal operation), and at least fix the NIP. After this patch, the same interrupt reports NIP properly: NIP [c00000000009dd14] plpar_hcall_norets+0x1c/0x28 Signed-off-by: Nicholas Piggin <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2017-08-31powerpc: Do not call ppc_md.panic in fadump panic notifierNicholas Piggin6-45/+22
If fadump is not registered, and no other crash or debug handlers are registered, the powerpc panic handler stops the guest before the generic panic code can push out debug information to the console. Currently, system reset injection causes the guest to silently stop. Stop calling ppc_md.panic in the panic notifier. crash_fadump already does rtas_os_term() to terminate the guest if fadump is registered. Remove ppc_md.panic. Move fadump panic notifier into fadump code. Signed-off-by: Nicholas Piggin <[email protected]> Reviewed-by: Mahesh Salgaonkar <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2017-08-31powerpc/64: Fix watchdog configuration regressionsNicholas Piggin3-9/+29
This fixes a couple more bits of fallout from the new hard lockup watchdog patch. It restores the required hw_nmi_get_sample_period() function for the perf watchdog, and removes some function declarations on 64e that are only defined for 64s. This fixes the 64e build when the hardlockup detector is enabled. It restores the default behaviour of disabling the perf watchdog, and also fixes disabling the 64s watchdog when running as a guest. Fixes: 2104180a53 ("powerpc/64s: implement arch-specific hardlockup watchdog") Signed-off-by: Nicholas Piggin <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2017-08-31powerpc/64s/radix: Do not allocate SLB shadow structuresNicholas Piggin1-2/+11
These are unused in radix mode. Signed-off-by: Nicholas Piggin <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2017-08-31powerpc/64s/radix: Remove bolted-SLB address limit for per-cpu stacksNicholas Piggin1-3/+8
Radix MMU does not take SLB or TLB interrupts when accessing kernel linear address. Remove this restriction for radix mode. Signed-off-by: Nicholas Piggin <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2017-08-31powerpc/powernv: powernv platform is not constrained by RMANicholas Piggin1-5/+2
Remove incorrect comment about real mode address restrictions on powernv (bare metal), and unnecessary clamping to ppc64_rma_size. Signed-off-by: Nicholas Piggin <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2017-08-31Merge remote-tracking branch 'remotes/powerpc/topic/ppc-kvm' into kvm-ppc-nextPaul Mackerras17-67/+151
This merges in the 'ppc-kvm' topic branch from the powerpc tree in order to bring in some fixes which touch both powerpc and KVM code. Signed-off-by: Paul Mackerras <[email protected]>
2017-08-31KVM: PPC: Book3S HV: Report storage key support to userspacePaul Mackerras1-0/+8
This adds information about storage keys to the struct returned by the KVM_PPC_GET_SMMU_INFO ioctl. The new fields replace a pad field, which was zeroed by previous kernel versions. Thus userspace that knows about the new fields will see zeroes when running on an older kernel, indicating that storage keys are not supported. The size of the structure has not changed. The number of keys is hard-coded for the CPUs supported by HV KVM, which is just POWER7, POWER8 and POWER9. Signed-off-by: Paul Mackerras <[email protected]> Reviewed-by: David Gibson <[email protected]> Signed-off-by: Paul Mackerras <[email protected]>
2017-08-31KVM: PPC: Book3S HV: Fix case where HDEC is treated as 32-bit on POWER9Paul Mackerras1-1/+2
Commit 2f2724630f7a ("KVM: PPC: Book3S HV: Cope with host using large decrementer mode", 2017-05-22) added code to treat the hypervisor decrementer (HDEC) as a 64-bit value on POWER9 rather than 32-bit. Unfortunately, that commit missed one place where HDEC is treated as a 32-bit value. This fixes it. This bug should not have any user-visible consequences that I can think of, beyond an occasional unnecessary exit to the host kernel. If the hypervisor decrementer has gone negative, then the bottom 32 bits will be negative for about 4 seconds after that, so as long as we get out of the guest within those 4 seconds we won't conclude that the HDEC interrupt is spurious. Reported-by: Suraj Jitindar Singh <[email protected]> Fixes: 2f2724630f7a ("KVM: PPC: Book3S HV: Cope with host using large decrementer mode") Signed-off-by: Paul Mackerras <[email protected]>
2017-08-31KVM: PPC: Book3S HV: Fix invalid use of register expressionAndreas Schwab1-1/+1
binutils >= 2.26 now warns about misuse of register expressions in assembler operands that are actually literals. In this instance r0 is being used where a literal 0 should be used. Signed-off-by: Andreas Schwab <[email protected]> [mpe: Split into separate KVM patch, tweak change log] Signed-off-by: Michael Ellerman <[email protected]> Signed-off-by: Paul Mackerras <[email protected]>
2017-08-31KVM: PPC: Book3S HV: Fix H_REGISTER_VPA VPA size validationNicholas Piggin1-1/+7
KVM currently validates the size of the VPA registered by the client against sizeof(struct lppaca), however we align (and therefore size) that struct to 1kB to avoid crossing a 4kB boundary in the client. PAPR calls for sizes >= 640 bytes to be accepted. Hard code this with a comment. Signed-off-by: Nicholas Piggin <[email protected]> Signed-off-by: Paul Mackerras <[email protected]>
2017-08-31KVM: PPC: Book3S HV: Fix setting of storage key in H_ENTERRam Pai2-1/+2
In handling a H_ENTER hypercall, the code in kvmppc_do_h_enter clobbers the high-order two bits of the storage key, which is stored in a split field in the second doubleword of the HPTE. Any storage key number above 7 hence fails to operate correctly. This makes sure we preserve all the bits of the storage key. Acked-by: Balbir Singh <[email protected]> Signed-off-by: Ram Pai <[email protected]> Signed-off-by: Paul Mackerras <[email protected]>
2017-08-31KVM: PPC: e500mc: Fix a NULL dereferenceDan Carpenter1-1/+3
We should set "err = -ENOMEM;", otherwise it means we're returning ERR_PTR(0) which is NULL. It results in a NULL pointer dereference in the caller. Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Paul Mackerras <[email protected]>
2017-08-31KVM: PPC: e500: Fix some NULL dereferences on errorDan Carpenter1-2/+6
There are some error paths in kvmppc_core_vcpu_create_e500() where we forget to set the error code. It means that we return ERR_PTR(0) which is NULL and it results in a NULL pointer dereference in the caller. Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Paul Mackerras <[email protected]>
2017-08-30Merge branch 'for-linus-4.13-rc7' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/rw/uml Pull UML fix from Richard Weinberger: "This contains a single fix for a regression which was introduced while the merge window" * 'for-linus-4.13-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/uml: um: Fix check for _xstate for older hosts
2017-08-30Merge branch 'for-linus' of ↵Linus Torvalds13-16/+68
git://git.kernel.org/pub/scm/linux/kernel/git/mattst88/alpha Pull alpha update from Matt Turner: "A few fixes and wires up some additional syscalls." [ Some of this is technically not really rc7 material, but it's alpha, and it all looks safe anyway. Matt explains: "My alpha has been offline, hence the very late-in-cycle pull request" and hasn't caused problems before, so he gets to slide. - Linus ] * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mattst88/alpha: alpha: uapi: Add support for __SANE_USERSPACE_TYPES__ alpha: Define ioremap_wc alpha: Fix section mismatches alpha: support R_ALPHA_REFLONG relocations for module loading alpha: Fix typo in ev6-copy_user.S alpha: Package string routines together alpha: Update for new syscalls alpha: Fix build error without CONFIG_VGA_HOSE.
2017-08-30x86/PCI: Use is_vmd() rather than relying on the domain numberJon Derrick1-1/+1
Use the is_vmd() predicate to identify devices below a VMD host rather than relying on the domain number. Signed-off-by: Jon Derrick <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-08-30x86/PCI: Move VMD quirk to x86 fixupsJon Derrick1-0/+17
VMD currently only exists for Intel x86 products, so move the VMD quirk to arch/x86. Signed-off-by: Jon Derrick <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-08-30Merge tag 'sunxi-dt-for-4.14-3' of ↵Olof Johansson3-8/+150
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt Allwinner DT changes for 4.14, take 3 One new board, and a revert of a patch relying on a binding not stable enough so that we can commit to it. * tag 'sunxi-dt-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: Revert "ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Beelink X2" ARM: sun8i: a83t: Add device tree for Sinovoip Bananapi BPI-M3 Signed-off-by: Olof Johansson <[email protected]>
2017-08-30ARM: dts: at91: at91sam9g45: add AC97Dmitry Rezvanov2-0/+25
AT91SAM9G45 has an AC97 controller, but it is not described in the dts file. This patch adds AC97 node in device tree. Signed-off-by: Dmitry Rezvanov <[email protected]> Signed-off-by: Alexandre Belloni <[email protected]>
2017-08-30ARCv2: SLC: provide a line based flush routine for debuggingVineet Gupta2-1/+55
Signed-off-by: Vineet Gupta <[email protected]>
2017-08-30ARC: Hardcode ARCH_DMA_MINALIGN to max line length we may haveAlexey Brodkin1-1/+2
Current implementation relies on L1 line length which might easily be smaller than L2 line (which is usually the case BTW). Imagine this typical case: L2 line is 128 bytes while L1 line is 64-bytes. Now we want to allocate small buffer and later use it for DMA (consider IOC is not available). kmalloc() allocates small KMALLOC_MIN_SIZE-sized, KMALLOC_MIN_SIZE-aligned That way if buffer happens to be aligned to L1 line and not L2 line we'll be flushing and invalidating extra portions of data from L2 which will cause cache coherency issues. And since KMALLOC_MIN_SIZE is bound to ARCH_DMA_MINALIGN the fix could be simple - set ARCH_DMA_MINALIGN to the largest cache line we may ever get. As of today neither L1 of ARC700 and ARC HS38 nor SLC might not be longer than 128 bytes. Signed-off-by: Alexey Brodkin <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2017-08-30arm64: dts: marvell: fix number of GPIOs in Armada AP806 descriptionThomas Petazzoni1-2/+2
The Armada AP806 has 20 pins, and therefore 20 GPIOs (from 0 to 19 included) and not 19 pins. Therefore, we fix the Device Tree description for the GPIO controller. Before this patch: $ cat /sys/kernel/debug/pinctrl/f06f4000.system-controller:pinctrl/gpio-ranges GPIO ranges handled: 0: mvebu-gpio GPIOS [0 - 19] PINS [0 - 19] 0: f06f4000.system-controller:gpio GPIOS [0 - 18] PINS [0 - 18] After this patch: $ cat /sys/kernel/debug/pinctrl/f06f4000.system-controller:pinctrl/gpio-ranges GPIO ranges handled: 0: mvebu-gpio GPIOS [0 - 19] PINS [0 - 19] 0: f06f4000.system-controller:gpio GPIOS [0 - 19] PINS [0 - 19] Fixes: 63dac0f4924b9 ("arm64: dts: marvell: add gpio support for Armada 7K/8K") Signed-off-by: Thomas Petazzoni <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2017-08-30MIPS: GIC: Introduce asm/mips-gic.h with accessor functionsPaul Burton2-0/+294
This patch introduces a new header providing accessor functions for the MIPS Global Interrupt Controller (GIC) mirroring those provided for the other 2 components of the MIPS Coherent Processing System (CPS) - the Coherence Manager (CM) & Cluster Power Controller (CPC). This header makes use of the new standardised CPS accessor macros where possible, but does require some custom accessors for cases where we have either a bit or a register per interrupt. A major advantage of this over the existing include/linux/irqchip/mips-gic.h definitions is that code performing accesses can become much simpler, for example this: gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) + GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr), (unsigned long)trig << GIC_INTR_BIT(intr)); ...can become simply: change_gic_trig(intr, trig); The accessors handle 32 vs 64 bit in the same way as for CM & CPC code, which means that GIC code will also not need to worry about the access size in most cases. They are also accessible outside of drivers/irqchip/irq-mips-gic.c which will allow for simplification in the use of the non-interrupt portions of the GIC (eg. counters) which currently require the interrupt controller driver to expose helper functions for access. This patch doesn't change any existing code over to use the new accessors yet, since a wholesale change would be invasive & difficult to review. Instead follow-on patches will convert code piecemeal to use this new header. The one change to existing code is to rename gic_base to mips_gic_base & make it global, in order to fit in with the naming expected by the standardised CPS accessor macros. Signed-off-by: Paul Burton <[email protected]> Acked-by: Marc Zyngier <[email protected]> Cc: Jason Cooper <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/17020/ Signed-off-by: Ralf Baechle <[email protected]>
2017-08-30arc: remove num-slots from arc platformsShawn Lin2-2/+0
dwmmc driver deprecated num-slots and plan to get rid of it finally. Just move a step to cleanup it from DT. Reviewed-by: Jaehoon Chung <[email protected]> Acked-by: Alexey Brodkin <[email protected]> Acked-by: Vineet Gupta <[email protected]> Signed-off-by: Shawn Lin <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2017-08-30arm64: dts: marvell: mcbin: enable more networking portsAntoine Tenart1-0/+30
This patch enables the two GE/SFP ports. They are configured in 10GKR mode by default. To do this the cpm_xdmio is enabled as well, and two phy descriptions are added. Signed-off-by: Antoine Tenart <[email protected]> Tested-by: Marcin Wojtas <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2017-08-30arm64: dts: marvell: add a reference to the sysctrl syscon in the ppv2 nodeAntoine Tenart2-0/+2
The network driver on Marvell SoC (7k/8k) needs to access some registers in the system controller to configure its ports at runtime. This patch adds a phandle reference to the syscon system controller node in the ppv2 node. Signed-off-by: Antoine Tenart <[email protected]> Tested-by: Marcin Wojtas <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2017-08-30arm64: dts: marvell: add TX interrupts for PPv2.2Thomas Petazzoni2-6/+42
This commit updates the Marvell Armada 7K/8K Device Tree to describe the TX interrupts of the Ethernet controllers, in both the master and slave CP110s. Signed-off-by: Thomas Petazzoni <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2017-08-29Merge tag 'uniphier-dt64-v4.14-2' of ↵Olof Johansson5-2/+468
git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt64 UniPhier ARM64 SoC DT updates for v4.14 (2nd) - add reset controller node of analog amplifier - add AIDET irqchip device nodes - fix size of sdctrl node - support new SoC PXs3 and its reference development board * tag 'uniphier-dt64-v4.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier: arm64: dts: uniphier: add PXs3 SoC support arm64: dts: uniphier: fix size of sdctrl node arm64: dts: uniphier: add AIDET nodes arm64: dts: uniphier: add reset controller node of analog amplifier Signed-off-by: Olof Johansson <[email protected]>
2017-08-29Merge tag 'uniphier-dt-v4.14-2' of ↵Olof Johansson6-2/+52
git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt UniPhier ARM SoC DT updates for v4.14 (2nd) - add AIDET irqchip device nodes - fix size of sdctrl node - add ethernet pinmux nodes * tag 'uniphier-dt-v4.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier: ARM: dts: uniphier: add pinctrl groups of ethernet phy mode ARM: dts: uniphier: fix size of sdctrl nodes ARM: dts: uniphier: add AIDET nodes Signed-off-by: Olof Johansson <[email protected]>
2017-08-29Merge tag 'sunxi-fixes-for-4.13-3' of ↵Olof Johansson18-263/+0
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into fixes Allwinner fixes for 4.13, take 3 This is a revert of the EMAC bindings. The discussion has not settled down yet on a proper representation of the PHY, and therefore we cannot commit to a binding yet * tag 'sunxi-fixes-for-4.13-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm: dts: sunxi: Revert EMAC changes arm64: dts: allwinner: Revert EMAC changes dt-bindings: net: Revert sun8i dwmac binding Signed-off-by: Olof Johansson <[email protected]>
2017-08-29Merge tag 'amlogic-dt64-2' of ↵Olof Johansson14-6/+164
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt64 Amlogic 64-bit DT updates for v4.14, round 2 - clock updates w/dependencies on clock tree - GPIO names updates * tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM64: dts: meson-gxl-libretech-cc: Add GPIO lines names ARM64: dts: meson-gx: Add AO CEC nodes ARM64: dts: meson-gx: update AO clkc to new bindings dt-bindings: clock: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb: Add sd_emmc clk0 clkids clk: meson-gxbb: expose almost every clock in the bindings clk: meson8b: expose every clock in the bindings clk: meson: gxbb: fix protection against undefined clks clk: meson: meson8b: fix protection against undefined clks dt-bindings: clock: meson8b: describe the embedded reset controller Signed-off-by: Olof Johansson <[email protected]>
2017-08-29arm64: defconfig: enable rockchip graphicsHeiko Stuebner1-0/+8
Enable the graphics-related options needed by Rockchip boards. This includes the pwm-backlight which will be needed by the internal displays used on Gru Chrome-devices. Signed-off-by: Heiko Stuebner <[email protected]> Reviewed-by: Mark yao <[email protected]> Signed-off-by: Olof Johansson <[email protected]>
2017-08-29Merge tag 'mvebu-dt64-4.14-3' of git://git.infradead.org/linux-mvebu into ↵Olof Johansson5-0/+388
next/dt64 mvebu dt64 for 4.14 (part 3) Add description for a new family SoC from Marvell: Armada-8KP. * tag 'mvebu-dt64-4.14-3' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: add Device Tree files for Armada-8KP Signed-off-by: Olof Johansson <[email protected]>
2017-08-29Merge tag 'v4.13-next-dts32' of https://github.com/mbgg/linux-mediatek into ↵Olof Johansson8-78/+1206
next/dt - mt7623: add mt7623n and mt7623a plattform - add mt7623 based reference boards - mt7623: add usb3, ethernet, cpufreq, - Add banana-pi board - add mt6323 pmic - mt2701: add larb-id property to smi larb * tag 'v4.13-next-dts32' of https://github.com/mbgg/linux-mediatek: arm: dts: mt7623: cleanup binding file arm: dts: mt7623: Add SD-card and EMMC to bananapi-r2 arm: dts: mediatek: add larbid property for larb arm: dts: mt7623: fix mmc interrupt assignment arm: dts: mt2701: Add usb3 device nodes arm: dts: mt2701: Add ethernet device node arm: dts: mt7623: add clock-frequency to CPU nodes arm: dts: mt7623: add support for Bananapi R2 (BPI-R2) board arm: dts: mt7623: enable the nand device on the mt7623n nand rfb arm: dts: mt7623: enable the usb device on the mt7623n rfb arm: dts: mt7623: cleanup the mt7623n rfb uart nodes arm: dts: mt7623: rename mt7623-evb.dts to arch/arm/boot/dts/mt7623n-rfb.dtsi arm: dts: mt7623: add mt6323.dtsi file dt-bindings: arm: mediatek: add bindings for mediatek MT7623a SoC Platform dt-bindings: arm: mediatek: update for MT7623n SoC and relevant boards arm: dts: mt7623: fixup binding violation missing reset in ethernet node dt-bindings: net: mediatek: update documentation for reset signals Signed-off-by: Olof Johansson <[email protected]>
2017-08-30KVM: PPC: Book3S HV: Protect updates to spapr_tce_tables listPaul Mackerras1-11/+10
Al Viro pointed out that while one thread of a process is executing in kvm_vm_ioctl_create_spapr_tce(), another thread could guess the file descriptor returned by anon_inode_getfd() and close() it before the first thread has added it to the kvm->arch.spapr_tce_tables list. That highlights a more general problem: there is no mutual exclusion between writers to the spapr_tce_tables list, leading to the possibility of the list becoming corrupted, which could cause a host kernel crash. To fix the mutual exclusion problem, we add a mutex_lock/unlock pair around the list_del_rce in kvm_spapr_tce_release(). Also, this moves the call to anon_inode_getfd() inside the region protected by the kvm->lock mutex, after we have done the check for a duplicate LIOBN. This means that if another thread does guess the file descriptor and closes it, its call to kvm_spapr_tce_release() will not do any harm because it will have to wait until the first thread has released kvm->lock. With this, there are no failure points in kvm_vm_ioctl_create_spapr_tce() after the call to anon_inode_getfd(). The other things that the second thread could do with the guessed file descriptor are to mmap it or to pass it as a parameter to a KVM_DEV_VFIO_GROUP_SET_SPAPR_TCE ioctl on a KVM device fd. An mmap call won't cause any harm because kvm_spapr_tce_mmap() and kvm_spapr_tce_fault() don't access the spapr_tce_tables list or the kvmppc_spapr_tce_table.list field, and the fields that they do use have been properly initialized by the time of the anon_inode_getfd() call. The KVM_DEV_VFIO_GROUP_SET_SPAPR_TCE ioctl calls kvm_spapr_tce_attach_iommu_group(), which scans the spapr_tce_tables list looking for the kvmppc_spapr_tce_table struct corresponding to the fd given as the parameter. Either it will find the new entry or it won't; if it doesn't, it just returns an error, and if it does, it will function normally. So, in each case there is no harmful effect. Reviewed-by: David Gibson <[email protected]> Signed-off-by: Paul Mackerras <[email protected]>
2017-08-30MIPS: Don't use dma_cache_sync to implement fd_cacheflushChristoph Hellwig1-2/+2
The floppy drivers doesn't otherwise use the DMA API, so indirecting through it just for cache flushing in MIPS-specific code just call dma_cache_wback_inv directly. Signed-off-by: Christoph Hellwig <[email protected]> Cc: [email protected] Cc: Marek Szyprowski <[email protected]> Cc: Robin Murphy <[email protected]> Cc: Michal Simek <[email protected]> Cc: David Howells <[email protected]> Cc: Guan Xuetao <[email protected]> Cc: Chris Zankel <[email protected]> Cc: Max Filippov <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/17183/ Signed-off-by: Ralf Baechle <[email protected]>
2017-08-30MIPS: generic: Bump default NR_CPUS to 16Paul Burton1-1/+1
In generic_defconfig set CONFIG_NR_CPUS to 16 rather than 2, which is a rather too low limit for many modern day MIPS systems. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/16949/ Signed-off-by: Ralf Baechle <[email protected]>
2017-08-30MIPS: generic: Don't explicitly disable CONFIG_USB_SUPPORTPaul Burton1-1/+0
Leave CONFIG_USB_SUPPORT at its default, allowing board config fragments to make use of USB drivers without needing to override it & trigger warnings from merge_config.sh. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/16948/ Signed-off-by: Ralf Baechle <[email protected]>
2017-08-30MIPS: Make CONFIG_MIPS_MT_SMP default yPaul Burton6-4/+2
On systems that support MT ASE multithreading (ie. VPEs) we are very likely to want to include that support as default. Rather than setting it in various defconfigs, simply make CONFIG_MIPS_MT_SMP default y such that systems which select CONFIG_SYS_SUPPORTS_MULTITHREADING get it by default. As well as allowing us to remove the selection of CONFIG_MIPS_MT_SMP from various defconfigs, this also allows the generated generic defconfigs which derive from generic_defconfig to automatically gain support for MT ASE SMP when building for a suitable (pre-MIPSr6) ISA. For malta_kvm_guest_defconfig CONFIG_MIPS_MT_SMP is explicitly disabled since enabling SMP implicitly disables CONFIG_KVM_GUEST, which depends on CONFIG_BROKEN_ON_SMP. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/16947/ Signed-off-by: Ralf Baechle <[email protected]>
2017-08-30MIPS: Prevent direct use of generic_defconfigPaul Burton1-0/+13
Using generic_defconfig directly is unlikely to be what a user actually wants to do - it doesn't specify any particular ISA revision & it doesn't enable any board or driver support, resulting in a largely useless kernel. Prevent users from using it directly, printing a helpful message to point them in the right direction if they attempt to. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/16946/ Signed-off-by: Ralf Baechle <[email protected]>
2017-08-30MIPS: NI 169445: Only include in 32r2el kernelsPaul Burton1-0/+3
The NI 169445 board uses a little endian MIPS32r2 CPU, and therefore including board support in kernels that are unable to run on such a CPU is pointless. Specify requirements in the board config fragment that cause the NI 169445 board support to only be included in generic kernels that target little endian MIPS32r2 CPUs. For example, NI 169445 support will be included when configuring using 32r2el_defconfig but not when using 64r6_defconfig. Signed-off-by: Paul Burton <[email protected]> Acked-by: Nathan Sullivan <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/16945/ Signed-off-by: Ralf Baechle <[email protected]>
2017-08-30MIPS: SEAD-3: Only include in 32 bit kernels by defaultPaul Burton1-0/+2
The MIPS SEAD-3 development board has only ever been used with 32 bit CPUs, so including support for it in 64 bit kernels is wasteful since those kernels will never run on a SEAD-3. Specify a requirement in the SEAD-3 board config fragment that ensures the board support is only included in 32 bit kernels, by checking that CONFIG_32BIT=y. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/16944/ Signed-off-by: Ralf Baechle <[email protected]>
2017-08-30MIPS: generic: Allow filtering enabled boards by requirementsPaul Burton2-2/+98
Up until now when configuring a generic kernel all board config fragments have been merged by default unless boards are explicitly selected by the user specifying BOARDS=. In many cases this is sub-optimal, since some boards don't make sense to include in some kernels. For example the MIPS SEAD-3 development board has only ever been used with 32 bit CPUs, so including support for the SEAD-3 in a 64 bit kernel is wasteful. This patch introduces support for specifying requirements in board config fragments, using comments formatted like so: # require CONFIG_BLA=y For example the SEAD-3 board could specify that it should only be merged for 32 bit kernels using a requirement line like the following: # require CONFIG_32BIT=y A new generic-board-config.sh script is introduced to handle selecting the board config fragments to merge & calling merge_config.sh to merge them. In order to allow requirements to check Kconfig symbols that are implicitly selected, rather than explicitly specified by generic_defconfig or one of the ISA config fragments, an intermediate .config file is saved & used as a reference when checking requirements. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/16943/ Signed-off-by: Ralf Baechle <[email protected]>
2017-08-30MIPS: CPS: Detect CPUs in secondary clustersPaul Burton1-29/+51
As a first step towards supporting multi-cluster systems, detect cores & VPs in secondary clusters & record their cluster information in the cpu_data array. The "VP topology" line printed during boot is extended to display multiple clusters. On a single cluster it shows output like the following: VP topology: {4,4} This would indicate a system with 2 cores which each contain 4 VPs. We extend this to cover multiple clusters in a natural way: VP topology: {4,4},{2,2} This would indicate a system with 2 clusters. The first cluster contains 2 cores which each contain 4 VPs. The second cluster contains 2 cores which each contain 2 VPs. Actually booting these cores & VPs is left to further patches once other pieces are in place. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/17017/ Signed-off-by: Ralf Baechle <[email protected]>
2017-08-30MIPS: CPS: Cluster support for topology functionsPaul Burton7-48/+136
Modify the functions we use to read information about the topology of the system (the number of cores, VPs & IOCUs that it contains) in order to take into account multiple clusters, and provide a new function to determine the number of clusters in the system. Users of these functions are modified only such that they continue to build successfully - having them actually handle multiple clusters is left to further patches. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/17016/ Patchwork: https://patchwork.linux-mips.org/patch/17218/ Signed-off-by: Ralf Baechle <[email protected]>
2017-08-30MIPS: CPS: Have asm/mips-cps.h include CM & CPC headersPaul Burton19-29/+27
With Coherence Manager (CM) 3.5 information about the topology of the system, which has previously only been available through & accessed from the CM, is now also provided by the Cluster Power Controller (CPC). This includes a new CPC_CONFIG register mirroring GCR_CONFIG, and similarly a new CPC_Cx_CONFIG register mirroring GCR_Cx_CONFIG. In preparation for adjusting functions such as mips_cm_numcores(), which have previously only needed to access the CM, to also access the CPC this patch modifies the way we use the various CPS headers. Rather than having users include asm/mips-cm.h or asm/mips-cpc.h individually we instead have users include asm/mips-cps.h which in turn includes asm/mips-cm.h & asm/mips-cpc.h. This means that users will gain access to both CM & CPC registers by including one header, and most importantly it makes asm/mips-cps.h an ideal location for helper functions which need to access the various components of the CPS. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/17015/ Patchwork: https://patchwork.linux-mips.org/patch/17217/ Signed-off-by: Ralf Baechle <[email protected]>
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