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This patch fixes bug on eint type set function, s5p_irq_eint_set_type().
In the IRQ_TYPE_EDGE_FALLING case, S5P_EXTINT_FALLEDGE is right
instead of S5P_EXTINT_RISEEDGE
Signed-off-by: Boojin Kim <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
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* master.kernel.org:/home/rmk/linux-2.6-arm:
ARM: 6205/1: perf: ensure counter delta is treated as unsigned
ARM: 6202/1: Do not ARM_DMA_MEM_BUFFERABLE on RealView boards with L210/L220
ARM: 6201/1: RealView: Do not use outer_sync() on ARM11MPCore boards with L220
ARM: 6195/1: OMAP3: pmu: make CPU_HAS_PMU dependent on OMAP3_EMU
ARM: 6194/1: change definition of cpu_relax() for ARM11MPCore
ARM: 6193/1: RealView: Align the machine_desc.phys_io to 1MB section
ARM: 6192/1: VExpress: Align the machine_desc.phys_io to 1MB section
ARM: 6188/1: Add a config option for the ARM11MPCore DMA cache maintenance workaround
ARM: 6187/1: The v6_dma_inv_range() function must preserve data on SMP
ARM: 6186/1: Avoid the CONSISTENT_DMA_SIZE warning on noMMU builds
ARM: mx3: mx31lilly: fix build error for !CONFIG_USB_ULPI
[ARM] mmp: fix build failure due to IRQ_PMU depends on ARCH_PXA
[ARM] pxa/mioa701: fix camera regression
[ARM] pxa/z2: fix flash layout to final version
[ARM] pxa/z2: fix missing include in battery driver
[ARM] pxa: fix incorrect gpio type in udc_pxa2xx.h
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
perf, x86: Fix incorrect branches event on AMD CPUs
perf tools: Fix find tids routine by excluding "." and ".."
x86: Send a SIGTRAP for user icebp traps
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Hardware performance counters on ARM are 32-bits wide but atomic64_t
variables are used to represent counter data in the hw_perf_event structure.
The armpmu_event_update function right-shifts a signed 64-bit delta variable
and adds the result to the event count. This can lead to shifting in sign-bits
if the MSB of the 32-bit counter value is set. This results in perf output
such as:
Performance counter stats for 'sleep 20':
18446744073460670464 cycles <-- 0xFFFFFFFFF12A6000
7783773 instructions # 0.000 IPC
465 context-switches
161 page-faults
1172393 branches
20.154242147 seconds time elapsed
This patch ensures that the delta value is treated as unsigned so that the
right shift sets the upper bits to zero.
Cc: <[email protected]>
Acked-by: Jamie Iles <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
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While doing some performance counter validation tests on some
assembly language programs I noticed that the "branches:u"
count was very wrong on AMD machines.
It looks like the wrong event was selected.
Signed-off-by: Vince Weaver <[email protected]>
Acked-by: Peter Zijlstra <[email protected]>
Cc: Paul Mackerras <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Robert Richter <[email protected]>
Cc: Borislav Petkov <[email protected]>
Cc: Frederic Weisbecker <[email protected]>
Cc: <[email protected]>
LKML-Reference: <[email protected]>
Signed-off-by: Ingo Molnar <[email protected]>
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RealView boards with certain revisions of the L210/L220 cache controller
may have issues (hardware deadlock) with the mandatory barriers (DSB
followed by an L2 cache sync) when ARM_DMA_MEM_BUFFERABLE is enabled.
The patch disables ARM_DMA_MEM_BUFFERABLE for these boards.
Tested-by: Linus Walleij <[email protected]>
Signed-off-by: Catalin Marinas <[email protected]>
Signed-off-by: Russell King <[email protected]>
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RealView boards with certain revisions of the L220 cache controller (ARM11*
processors only) may have issues (hardware deadlock) with the recent changes to
the mb() barrier implementation (DSB followed by an L2 cache sync). The patch
redefines the RealView ARM11MPCore mandatory barriers without the outer_sync()
call.
Cc: <[email protected]>
Tested-by: Linus Walleij <[email protected]>
Signed-off-by: Catalin Marinas <[email protected]>
Signed-off-by: Russell King <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6:
[IA64] Fix spinaphore down_spin()
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git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
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CPU performance event counters on v7 cores will only operate
if either the NIDEN or DBGEN signals are driven high.
For the OMAP3 platform, these signals are driven low by default
but DBGEN can be asserted by selecting the OMAP3_EMU Kconfig option,
which enables the virtual clock for hardware debugging peripherals.
Acked-by: Jean Pihet <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Linux expects that if a CPU modifies a memory location, then that
modification will eventually become visible to other CPUs in the system.
On an ARM11MPCore processor, loads are prioritised over stores so it is
possible for a store operation to be postponed if a polling loop immediately
follows it. If the variable being polled indirectly depends on the outstanding
store [for example, another CPU may be polling the variable that is pending
modification] then there is the potential for deadlock if interrupts are
disabled. This deadlock occurs in the KGDB testsuire when executing on an
SMP ARM11MPCore configuration.
This patch changes the definition of cpu_relax() to smp_mb() for ARMv6 cores,
forcing a flushing of the write buffer on SMP systems before the next load
takes place. If the Kernel is not compiled for SMP support, this will expand
to a barrier() as before.
Acked-by: Catalin Marinas <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
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When not aligned, random bits could be written in the initial page table
by the __create_page_tables() function.
Signed-off-by: Catalin Marinas <[email protected]>
Signed-off-by: Russell King <[email protected]>
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When not aligned, random bits could be written in the initial page table
by the __create_page_tables() function.
Signed-off-by: Catalin Marinas <[email protected]>
Signed-off-by: Russell King <[email protected]>
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workaround
Commit f4d6477f introduced a workaround for the lack of hardware
broadcasting of the cache maintenance operations on ARM11MPCore.
However, the workaround is only valid on CPUs that do not do speculative
loads into the D-cache.
This patch adds a Kconfig option with the corresponding help to make the
above clear. When the DMA_CACHE_RWFO option is disabled, the kernel
behaviour is that prior to the f4d6477f commit. This also allows ARMv6
UP processors with speculative loads to work correctly.
For other processors, a different workaround may be needed.
Cc: Ronen Shitrit <[email protected]>
Signed-off-by: Catalin Marinas <[email protected]>
Signed-off-by: Russell King <[email protected]>
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A recent patch for DMA cache maintenance on ARM11MPCore added a write
for ownership trick to the v6_dma_inv_range() function. Such operation
destroys data already present in the buffer. However, this function is
used with with dma_sync_single_for_device() which is supposed to
preserve the existing data transfered into the buffer. This patch adds a
combination of read/write for ownership to preserve the original data.
Reported-by: Ronen Shitrit <[email protected]>
Signed-off-by: Catalin Marinas <[email protected]>
Signed-off-by: Russell King <[email protected]>
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This macro is not defined when !CONFIG_MMU so this patch moves the
CONSISTENT_* definitions to the CONFIG_MMU section.
Signed-off-by: Catalin Marinas <[email protected]>
Signed-off-by: Russell King <[email protected]>
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arch/arm/mach-mx3/built-in.o: In function `mx31lilly_board_init':
mach-kzm_arm11_01.c:(.init.text+0x674): undefined reference to `otg_ulpi_create'
mach-kzm_arm11_01.c:(.init.text+0x68c): undefined reference to `otg_ulpi_create'
mach-kzm_arm11_01.c:(.init.text+0x744): undefined reference to `mxc_ulpi_access_ops'
make: *** [.tmp_vmlinux1] Error 1
Signed-off-by: Daniel Mack <[email protected]>
Signed-off-by: Sascha Hauer <[email protected]>
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The x3950 family can have as many as 256 PCI buses in a single system, so
change the limits to the maximum. Since there can only be 256 PCI buses in one
domain, we no longer need the BUG_ON check.
Signed-off-by: Darrick J. Wong <[email protected]>
LKML-Reference: <[email protected]>
Signed-off-by: H. Peter Anvin <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6:
OMAP: hwmod: Fix the missing braces
OMAP4: clock: Fix multi-omap boot with reset un-used clocks
OMAP3: PM: fix IO daisy chain enable to use PM_WKEN reg
omap: GPIO: fix auto-disable of debounce clock
omap: DMTIMER: Ack pending interrupt always when stopping a timer
omap: Stalker board: switch over to gpio_set_debounce
omap: fix build failure due to missing include dma-mapping.h
omap iommu: Fix Memory leak
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Typo in down_spin() meant it only read the low 32 bits of the
"serve" value, instead of the full 64 bits. This results in the
system hanging when the values in ticket/serve get larger than
32-bits. A big enough system running the right test can hit this
in a just a few hours.
Broken since 883a3acf5b0d4782ac35981227a0d094e8b44850
[IA64] Re-implement spinaphores using ticket lock concepts
Reported via IRC by Bjorn Helgaas
Signed-off-by: Tony Luck <[email protected]>
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Before we had a generic breakpoint layer, x86 used to send a
sigtrap for any debug event that happened in userspace,
except if it was caused by lazy dr7 switches.
Currently we only send such signal for single step or breakpoint
events.
However, there are three other kind of debug exceptions:
- debug register access detected: trigger an exception if the
next instruction touches the debug registers. We don't use
it.
- task switch, but we don't use tss.
- icebp/int01 trap. This instruction (0xf1) is undocumented and
generates an int 1 exception. Unlike single step through TF
flag, it doesn't set the single step origin of the exception
in dr6.
icebp then used to be reported in userspace using trap signals
but this have been incidentally broken with the new breakpoint
code. Reenable this. Since this is the only debug event that
doesn't set anything in dr6, this is all we have to check.
This fixes a regression in Wine where World Of Warcraft got broken
as it uses this for software protection checks purposes. And
probably other apps do.
Reported-and-tested-by: Alexandre Julliard <[email protected]>
Signed-off-by: Frederic Weisbecker <[email protected]>
Cc: Ingo Molnar <[email protected]>
Cc: H. Peter Anvin <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Prasad <[email protected]>
Cc: 2.6.33.x 2.6.34.x <[email protected]>
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The os-linux/mem.c file calls fchmod function, which is declared in sys/stat.h
header file, so include it. Fixes build breakage under FC13.
Signed-off-by: Liu Aleaxander <[email protected]>
Acked-by: Boaz Harrosh <[email protected]>
Cc: Jeff Dike <[email protected]>
Cc: <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
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Let's use the standard L1_CACHE_ALIGN macro instead.
Signed-off-by: FUJITA Tomonori <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
tracing: Fix undeclared ENOSYS in include/linux/tracepoint.h
perf record: prevent kill(0, SIGTERM);
perf session: Remove threads from tree on PERF_RECORD_EXIT
perf/tracing: Fix regression of perf losing kprobe events
perf_events: Fix Intel Westmere event constraints
perf record: Don't call newt functions when not initialized
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
x86, Calgary: Increase max PHB number
x86: Fix rebooting on Dell Precision WorkStation T7400
x86: Fix vsyscall on gcc 4.5 with -Os
x86, pat: Proper init of memtype subtree_max_end
um, hweight: Fix UML boot crash due to x86 optimized hweight
x86, setup: Set ax register in boot vga query
percpu, x86: Avoid warnings of unused variables in per cpu
x86, irq: Rename gsi_end gsi_top, and fix off by one errors
x86: use __ASSEMBLY__ rather than __ASSEMBLER__
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omap-fixes-for-linus
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Implicit slab.h inclusion via percpu.h is about to go away. Make sure
gfp.h or slab.h is included as necessary.
Signed-off-by: Tejun Heo <[email protected]>
Cc: Stephen Rothwell <[email protected]>
Cc: Russell King <[email protected]>
Signed-off-by: Stephen Rothwell <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* 'sh/for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6:
clocksource: sh_cmt: Fix up bogus shift value.
arch/sh/mm: Eliminate a double lock
sh: Fix up IORESOURCE_PCI_FIXED usage in pcibios_fixup_device_resources().
sh: remove duplicated #include
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* 'merge' of git://git.secretlab.ca/git/linux-2.6:
powerpc/5200: fix lite5200 ethernet phy address
powerpc/5200: Fix build error in sound code.
powerpc/5200: fix oops during going to standby
powerpc/5200: add lite5200 onboard I2C eeprom and flash
maintainers: Add git trees for SPI and device tree
of: Drop properties with "/" in their name
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git://git.kernel.org/pub/scm/linux/kernel/git/mattst88/alpha-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mattst88/alpha-2.6:
alpha: Fix de2104x driver failing to readout MAC address correctly
alpha: Detect Super IO chip, no IDE on Avanti, enable EPP19
alpha: fix pci_mmap_resource API breakage
alpha: fix __arch_hweight32 typo
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git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:
powerpc: Fix mpic_resume on early G5 macs
powerpc: rtas_flash needs to use rtas_data_buf
powerpc: Unconditionally enabled irq stacks
powerpc/kexec: Wait for online/possible CPUs only.
powerpc: Disable CONFIG_SYSFS_DEPRECATED
powerpc/boot: Remove addRamdisk.c since it is now unused
powerpc: Move kdump default base address to 64MB on 64bit
powerpc: Remove dead CONFIG_HIGHPTE
powerpc/fsl-booke: Move loadcam_entry back to asm code to fix SMP ftrace
powerpc/fsl-booke: Fix InstructionTLBError execute permission check
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Signed-off-by: Dongdong Deng <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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Newer systems (x3950M2) can have 48 PHBs per chassis and 8
chassis, so bump the limits up and provide an explanation
of the requirements for each class.
Signed-off-by: Darrick J. Wong <[email protected]>
Acked-by: Muli Ben-Yehuda <[email protected]>
Cc: Corinna Schultz <[email protected]>
Cc: <[email protected]>
LKML-Reference: <[email protected]>
[ v2: Fixed build bug, added back PHBS_PER_CALGARY == 4 ]
Signed-off-by: Ingo Molnar <[email protected]>
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As reported by Sergei, a couple of braces were missing after
the WARN removal patch.
[07/22] OMAP: hwmod: Replace WARN by pr_warning if clock lookup failed
https://patchwork.kernel.org/patch/100756/
Signed-off-by: Benoit Cousson <[email protected]>
[[email protected]: fixed patch description per Anand's E-mail]
Signed-off-by: Paul Walmsley <[email protected]>
Cc: Sergei Shtylyov <[email protected]>
Cc: Anand Gadiyar <[email protected]>
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Need to mask out the existing event bits before OR'ing in
the new ones.
Noticed by Peter Zijlstra.
Signed-off-by: David S. Miller <[email protected]>
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The function begins and ends with a read_lock. The latter is changed to a
read_unlock.
A simplified version of the semantic match that finds this problem is as
follows: (http://coccinelle.lip6.fr/)
// <smpl>
@locked@
expression E1;
position p;
@@
read_lock(E1@p,...);
@r exists@
expression x <= locked.E1;
expression locked.E1;
expression E2;
identifier lock;
position locked.p,p1,p2;
@@
*lock@p1 (E1@p,...);
... when != E1
when != \(x = E2\|&x\)
*lock@p2 (E1,...);
// </smpl>
Signed-off-by: Julia Lawall <[email protected]>
Acked-by: Matt Fleming <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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Dell Precision WorkStation T7400 freezes on reboot unless
reboot=b is used.
Reference: https://qa.mandriva.com/show_bug.cgi?id=58017
Signed-off-by: Thomas Backlund <[email protected]>
LKML-Reference: <[email protected]>
Signed-off-by: Ingo Molnar <[email protected]>
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This fixes the -Os breaks with gcc 4.5 bug. rdtsc_barrier needs to be
force inlined, otherwise user space will jump into kernel space and
kill init.
This also addresses http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44129
I believe.
Signed-off-by: Andi Kleen <[email protected]>
LKML-Reference: <[email protected]>
Signed-off-by: H. Peter Anvin <[email protected]>
Cc: <[email protected]>
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This patch uses "ENABLE_ON_INIT" flag on the emif clock nodes
to avoid the emif clk getting cut as part of reset un-used clock
routine which prevents boot.
Since "omap4xxx_clk_init()" calls "clk_enable_init_clocks()"
which increases the usecount on all ENABLE_ON_INIT clocks, it
prevents "omap2_clk_disable_unused()" from disabling the clock.
The real fix is to have driver for EMIF and do clock get/enable
as part of it. The EMIF driver is planned to be done HWMOD way
so till that available to keep omap3_defconfig booting on OMAP4430,
this patch is necessary.
(Will updated the auto-gen script for 44xx accordingly)
The fix was suggested by Paul Walmsley
Signed-off-by: Santosh Shilimkar <[email protected]>
Tested-by: Nishanth Menon <[email protected]>
Acked-by: Paul Walmsley <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
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According to my schematics, on Lite5200 board ethernet phy uses address
0 (all ADDR lines are pulled down). With this change I can talk to
onboard phy (LXT971) and correctly use autonegotiation.
Signed-off-by: Dmitry Eremin-Solenikov <[email protected]>
Signed-off-by: Grant Likely <[email protected]>
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When going to standby mode mpc code maps the whole soc5200 node
to access warious MBAR registers. However as of_iomap uses 'reg'
property of device node, only small part of MBAR is getting mapped.
Thus pm code gets oops when trying to access high parts of MBAR.
As a way to overcome this, make mpc52xx_pm_prepare() explicitly
map whole MBAR (0xc0000).
Signed-off-by: Dmitry Eremin-Solenikov <[email protected]>
Signed-off-by: Grant Likely <[email protected]>
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This patch probes for the Super IO chip and reserves the IO range when
found. It avoids enabling the IDE interface on the Avanti family, since
none has IDE. It enables the Enhanced Parallel Port v1.9 feature.
Signed-off-by: Morten H. Larsen <[email protected]>
Signed-off-by: Matt Turner <[email protected]>
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Caused by 2c3c8bea608866d8bd9dcf92657d57fdcac011c5 which was clearly not
even compile tested.
Signed-off-by: Matt Turner <[email protected]>
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Typo in 1527bc8b928dd1399c3d3467dd47d9ede210978a renamed hweight32 to
__arch_weight32.
Signed-off-by: Matt Turner <[email protected]>
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Add dts descriptions for onboard 256 byte I2C eeprom (pcf8582C-2)
and 16MB NOR flash (am29lv652d).
Signed-off-by: Dmitry Eremin-Solenikov <[email protected]>
[[email protected]: added lite5200b eeprom and declared lite5200 gpios]
Signed-off-by: Grant Likely <[email protected]>
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mpic_resume() on G5 macs blindly dereferences mpic->fixups, but
it may legitimately be NULL (as on PowerMac7,2). Add an explicit
check.
This fixes suspend-to-disk with one processor (maxcpus=1) for me.
Signed-off-by: Alastair Bridgewater <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
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When trying to flash a machine via the update_flash command, Anton received the
following error:
Restarting system.
FLASH: kernel bug...flash list header addr above 4GB
The code in question has a comment that the flash list should be in
the kernel data and therefore under 4GB:
/* NOTE: the "first" block list is a global var with no data
* blocks in the kernel data segment. We do this because
* we want to ensure this block_list addr is under 4GB.
*/
Unfortunately the Kconfig option is marked tristate which means the variable
may not be in the kernel data and could be above 4GB.
Instead of relying on the data segment being below 4GB, use the static
data buffer allocated by the kernel for use by rtas. Since we don't
use the header struct directly anymore, convert it to a simple pointer.
Reported-By: Anton Blanchard <[email protected]>
Signed-Off-By: Milton Miller <[email protected]
Tested-By: Anton Blanchard <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
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Irq stacks provide an essential protection from stack overflows through
external interrupts, at the cost of two additionals stacks per CPU.
Enable them unconditionally to simplify the kernel build and prevent
people from accidentally disabling them.
Signed-off-by: Christoph Hellwig <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
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