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2011-03-15ARM: EXYNOS4: Add keypad device helpersNaveen Krishna Ch3-0/+41
This patch adds the samsung_keypad_cfg_gpio() for EXYNOS4. Now, this helpers are only for keypad operating in PORT-0. Signed-off-by: Naveen Krishna Ch <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2011-03-15m68knommu: external interrupt support to ColdFire intc-simr controllerGreg Ungerer2-4/+113
The EDGE Port module of some ColdFire parts using the intc-simr interrupt controller provides support for 7 external interrupts. These interrupts go off-chip (that is they are not for internal peripherals). They need some special handling and have some extra setup registers. Add code to support them. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: external interrupt support to ColdFire intc-2 controllerGreg Ungerer4-4/+97
The EDGE Port module of some ColdFire parts using the intc-2 interrupt controller provides support for 7 external interrupts. These interrupts go off-chip (that is they are not for internal peripherals). They need some special handling and have some extra setup registers. Add code to support them. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: remove ColdFire CLOCK_DIV config optionGreg Ungerer13-16/+15
The reality is that you do not need the abiltity to configure the clock divider for ColdFire CPUs. It is a fixed ratio on any given ColdFire family member. It is not the same for all ColdFire parts, but it is always the same in a model range. So hard define the divider for each supported ColdFire CPU type and remove the Kconfig option. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: fix gpio warnings for ColdFire 5407 targetsGreg Ungerer1-3/+3
Fix these compiler warnings: arch/m68knommu/platform/5407/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5407/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5407/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: fix gpio warnings for ColdFire 532x targetsGreg Ungerer1-83/+83
Fix these compiler warnings: arch/m68knommu/platform/532x/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/532x/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/532x/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/532x/gpio.c:51:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/532x/gpio.c:52:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/532x/gpio.c:53:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/532x/gpio.c:54:3: warning: initialisation makes pointer from integer without a cast ... Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: fix gpio warnings for ColdFire 5307 targetsGreg Ungerer1-3/+3
Fix these compiler warnings: arch/m68knommu/platform/5307/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5307/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5307/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: fix gpio warnings for ColdFire 527x targetsGreg Ungerer1-156/+156
Fix these compiler warnings: arch/m68knommu/platform/527x/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/527x/gpio.c:38:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/527x/gpio.c:39:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/527x/gpio.c:53:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/527x/gpio.c:54:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/527x/gpio.c:55:3: warning: initialisation makes pointer from integer without a cast ... Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: fix gpio warnings for ColdFire 5272 targetsGreg Ungerer1-9/+9
Fix these compiler warnings: arch/m68knommu/platform/5272/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5272/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5272/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5272/gpio.c:51:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5272/gpio.c:52:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5272/gpio.c:53:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5272/gpio.c:67:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5272/gpio.c:68:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5272/gpio.c:69:3: warning: initialisation makes pointer from integer without a cast Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: fix gpio warnings for ColdFire 5249 targetsGreg Ungerer1-6/+6
Fix these compiler warnings: arch/m68knommu/platform/5249/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5249/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5249/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5249/gpio.c:51:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5249/gpio.c:52:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5249/gpio.c:53:3: warning: initialisation makes pointer from integer without a cast Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: fix gpio warnings for ColdFire 523x targetsGreg Ungerer1-68/+68
Fix these compiler warnings: arch/m68knommu/platform/523x/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/523x/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/523x/gpio.c:38:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/523x/gpio.c:52:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/523x/gpio.c:53:3: warning: initialisation makes pointer from integer without a cast ... Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: fix gpio warnings for ColdFire 520x targetsGreg Ungerer1-48/+48
Fix these compiler warnings: rch/m68knommu/platform/520x/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/520x/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/520x/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/520x/gpio.c:51:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/520x/gpio.c:52:3: warning: initialisation makes pointer from integer without a cast ... Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: fix gpio warnings for ColdFire 5206e targetsGreg Ungerer1-3/+3
Fix these compiler warnings: arch/m68knommu/platform/5206e/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast CC kernel/panic.o arch/m68knommu/platform/5206e/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5206e/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: fix gpio warnings for ColdFire 5206 targetsGreg Ungerer1-3/+3
Fix these compiler warnings: arch/m68knommu/platform/5206/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5206/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5206/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: fixing compiler warningsAlexander Kurz1-105/+105
Signed-off-by: Alexander Kurz <[email protected]> Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: limit interrupts supported by ColdFire intc-simr driverGreg Ungerer1-23/+24
The intc-simr interrupt controller on some ColdFire CPUs has a set range of interrupts its supports (64 through 128 or 192 depending on model). We shouldn't be setting this handler for every possible interrupt from 0 to 255. Set more appropriate limits, and this means we can drop the interrupt number check in the mask and unmask routines. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: move some init code out of unmask routine for ColdFire intc-2Greg Ungerer1-15/+32
Use a proper irq_startup() routine to intialize the interrupt priority and level register in the ColdFire intc-2 controller code. We shouldn't be checking if the priority/level has been set on every unmask operation. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: limit interrupts supported by ColdFire intc-2 driverGreg Ungerer1-33/+25
The intc-2 interrupt controller on some ColdFire CPUs has a set range of interrupts its supports (64 through 128 or 192 depending on model). We shouldn't be setting this handler for every possible interrupt from 0 to 255. Set more appropriate limits, and this means we can drop the interrupt number check in the mask and unmask routines. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: add basic support for the ColdFire based FireBee boardGreg Ungerer3-0/+93
The FireBee is a ColdFire 5475 based board. Add a configuration option to support it, and the basic platform flash layout code. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: make ColdFire internal peripheral region configurableGreg Ungerer2-6/+49
Most ColdFire CPUs have an internal peripheral set that can be mapped at a user selectable address. Different ColdFire parts either use an MBAR register of an IPSBAR register to map the peripheral region. Most boards use the Freescale default mappings - but not all. Make the setting of the MBAR or IPSBAR register configurable. And only make the selection available on the appropriate ColdFire CPU types. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: clean up definitions of ColdFire peripheral base registersGreg Ungerer1-6/+11
Different ColdFire CPUs have different ways of defining where their internal peripheral registers sit in their address space. Some use an MBAR register, some use and IPSBAR register, some have a fixed mapping. Now that most of the peripheral address definitions have been cleaned up we can clean up the setting of the MBAR and IPSBAR defines to limit them to just where they are needed (and where they actually exist). Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: clean up use of MBAR for DRAM registers on ColdFire startGreg Ungerer8-49/+49
In some of the RAM size autodetection code on ColdFire CPU startup we reference DRAM registers relative to the MBAR register. Not all of the supported ColdFire CPUs have an MBAR, and currently this works because we fake an MBAR address on those registers. In an effort to clean this up, and eventually remove the fake MBAR setting make the DRAM register address definitions actually contain the MBAR (or IPSBAR as appropriate) value as required. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: remove use of MBAR in old-style ColdFire timerGreg Ungerer8-26/+37
Not all ColdFire CPUs that use the old style timer hardware module use an MBAR set peripheral region. Move the TIMER base address defines to the per-CPU header files where we can set it correctly based on how the peripherals are mapped - instead of using a fake MBAR for some platforms. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: move ColdFire DMA register addresses to per-cpu headersGreg Ungerer10-27/+58
The base addresses of the ColdFire DMA unit registers belong with all the other address definitions in the per-cpu headers. The current definitions assume they are relative to an MBAR register. Not all ColdFire CPUs have an MBAR register. A clean address define can only be acheived in the per-cpu headers along with all the other chips peripheral base addresses. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: remove use of MBAR value for ColdFire 528x peripheral addressingGreg Ungerer2-10/+16
The ColdFire 528x family of CPUs does not have an MBAR register, so don't define its peripheral addresses relative to one. Its internal peripherals are relative to the IPSBAR register, so make sure to use that. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: remove use of MBAR value for ColdFire 527x peripheral addressingGreg Ungerer2-10/+18
The ColdFire 527x family of CPUs does not have an MBAR register, so don't define its peripheral addresses relative to one. Its internal peripherals are relative to the IPSBAR register, so make sure to use that. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: remove use of MBAR value for ColdFire 523x peripheral addressingGreg Ungerer2-8/+17
The ColdFire 523x family of CPUs does not have an MBAR register, so don't define its peripheral addresses relative to one. Its internal peripherals are relative to the IPSBAR register, so make sure to use that. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: remove MBAR and IPSBAR hacks for the ColdFire 520x CPUsGreg Ungerer4-43/+44
The ColdFire 5207 and 5208 CPUs have fixed peripheral addresses. They do not use the setable peripheral address registers like the MBAR and IPSBAR used on many other ColdFire parts. Don't use fake values of MBAR and IPSBAR when using peripheral addresses for them, there is no need to. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: move ColdFire PIT timer base addressesGreg Ungerer6-20/+32
The PIT hardware timer module used in some ColdFire CPU's is not always addressed relative to an IPSBAR register. Parts like the ColdFire 5207 and 5208 have fixed peripheral addresses. So lets not define the register addresses of the PIT relative to an IPSBAR definition. Move the base address definitions into the per-part headers. This is a lot more consistent since all the other peripheral base addresses are defined in the per-part header files already. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: remove bogus definition of MBAR for ColdFire 532x familyGreg Ungerer1-3/+0
Remove the bogus definition of the MBAR register for the ColdFire 532x family. It doesn't have an MBAR register, its peripheral registers are at fixed addresses and are not relative to a settable base. All the code that relyed on this definition existing has been cleaned up. The register address definitions now include the base as required. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: remove kludge seting of MCF_IPSBAR for ColdFire 54xxGreg Ungerer6-18/+18
The ColdFire 54xx family shares the same interrupt controller used on the 523x, 527x and 528x ColdFire parts, but it isn't offset relative to the IPSBAR register. The 54xx doesn't have an IPSBAR register. By including the base address of the peripheral registers in the register definitions (MCFICM_INTC0 and MCFICM_INTC1 in this case) we can avoid having to define a fake IPSBAR for the 54xx. And this makes the register address definitions of these more consistent, the majority of the other register address defines include the peripheral base address already. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: move ColdFire 5249 MBAR2 definitionGreg Ungerer2-1/+5
The MBAR2 register is only used on the ColdFire 5249 part, so move its definition out of the common coldfire.h and into the 5249 support header. Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: Select GENERIC_HARDIRQS_NO_DEPRECATEDThomas Gleixner1-0/+1
All chips converted and proper accessor functions used. Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: Use proper irq_desc accessors inThomas Gleixner1-2/+4
Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: Convert 5249 intc irq_chip to new functionsThomas Gleixner1-10/+10
/me idly wonders what sets the handlers for this chip. Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: Convert 5272 intc irq_chip to new functionsThomas Gleixner1-10/+18
Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: Convert 68360 ints irq_chip to new functionsThomas Gleixner1-9/+9
Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: Convert 68328 ints irq_chip to new functionsThomas Gleixner1-6/+6
Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: Convert coldfire intc-simr irq_chip to newThomas Gleixner1-6/+12
Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: Convert coldfire intc-2 irq_chip to newThomas Gleixner1-6/+10
Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: Convert coldfire intc irq_chip to newThomas Gleixner1-10/+10
Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15m68knommu: 5772: Replace private irq flow handlerThomas Gleixner1-4/+1
That handler lacks the minimal checks for action being zero etc. Keep the weird flow - ack before handling - intact and call into handle_simple_irq which does the right thing. Signed-off-by: Thomas Gleixner <[email protected]> Acked-by: Greg Ungerer <[email protected]> LKML-Reference: <[email protected]> Signed-off-by: Greg Ungerer <[email protected]>
2011-03-15microblaze: Do not copy reset vectors/manual reset vector setupMichal Simek3-6/+24
Reset vector can be setup by bootloader and kernel doens't need to touch it. If you require to setup reset vector, please use CONFIG_MANUAL_RESET_VECTOR throught menuconfig. It is not possible to setup address 0x0 as reset address because make no sense to set it up at all. Signed-off-by: Michal Simek <[email protected]> Signed-off-by: John Williams <[email protected]>
2011-03-15microblaze: Fix _reset functionMichal Simek1-1/+1
If soft reset falls through with no hardware assisted reset, the best we can do is jump to the reset vector and see what the bootloader left for us. Signed-off-by: Michal Simek <[email protected]> Signed-off-by: John Williams <[email protected]>
2011-03-15microblaze: Fix microblaze init vectorsMichal Simek1-1/+4
Microblaze vector table stores several vectors (reset, user exception, interrupt, debug exception and hardware exception). All these functions can be below address 0x10000. If they are, wrong vector table is genarated because jump is not setup from two instructions (imm upper 16bit and brai lower 16bit). Adding specific offset prevent problem if address is below 0x10000. For this case only brai instruction is used. Signed-off-by: Michal Simek <[email protected]>
2011-03-15ARM: 6806/1: irq: introduce entry and exit functions for chained handlersWill Deacon1-0/+31
Some chained IRQ handlers are written to cope with primary chips of potentially different flow types. Whether this a sensible thing to do is a point of contention. This patch introduces entry/exit functions for chained handlers which infer the flow type of the primary chip as fasteoi or level-type by checking whether or not the ->irq_eoi function pointer is present and calling back to the primary chip as necessary. Other methods of flow control are not considered. Acked-by: Thomas Gleixner <[email protected]> Acked-by: Catalin Marinas <[email protected]> Signed-off-by: Will Deacon <[email protected]> Signed-off-by: Russell King <[email protected]>
2011-03-15ARM: EXYNOS4: Add support for SATA on ARMLEX4210Abhilash Kesavan8-0/+280
Adds the device definitions, platform specific initialization and clocks for SATA on ARMLEX4210. Signed-off-by: Abhilash Kesavan <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2011-03-15x86, tlb, UV: Do small micro-optimization for native_flush_tlb_others()Xiao Guangrong1-2/+1
native_flush_tlb_others() is called from: flush_tlb_current_task() flush_tlb_mm() flush_tlb_page() All these functions disable preemption explicitly, so we can use smp_processor_id() instead of get_cpu() and put_cpu(). Signed-off-by: Xiao Guangrong <[email protected]> Cc: Cliff Wickman <[email protected]> LKML-Reference: <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
2011-03-15Merge commit 'v2.6.38' into x86/mmIngo Molnar196-1284/+1727
Conflicts: arch/x86/mm/numa_64.c Merge reason: Resolve the conflict, update the branch to .38. Signed-off-by: Ingo Molnar <[email protected]>
2011-03-15x86: Add new syscalls for x86_64Aneesh Kumar K.V2-0/+6
This patch add new syscalls to x86_64 Signed-off-by: Aneesh Kumar K.V <[email protected]> Signed-off-by: Al Viro <[email protected]>
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