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2010-05-17KVM: x86: fix the error of ioctl KVM_IRQ_LINE if no irq chipWei Yongjun1-0/+2
If no irq chip in kernel, ioctl KVM_IRQ_LINE will return -EFAULT. But I see in other place such as KVM_[GET|SET]IRQCHIP, -ENXIO is return. So this patch used -ENXIO instead of -EFAULT. Signed-off-by: Wei Yongjun <[email protected]> Signed-off-by: Marcelo Tosatti <[email protected]>
2010-05-17KVM: x86: Use native_store_idt() instead of kvm_get_idt()Wei Yongjun2-6/+1
This patch use generic linux function native_store_idt() instead of kvm_get_idt(), and also removed the useless function kvm_get_idt(). Signed-off-by: Wei Yongjun <[email protected]> Signed-off-by: Marcelo Tosatti <[email protected]>
2010-05-17KVM: Trace exception injectionAvi Kivity2-0/+35
Often an exception can help point out where things start to go wrong. Signed-off-by: Avi Kivity <[email protected]>
2010-05-17KVM: Move kvm_exit tracepoint rip reading inside tracepointAvi Kivity3-5/+5
Reading rip is expensive on vmx, so move it inside the tracepoint so we only incur the cost if tracing is enabled. Signed-off-by: Avi Kivity <[email protected]>
2010-05-17KVM: remove redundant initialization of page->privateMinchan Kim1-1/+0
The prep_new_page() in page allocator calls set_page_private(page, 0). So we don't need to reinitialize private of page. Signed-off-by: Minchan Kim <[email protected]> Cc: Avi Kivity<[email protected]> Signed-off-by: Avi Kivity <[email protected]>
2010-05-17KVM: cleanup kvm traceXiao Guangrong4-6/+11
This patch does: - no need call tracepoint_synchronize_unregister() when kvm module is unloaded since ftrace can handle it - cleanup ftrace's macro Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Avi Kivity <[email protected]>
2010-05-17KVM: x86 emulator mark VMMCALL and LMSW as privilegedGleb Natapov1-2/+2
LMSW is present in both group tables. It was marked privileged only in one of them. Intel analog of VMMCALL is already marked privileged. Signed-off-by: Gleb Natapov <[email protected]> Signed-off-by: Marcelo Tosatti <[email protected]>
2010-05-17KVM: SVM: Ignore lower 12 bit of nested msrpm_paJoerg Roedel1-1/+1
These bits are ignored by the hardware too. Implement this for nested svm too. Signed-off-by: Joerg Roedel <[email protected]> Signed-off-by: Marcelo Tosatti <[email protected]>
2010-05-17KVM; SVM: Add correct handling of nested iopmJoerg Roedel1-0/+25
This patch adds the correct handling of the nested io permission bitmap. Old behavior was to not lookup the port in the iopm but only reinject an io intercept to the guest. Signed-off-by: Joerg Roedel <[email protected]> Signed-off-by: Marcelo Tosatti <[email protected]>
2010-05-17KVM: SVM: Use svm_msrpm_offset in nested_svm_exit_handled_msrJoerg Roedel1-30/+17
There is a generic function now to calculate msrpm offsets. Use that function in nested_svm_exit_handled_msr() remove the duplicate logic (which had a bug anyway). Signed-off-by: Joerg Roedel <[email protected]> Signed-off-by: Marcelo Tosatti <[email protected]>
2010-05-17KVM: SVM: Optimize nested svm msrpm mergingJoerg Roedel1-9/+71
This patch optimizes the way the msrpm of the host and the guest are merged. The old code merged the 2 msrpm pages completly. This code needed to touch 24kb of memory for that operation. The optimized variant this patch introduces merges only the parts where the host msrpm may contain zero bits. This reduces the amount of memory which is touched to 48 bytes. Signed-off-by: Joerg Roedel <[email protected]> Signed-off-by: Marcelo Tosatti <[email protected]>
2010-05-17KVM: SVM: Introduce direct access msr listJoerg Roedel1-10/+46
This patch introduces a list with all msrs a guest might have direct access to and changes the svm_vcpu_init_msrpm function to use this list. It also adds a check to set_msr_interception which triggers a warning if a developer changes a msr intercept that is not in the list. Signed-off-by: Joerg Roedel <[email protected]> Signed-off-by: Marcelo Tosatti <[email protected]>
2010-05-17KVM: SVM: Move msrpm offset calculation to seperate functionJoerg Roedel1-16/+37
The algorithm to find the offset in the msrpm for a given msr is needed at other places too. Move that logic to its own function. Signed-off-by: Joerg Roedel <[email protected]> Signed-off-by: Marcelo Tosatti <[email protected]>
2010-05-17KVM: SVM: Return correct values in nested_svm_exit_handled_msrJoerg Roedel1-5/+5
The nested_svm_exit_handled_msr() returned an bool which is a bug. I worked by accident because the exected integer return values match with the true and false values. This patch changes the return value to int and let the function return the correct values. Signed-off-by: Joerg Roedel <[email protected]> Signed-off-by: Marcelo Tosatti <[email protected]>
2010-05-17KVM: arch/x86/kvm/kvm_timer.h checkpatch cleanupAndrea Gelmini1-3/+1
arch/x86/kvm/kvm_timer.h:13: ERROR: code indent should use tabs where possible Signed-off-by: Andrea Gelmini <[email protected]> Signed-off-by: Marcelo Tosatti <[email protected]>
2010-05-16x86, mrst: add nop functions to x86_init mpparse functionsJacob Pan1-0/+5
Moorestown does not have BIOS provided MP tables, we can save some time by avoiding scaning of these tables. e.g. [ 0.000000] Scan SMP from c0000000 for 1024 bytes. [ 0.000000] Scan SMP from c009fc00 for 1024 bytes. [ 0.000000] Scan SMP from c00f0000 for 65536 bytes. [ 0.000000] Scan SMP from c00bfff0 for 1024 bytes. Searching EBDA with the base at 0x40E will also result in random pointer deferencing within 1MB. This can be a problem in Lincroft if the pointer hits VGA area and VGA mode is not enabled. Signed-off-by: Jacob Pan <[email protected]> LKML-Reference: <[email protected]> Acked-by: Thomas Gleixner <[email protected]> Signed-off-by: H. Peter Anvin <[email protected]>
2010-05-16x86, mrst, pci: return 0 for non-present pci barsJacob Pan1-1/+1
Moorestown PCI code has special handling of devices with fixed BARs. In case of BAR sizing writes, we need to update the fake PCI MMCFG space with real size decode value. When a BAR is not present, we need to return 0 instead of ~0. ~0 will be treated as device error per bugzilla 12006. Signed-off-by: Jacob Pan <[email protected]> LKML-Reference: <[email protected]> Acked-by: Jesse Barnes <[email protected]> Acked-by: Thomas Gleixner <[email protected]> Signed-off-by: H. Peter Anvin <[email protected]>
2010-05-15x86, perf: P4 PMU - fix counters management logicCyrill Gorcunov1-4/+4
Jaswinder reported this #GP: | | Message from syslogd@ht at May 14 09:39:32 ... | kernel:[ 314.908612] EIP: [<c100ccca>] | x86_perf_event_set_period+0x19d/0x1b2 SS:ESP 0068:edac3d70 | Ming has narrowed it down to a comparision issue between arguments with different sizes and signs. As result event index reached a wrong value which in turn led to a GP fault. At the same time it was found that p4_next_cntr has broken logic and should return the counter index only if it was not yet borrowed for another event. Reported-by: Jaswinder Singh Rajput <[email protected]> Reported-by: Lin Ming <[email protected]> Bisected-by: Lin Ming <[email protected]> Tested-by: Jaswinder Singh Rajput <[email protected]> Signed-off-by: Cyrill Gorcunov <[email protected]> CC: Peter Zijlstra <[email protected]> CC: Frederic Weisbecker <[email protected]> LKML-Reference: <20100514190815.GG13509@lenovo> Signed-off-by: Ingo Molnar <[email protected]>
2010-05-14Merge branch 'x86-fixes-for-linus' of ↵Linus Torvalds1-0/+4
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, mrst: Don't blindly access extended config space
2010-05-14x86, mrst: Don't blindly access extended config spaceH. Peter Anvin1-0/+4
Do not blindly access extended configuration space unless we actively know we're on a Moorestown platform. The fixed-size BAR capability lives in the extended configuration space, and thus is not applicable if the configuration space isn't appropriately sized. This fixes booting certain VMware configurations with CONFIG_MRST=y. Moorestown will add a fake PCI-X 266 capability to advertise the presence of extended configuration space. Reported-and-tested-by: Petr Vandrovec <[email protected]> Signed-off-by: H. Peter Anvin <[email protected]> Acked-by: Jacob Pan <[email protected]> Acked-by: Jesse Barnes <[email protected]> LKML-Reference: <[email protected]>
2010-05-14Merge branch 'x86-fixes-for-linus' of ↵Linus Torvalds4-6/+18
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, cacheinfo: Turn off L3 cache index disable feature in virtualized environments x86, k8: Fix build error when K8_NB is disabled x86, amd: Check X86_FEATURE_OSVW bit before accessing OSVW MSRs x86: Fix fake apicid to node mapping for numa emulation
2010-05-14x86, cacheinfo: Turn off L3 cache index disable feature in virtualized ↵Frank Arnold1-0/+4
environments When running a quest kernel on xen we get: BUG: unable to handle kernel NULL pointer dereference at 0000000000000038 IP: [<ffffffff8142f2fb>] cpuid4_cache_lookup_regs+0x2ca/0x3df PGD 0 Oops: 0000 [#1] SMP last sysfs file: CPU 0 Modules linked in: Pid: 0, comm: swapper Tainted: G W 2.6.34-rc3 #1 /HVM domU RIP: 0010:[<ffffffff8142f2fb>] [<ffffffff8142f2fb>] cpuid4_cache_lookup_regs+0x 2ca/0x3df RSP: 0018:ffff880002203e08 EFLAGS: 00010046 RAX: 0000000000000000 RBX: 0000000000000003 RCX: 0000000000000060 RDX: 0000000000000000 RSI: 0000000000000040 RDI: 0000000000000000 RBP: ffff880002203ed8 R08: 00000000000017c0 R09: ffff880002203e38 R10: ffff8800023d5d40 R11: ffffffff81a01e28 R12: ffff880187e6f5c0 R13: ffff880002203e34 R14: ffff880002203e58 R15: ffff880002203e68 FS: 0000000000000000(0000) GS:ffff880002200000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 000000008005003b CR2: 0000000000000038 CR3: 0000000001a3c000 CR4: 00000000000006f0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400 Process swapper (pid: 0, threadinfo ffffffff81a00000, task ffffffff81a44020) Stack: ffffffff810d7ecb ffff880002203e20 ffffffff81059140 ffff880002203e30 <0> ffffffff810d7ec9 0000000002203e40 000000000050d140 ffff880002203e70 <0> 0000000002008140 0000000000000086 ffff880040020140 ffffffff81068b8b Call Trace: <IRQ> [<ffffffff810d7ecb>] ? sync_supers_timer_fn+0x0/0x1c [<ffffffff81059140>] ? mod_timer+0x23/0x25 [<ffffffff810d7ec9>] ? arm_supers_timer+0x34/0x36 [<ffffffff81068b8b>] ? hrtimer_get_next_event+0xa7/0xc3 [<ffffffff81058e85>] ? get_next_timer_interrupt+0x19a/0x20d [<ffffffff8142fa23>] get_cpu_leaves+0x5c/0x232 [<ffffffff8106a7b1>] ? sched_clock_local+0x1c/0x82 [<ffffffff8106a9a0>] ? sched_clock_tick+0x75/0x7a [<ffffffff8107748c>] generic_smp_call_function_single_interrupt+0xae/0xd0 [<ffffffff8101f6ef>] smp_call_function_single_interrupt+0x18/0x27 [<ffffffff8100a773>] call_function_single_interrupt+0x13/0x20 <EOI> [<ffffffff8143c468>] ? notifier_call_chain+0x14/0x63 [<ffffffff810295c6>] ? native_safe_halt+0xc/0xd [<ffffffff810114eb>] ? default_idle+0x36/0x53 [<ffffffff81008c22>] cpu_idle+0xaa/0xe4 [<ffffffff81423a9a>] rest_init+0x7e/0x80 [<ffffffff81b10dd2>] start_kernel+0x40e/0x419 [<ffffffff81b102c8>] x86_64_start_reservations+0xb3/0xb7 [<ffffffff81b103c4>] x86_64_start_kernel+0xf8/0x107 Code: 14 d5 40 ff ae 81 8b 14 02 31 c0 3b 15 47 1c 8b 00 7d 0e 48 8b 05 36 1c 8b 00 48 63 d2 48 8b 04 d0 c7 85 5c ff ff ff 00 00 00 00 <8b> 70 38 48 8d 8d 5c ff ff ff 48 8b 78 10 ba c4 01 00 00 e8 eb RIP [<ffffffff8142f2fb>] cpuid4_cache_lookup_regs+0x2ca/0x3df RSP <ffff880002203e08> CR2: 0000000000000038 ---[ end trace a7919e7f17c0a726 ]--- The L3 cache index disable feature of AMD CPUs has to be disabled if the kernel is running as guest on top of a hypervisor because northbridge devices are not available to the guest. Currently, this fixes a boot crash on top of Xen. In the future this will become an issue on KVM as well. Check if northbridge devices are present and do not enable the feature if there are none. [ hpa: backported to 2.6.34 ] Signed-off-by: Frank Arnold <[email protected]> LKML-Reference: <[email protected]> Acked-by: Borislav Petkov <[email protected]> Signed-off-by: H. Peter Anvin <[email protected]> Cc: <[email protected]>
2010-05-14x86, k8: Fix build error when K8_NB is disabledBorislav Petkov1-0/+5
K8_NB depends on PCI and when the last is disabled (allnoconfig) we fail at the final linking stage due to missing exported num_k8_northbridges. Add a header stub for that. Signed-off-by: Borislav Petkov <[email protected]> LKML-Reference: <20100503183036.GJ26107@aftab> Signed-off-by: H. Peter Anvin <[email protected]> Cc: <[email protected]>
2010-05-14add descriptive comment for TIF_MEMDIE task flag declaration.Andreas Dilger1-1/+1
Signed-off-by: Andreas Dilger <[email protected]> Acked-by: KOSAKI Motohiro <[email protected]> Signed-off-by: Jiri Kosina <[email protected]>
2010-05-13x86: Use .cfi_sections for assembly codeRoland McGrath2-2/+15
The newer assemblers support the .cfi_sections directive so we can put the CFI from .S files into the .debug_frame section that is preserved in unstripped vmlinux and in separate debuginfo, rather than the .eh_frame section that is now discarded by vmlinux.lds.S. Signed-off-by: Roland McGrath <[email protected]> LKML-Reference: <[email protected]> Signed-off-by: H. Peter Anvin <[email protected]>
2010-05-13x86, amd: Check X86_FEATURE_OSVW bit before accessing OSVW MSRsAndreas Herrmann1-5/+7
If host CPU is exposed to a guest the OSVW MSRs are not guaranteed to be present and a GP fault occurs. Thus checking the feature flag is essential. Cc: <[email protected]> # .32.x .33.x Signed-off-by: Andreas Herrmann <[email protected]> LKML-Reference: <[email protected]> Signed-off-by: H. Peter Anvin <[email protected]>
2010-05-13x86, perf: P4 PMU -- use hash for p4_get_escr_idx()Cyrill Gorcunov1-55/+71
Linear search over all p4 MSRs should be fine if only we would not use it in events scheduling routine which is pretty time critical. Lets use hashes. It should speed scheduling up significantly. v2: Steven proposed to use more gentle approach than issue BUG on error, so we use WARN_ONCE now Signed-off-by: Cyrill Gorcunov <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Steven Rostedt <[email protected]> Cc: Frederic Weisbecker <[email protected]> Cc: Lin Ming <[email protected]> LKML-Reference: <20100512174242.GA5190@lenovo> Signed-off-by: Ingo Molnar <[email protected]>
2010-05-13KVM: VMX: blocked-by-sti must not defer NMI injectionsJan Kiszka1-2/+1
As the processor may not consider GUEST_INTR_STATE_STI as a reason for blocking NMI, it could return immediately with EXIT_REASON_NMI_WINDOW when we asked for it. But as we consider this state as NMI-blocking, we can run into an endless loop. Resolve this by allowing NMI injection if just GUEST_INTR_STATE_STI is active (originally suggested by Gleb). Intel confirmed that this is safe, the processor will never complain about NMI injection in this state. Signed-off-by: Jan Kiszka <[email protected]> KVM-Stable-Tag Acked-by: Gleb Natapov <[email protected]> Signed-off-by: Marcelo Tosatti <[email protected]>
2010-05-13KVM: x86: Call vcpu_load and vcpu_put in cpuid_updateDongxiao Xu1-0/+4
cpuid_update may operate VMCS, so vcpu_load() and vcpu_put() should be called to ensure correctness. Signed-off-by: Dongxiao Xu <[email protected]> Signed-off-by: Marcelo Tosatti <[email protected]>
2010-05-13KVM: SVM: Fix wrong intercept masks on 32 bitJoerg Roedel1-4/+4
This patch makes KVM on 32 bit SVM working again by correcting the masks used for iret interception. With the wrong masks the upper 32 bits of the intercepts are masked out which leaves vmrun unintercepted. This is not legal on svm and the vmrun fails. Bug was introduced by commits 95ba827313 and 3cfc3092. Cc: Jan Kiszka <[email protected]> Cc: Gleb Natapov <[email protected]> Cc: [email protected] Signed-off-by: Joerg Roedel <[email protected]> Signed-off-by: Avi Kivity <[email protected]>
2010-05-12ACPI: Unconditionally set SCI_EN on resumeMatthew Garrett1-2/+0
The ACPI spec tells us that the firmware will reenable SCI_EN on resume. Reality disagrees in some cases. The ACPI spec tells us that the only way to set SCI_EN is via an SMM call. https://bugzilla.kernel.org/show_bug.cgi?id=13745 shows us that doing so may break machines. Tracing the ACPI calls made by Windows shows that it unconditionally sets SCI_EN on resume with a direct register write, and therefore the overwhelming probability is that everything is fine with this behaviour. Signed-off-by: Matthew Garrett <[email protected]> Tested-by: Rafael J. Wysocki <[email protected]> Signed-off-by: Len Brown <[email protected]>
2010-05-11x86, fpu: Use static_cpu_has() to implement use_xsave()H. Peter Anvin1-9/+3
use_xsave() is now just a special case of static_cpu_has(), so use static_cpu_has(). Signed-off-by: H. Peter Anvin <[email protected]> Cc: Avi Kivity <[email protected]> Cc: Suresh Siddha <[email protected]> LKML-Reference: <[email protected]>
2010-05-11x86: Add new static_cpu_has() function using alternativesH. Peter Anvin1-0/+57
For CPU-feature-specific code that touches performance-critical paths, introduce a static patching version of [boot_]cpu_has(). This is run at alternatives time and is therefore not appropriate for most initialization code, but on the other hand initialization code is generally not performance critical. On gcc 4.5+ this uses the new "asm goto" feature. Signed-off-by: H. Peter Anvin <[email protected]> Cc: Avi Kivity <[email protected]> Cc: Suresh Siddha <[email protected]> LKML-Reference: <[email protected]>
2010-05-11x86/PCI: irq and pci_ids patch for additional Intel Cougar Point DeviceIDsSeth Heasley1-2/+7
This patch adds additional LPC Controller DeviceIDs for the Intel Cougar Point PCH. The DeviceIDs are defined and referenced as a range of values, the same way Ibex Peak was implemented. Signed-off-by: Seth Heasley <[email protected]> Signed-off-by: Jesse Barnes <[email protected]>
2010-05-11x86/PCI: Convert pci_config_lock to raw_spinlockThomas Gleixner6-22/+22
pci_config_lock must be a real spinlock in preempt-rt. Convert it to raw_spinlock. No change for !RT kernels. Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Jesse Barnes <[email protected]>
2010-05-11Merge branch 'iommu/largepages' into amd-iommu/2.6.35Joerg Roedel2-71/+160
Conflicts: arch/x86/kernel/amd_iommu.c
2010-05-11x86/amd-iommu: Add amd_iommu=off command line optionJoerg Roedel1-0/+6
This patch adds a command line option to tell the AMD IOMMU driver to not initialize any IOMMU it finds. Signed-off-by: Joerg Roedel <[email protected]>
2010-05-11kprobes/x86: Fix removed int3 checking orderMasami Hiramatsu1-14/+13
Fix kprobe/x86 to check removed int3 when failing to get kprobe from hlist. Since we have a time window between checking int3 exists on probed address and getting kprobe on that address, we can have following scenario: ------- CPU1 CPU2 hit int3 check int3 exists remove int3 remove kprobe from hlist get kprobe from hlist no kprobe->OOPS! ------- This patch moves int3 checking if there is no kprobe on that address for fixing this problem as follows: ------ CPU1 CPU2 hit int3 remove int3 remove kprobe from hlist get kprobe from hlist no kprobe->check int3 exists ->rollback&retry ------ Signed-off-by: Masami Hiramatsu <[email protected]> Acked-by: Ananth N Mavinakayanahalli <[email protected]> Cc: systemtap <[email protected]> Cc: DLE <[email protected]> Cc: Dave Anderson <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Mike Galbraith <[email protected]> Cc: Paul Mackerras <[email protected]> Cc: Arnaldo Carvalho de Melo <[email protected]> Cc: Frederic Weisbecker <[email protected]> LKML-Reference: <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
2010-05-10x86, fpu: Use the proper asm constraint in use_xsave()H. Peter Anvin1-1/+1
The proper constraint for a receiving 8-bit variable is "=qm", not "=g" which equals "=rim"; even though the "i" will never match, bugs can and do happen due to the difference between "q" and "r". Signed-off-by: H. Peter Anvin <[email protected]> Cc: Avi Kivity <[email protected]> Cc: Suresh Siddha <[email protected]> LKML-Reference: <[email protected]>
2010-05-10x86, fpu: Unbreak FPU emulationH. Peter Anvin3-4/+4
Unbreak FPU emulation, broken by checkin 86603283326c9e95e5ad4e9fdddeec93cac5d9ad: x86: Introduce 'struct fpu' and related API Signed-off-by: H. Peter Anvin <[email protected]> Cc: Avi Kivity <[email protected]> Cc: Suresh Siddha <[email protected]> LKML-Reference: <[email protected]>
2010-05-10Merge remote branch 'origin/master' into drm-intel-nextEric Anholt18-108/+151
Conflicts: drivers/gpu/drm/i915/i915_dma.c drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/radeon/r300.c The BSD ringbuffer support that is landing in this branch significantly conflicts with the Ironlake PIPE_CONTROL fix on master, and requires it to be tested successfully anyway.
2010-05-10x86: Introduce 'struct fpu' and related APIAvi Kivity9-103/+160
Currently all fpu state access is through tsk->thread.xstate. Since we wish to generalize fpu access to non-task contexts, wrap the state in a new 'struct fpu' and convert existing access to use an fpu API. Signal frame handlers are not converted to the API since they will remain task context only things. Signed-off-by: Avi Kivity <[email protected]> Acked-by: Suresh Siddha <[email protected]> LKML-Reference: <[email protected]> Signed-off-by: H. Peter Anvin <[email protected]>
2010-05-10x86: Eliminate TS_XSAVEAvi Kivity5-16/+21
The fpu code currently uses current->thread_info->status & TS_XSAVE as a way to distinguish between XSAVE capable processors and older processors. The decision is not really task specific; instead we use the task status to avoid a global memory reference - the value should be the same across all threads. Eliminate this tie-in into the task structure by using an alternative instruction keyed off the XSAVE cpu feature; this results in shorter and faster code, without introducing a global memory reference. [ hpa: in the future, this probably should use an asm jmp ] Signed-off-by: Avi Kivity <[email protected]> Acked-by: Suresh Siddha <[email protected]> LKML-Reference: <[email protected]> Signed-off-by: H. Peter Anvin <[email protected]>
2010-05-10i7core_edac: do not export static functionsStephen Rothwell1-1/+0
Signed-off-by: Stephen Rothwell <[email protected]> Signed-off-by: Mauro Carvalho Chehab <[email protected]>
2010-05-10i7core_edac: Add a code to probe Xeon 55xx busMauro Carvalho Chehab1-0/+1
This code changes the detection procedure of i7core_edac. Instead of directly probing for MC registers, it probes for another register found on Nehalem. If found, it tries to pick the first MC PCI BUS. This should work fine with Xeon 35xx, but, on Xeon 55xx, this is at bus 254 and 255 that are not properly detected by the non-legacy PCI methods. The new detection code scans specifically at buses 254 and 255 for the Xeon 55xx devices. This code has not tested yet. After working, a change at the code will be needed, since the i7core is not yet ready for working with 2 sets of MC. Signed-off-by: Mauro Carvalho Chehab <[email protected]>
2010-05-10pci: Add a probing code that seeks for an specific busAristeu Rozanski2-17/+27
This patch adds a probing code that seeks for an specific pci bus. It still needs testing, but it is hoped that this will help to identify the memory controller with Xeon 55xx series. Signed-off-by: Aristeu Sergio <[email protected]> Signed-off-by: Mauro Carvalho Chehab <[email protected]>
2010-05-10edac_mce: Add an interface driver to report mce errors via edacMauro Carvalho Chehab1-0/+10
edac_mce module is an interface module that gets mcelog data and forwards to any registered edac module that expects to receive data via mce. Signed-off-by: Mauro Carvalho Chehab <[email protected]>
2010-05-10Merge branch 'core' of ↵Ingo Molnar3-113/+130
git://git.kernel.org/pub/scm/linux/kernel/git/rric/oprofile into oprofile
2010-05-10Merge commit 'v2.6.34-rc7' into oprofileIngo Molnar18-108/+151
Merge reason: Update to Linus's latest -rc. Signed-off-by: Ingo Molnar <[email protected]>
2010-05-09x86, hypervisor: add missing <linux/module.h>H. Peter Anvin2-0/+2
EXPORT_SYMBOL() needs <linux/module.h> to be included; fixes modular builds of the VMware balloon driver, and any future modular drivers which depends on the hypervisor. Reported-by: Ingo Molnar <[email protected]> Signed-off-by: H. Peter Anvin <[email protected]> Cc: Greg KH <[email protected]> Cc: Hank Janssen <[email protected]> Cc: Alok Kataria <[email protected]> Cc: Ky Srinivasan <[email protected]> Cc: Dmitry Torokhov <[email protected]> LKML-Reference: <[email protected]>
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