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AgeCommit message (Expand)AuthorFilesLines
2018-05-19x86/intel_rdt/mba_sc: Add schemata supportVikas Shivappa2-6/+20
2018-05-19x86/intel_rdt/mba_sc: Add initialization supportVikas Shivappa3-10/+33
2018-05-19x86/intel_rdt/mba_sc: Enable/disable MBA software controllerVikas Shivappa3-0/+41
2018-05-19x86/mm: Introduce the 'no5lvl' kernel parameterKirill A. Shutemov1-0/+15
2018-05-19Merge branches 'x86/urgent' and 'core/urgent' into x86/boot, to pick up fixes...Ingo Molnar4-7/+10
2018-05-18x86/bugs: Rename SSBD_NO to SSB_NOKonrad Rzeszutek Wilk1-1/+1
2018-05-17KVM: SVM: Implement VIRT_SPEC_CTRL support for SSBDTom Lendacky1-1/+2
2018-05-17x86/speculation, KVM: Implement support for VIRT_SPEC_CTRL/LS_CFGThomas Gleixner1-0/+30
2018-05-17x86/bugs: Rework spec_ctrl base and mask logicThomas Gleixner1-7/+19
2018-05-17x86/bugs: Remove x86_spec_ctrl_set()Thomas Gleixner1-11/+2
2018-05-17x86/bugs: Expose x86_spec_ctrl_base directlyThomas Gleixner1-10/+1
2018-05-17x86/bugs: Unify x86_spec_ctrl_{set_guest,restore_host}Borislav Petkov1-45/+15
2018-05-17x86/speculation: Rework speculative_store_bypass_update()Thomas Gleixner1-1/+1
2018-05-17x86/speculation: Add virtualized speculative store bypass disable supportTom Lendacky1-1/+3
2018-05-17x86/bugs, KVM: Extend speculation control for VIRT_SPEC_CTRLThomas Gleixner1-2/+18
2018-05-17x86/cpufeatures: Add FEATURE_ZENThomas Gleixner1-0/+1
2018-05-17x86/cpufeatures: Disentangle SSBD enumerationThomas Gleixner4-11/+10
2018-05-17x86/cpufeatures: Disentangle MSR_SPEC_CTRL enumeration from IBRSThomas Gleixner3-9/+19
2018-05-17x86/speculation: Use synthetic bits for IBRS/IBPB/STIBPBorislav Petkov1-4/+10
2018-05-16x86/mtrr: Convert to use strncpy_from_user() helperAndy Shevchenko1-10/+2
2018-05-16x86/mtrr: Convert to use match_string() helperAndy Shevchenko1-11/+10
2018-05-13x86/mtrr: Rename main.c to mtrr.c and remove duplicate prefixesJoe Perches2-18/+17
2018-05-13x86/CPU: Move x86_cpuinfo::x86_max_cores assignment to detect_num_cpu_cores()Thomas Gleixner4-8/+7
2018-05-13x86/Centaur: Report correct CPU/cache topologyDavid Wang1-0/+5
2018-05-13x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo()David Wang3-13/+8
2018-05-13x86/CPU: Make intel_num_cpu_cores() genericDavid Wang3-19/+16
2018-05-13x86/CPU: Move cpu local function declarations to local headerThomas Gleixner2-0/+11
2018-05-12x86/bugs: Fix the parameters alignment and missing voidKonrad Rzeszutek Wilk1-2/+2
2018-05-10x86/bugs: Make cpu_show_common() staticJiri Kosina1-1/+1
2018-05-10x86/bugs: Fix __ssb_select_mitigation() return typeJiri Kosina1-1/+1
2018-05-09x86/bugs: Rename _RDS to _SSBDKonrad Rzeszutek Wilk4-27/+27
2018-05-06x86/CPU/AMD: Derive CPU topology from CPUID function 0xB when availableSuravee Suthikulpanit1-1/+10
2018-05-06x86/CPU: Modify detect_extended_topology() to return resultSuravee Suthikulpanit1-4/+4
2018-05-06x86/CPU/AMD: Calculate last level cache ID from number of sharing threadsSuravee Suthikulpanit2-16/+42
2018-05-06x86/CPU: Rename intel_cacheinfo.c to cacheinfo.cBorislav Petkov2-1/+1
2018-05-06x86/CPU/AMD: Have smp_num_siblings and cpu_llc_id always be presentBorislav Petkov2-9/+8
2018-05-06x86/MCE: Fix stack out-of-bounds write in mce-inject.c: Flags_read()Luck, Tony1-1/+1
2018-05-06x86/MCE: Enable MCE broadcasting on new Centaur CPUsDavid Wang1-0/+18
2018-05-05x86/speculation: Make "seccomp" the default mode for Speculative Store BypassKees Cook1-9/+23
2018-05-05seccomp: Move speculation migitation control to arch codeThomas Gleixner1-11/+18
2018-05-05prctl: Add force disable speculationThomas Gleixner1-10/+25
2018-05-05x86/bugs: Make boot modes __ro_after_initKees Cook1-2/+3
2018-05-03nospec: Allow getting/setting on non-current taskKees Cook1-11/+16
2018-05-03x86/speculation: Add prctl for Speculative Store Bypass mitigationThomas Gleixner1-10/+73
2018-05-03x86/process: Allow runtime control of Speculative Store BypassThomas Gleixner1-5/+21
2018-05-03x86/speculation: Create spec-ctrl.h to avoid include hellThomas Gleixner2-2/+2
2018-05-03x86/bugs/AMD: Add support to disable RDS on Fam[15,16,17]h if requestedKonrad Rzeszutek Wilk3-1/+56
2018-05-03x86/bugs: Whitelist allowed SPEC_CTRL MSR valuesKonrad Rzeszutek Wilk1-2/+9
2018-05-03x86/bugs/intel: Set proper CPU features and setup RDSKonrad Rzeszutek Wilk4-6/+37
2018-05-03x86/bugs: Provide boot parameters for the spec_store_bypass_disable mitigationKonrad Rzeszutek Wilk1-0/+103
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