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path: root/arch/x86/include/asm/irq_vectors.h
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2009-06-03x86, mce: implement bootstrapping for machine check wakeupsAndi Kleen1-0/+5
Machine checks support waking up the mcelog daemon quickly. The original wake up code for this was pretty ugly, relying on a idle notifier and a special process flag. The reason it did it this way is that the machine check handler is not subject to normal interrupt locking rules so it's not safe to call wake_up(). Instead it set a process flag and then either did the wakeup in the syscall return or in the idle notifier. This patch adds a new "bootstraping" method as replacement. The idea is that the handler checks if it's in a state where it is unsafe to call wake_up(). If it's safe it calls it directly. When it's not safe -- that is it interrupted in a critical section with interrupts disables -- it uses a new "self IPI" to trigger an IPI to its own CPU. This can be done safely because IPI triggers are atomic with some care. The IPI is raised once the interrupts are reenabled and can then safely call wake_up(). When APICs are disabled the event is just queued and will be picked up eventually by the next polling timer. I think that's a reasonable compromise, since it should only happen quite rarely. Contains fixes from Ying Huang. [ solve conflict on irqinit, make it work on 32bit (entry_arch.h) - HS ] Signed-off-by: Andi Kleen <[email protected]> Signed-off-by: Hidetoshi Seto <[email protected]> Signed-off-by: H. Peter Anvin <[email protected]>
2009-06-03perf_counter/x86: Remove the IRQ (non-NMI) handling bitsYong Wang1-5/+0
Remove the IRQ (non-NMI) handling bits as NMI will be used always. Signed-off-by: Yong Wang <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Mike Galbraith <[email protected]> Cc: Paul Mackerras <[email protected]> Cc: Corey Ashford <[email protected]> Cc: Marcelo Tosatti <[email protected]> Cc: Arnaldo Carvalho de Melo <[email protected]> Cc: John Kacur <[email protected]> LKML-Reference: <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
2009-06-01Merge branch 'irq/numa' into x86/mce3H. Peter Anvin1-0/+1
Merge reason: arch/x86/kernel/irqinit_{32,64}.c unified in irq/numa and modified in x86/mce3; this merge resolves the conflict. Conflicts: arch/x86/kernel/irqinit.c Signed-off-by: H. Peter Anvin <[email protected]>
2009-05-28x86: trivial clean up for irq_vectors.hAndi Kleen1-2/+1
Fix a wrong comment. Signed-off-by: Hidetoshi Seto <[email protected]> Cc: Andi Kleen <[email protected]> Signed-off-by: H. Peter Anvin <[email protected]>
2009-05-28x86, mce: enable MCE_INTEL for 32bit new MCEAndi Kleen1-2/+3
Enable the 64bit MCE_INTEL code (CMCI, thermal interrupts) for 32bit NEW_MCE. Signed-off-by: Andi Kleen <[email protected]> Signed-off-by: H. Peter Anvin <[email protected]> Signed-off-by: Hidetoshi Seto <[email protected]> Signed-off-by: H. Peter Anvin <[email protected]>
2009-04-10x86: define IA32_SYSCALL_VECTOR on 32-bit to reduce ifdefsPekka Enberg1-0/+1
Impact: cleanup We can remove some #ifdefs if we define IA32_SYSCALL_VECTOR on 32-bit. Reviewed-by Cyrill Gorcunov <[email protected]> Signed-off-by: Pekka Enberg <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
2009-04-07perf_counter: x86: self-IPI for pending workPeter Zijlstra1-0/+5
Implement set_perf_counter_pending() with a self-IPI so that it will run ASAP in a usable context. For now use a second IRQ vector, because the primary vector pokes the apic in funny ways that seem to confuse things. Signed-off-by: Peter Zijlstra <[email protected]> Cc: Paul Mackerras <[email protected]> Cc: Corey Ashford <[email protected]> LKML-Reference: <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
2009-03-04x86: UV, SGI RTC: add generic system vectorDimitri Sivanich1-0/+5
This patch allocates a system interrupt vector for various platform specific uses. Signed-off-by: Dimitri Sivanich <[email protected]> Cc: Andrew Morton <[email protected]> Cc: john stultz <[email protected]> LKML-Reference: <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
2009-02-24x86: invalid_vm86_irq -- use predefined macrosCyrill Gorcunov1-1/+1
Impact: cleanup Signed-off-by: Cyrill Gorcunov <[email protected]> Cc: [email protected] Cc: Cyrill Gorcunov <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
2009-01-31x86, vm86: clean up invalid_vm86_irq()Ingo Molnar1-1/+7
Signed-off-by: Ingo Molnar <[email protected]>
2009-01-31x86, irq: describe NR_IRQ sizing details, clean upIngo Molnar1-9/+23
Impact: cleanup Signed-off-by: Ingo Molnar <[email protected]>
2009-01-31x86, irq_vectors.h: remove needless includesIngo Molnar1-14/+8
Reduce include file dependencies a bit - remove the two headers that are included in irq_vectors.h. Signed-off-by: Ingo Molnar <[email protected]>
2009-01-31x86, irq: add IRQ layout commentsIngo Molnar1-34/+58
Describe the layout of x86 trap/exception/IRQ vectors and clean up indentation and other small details. Signed-off-by: Ingo Molnar <[email protected]>
2009-01-31x86, irqs, voyager: remove Voyager quirkIngo Molnar1-11/+3
Remove a Voyager complication from the generic irq_vectors.h header. Signed-off-by: Ingo Molnar <[email protected]>
2009-01-31x86, voyager: move Voyager-specific defines to voyager.hIngo Molnar1-35/+0
They dont belong into the generic headers. Signed-off-by: Ingo Molnar <[email protected]>
2009-01-31x86, apic: clean up spurious vector sanity checkIngo Molnar1-0/+7
Move the spurious vector sanity check to the place where it's defined - out of a .c file. Signed-off-by: Ingo Molnar <[email protected]>
2009-01-31x86, apic: unify the APIC vector enumerationIngo Molnar1-23/+12
Most of the vector layout on 32-bit and 64-bit is identical now, so eliminate the duplicated enumeration of the vectors. Signed-off-by: Ingo Molnar <[email protected]>
2009-01-31x86, irq: add LOCAL_PERF_VECTORIngo Molnar1-0/+5
Add a slot for the performance monitoring interrupt. Not yet used by any subsystem - but the hardware has it. (This eases integration with performance monitoring code.) Signed-off-by: Ingo Molnar <[email protected]>
2009-01-21x86: make x86_32 use tlb_64.cTejun Heo1-2/+5
Impact: less contention when issuing invalidate IPI, cleanup Make x86_32 use the same tlb code as 64bit. The 64bit code uses multiple IPI vectors for tlb shootdown to reduce contention. This patch makes x86_32 allocate the same 8 IPIs as x86_64 and share the code paths. Note that the usage of asmlinkage is inconsistent for x86_32 and 64 and calls for further cleanup. This has been noted with a FIXME comment in tlb_64.c. Signed-off-by: Tejun Heo <[email protected]>
2009-01-21x86: prepare for tlb mergeTejun Heo1-17/+16
Impact: clean up, ipi vector number reordering for x86_32 Make the following changes to prepare for tlb merge. * reorder x86_32 ip vectors * adjust tlb_32.c and tlb_64.c such that their logics coincide exactly - on spurious invalidate ipi, tlb_32 acks the irq - tlb_64 now has proper memory barriers around clearing flush_cpumask (no change in generated code) * unexport flush_tlb_page from tlb_32.c, there's no user * use unsigned int for cpu id * drop unnecessary includes from tlb_64.c Signed-off-by: Tejun Heo <[email protected]>
2009-01-12x86: arch_probe_nr_irqsYinghai Lu1-5/+2
Impact: save RAM with large NR_CPUS, get smaller nr_irqs Signed-off-by: Yinghai Lu <[email protected]> Signed-off-by: Mike Travis <[email protected]>
2009-01-11irq: initialize nr_irqs based on nr_cpu_idsMike Travis1-5/+11
Impact: Reduce memory usage. This is the second half of the changes to make the irq_desc_ptrs be variable sized based on nr_cpu_ids. This is done by adding a new "max_nr_irqs" macro to irq_vectors.h (and a dummy in irqnr.h) to return a max NR_IRQS value based on NR_CPUS or nr_cpu_ids. This necessitated moving the define of MAX_IO_APICS to a separate file (asm/apicnum.h) so it could be included without the baggage of the other asm/apicdef.h declarations. Signed-off-by: Mike Travis <[email protected]>
2008-12-08x86: use NR_IRQS_LEGACYYinghai Lu1-0/+2
Impact: cleanup Introduce NR_IRQS_LEGACY instead of hard coded number. Signed-off-by: Yinghai Lu <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
2008-12-08sparse irq_desc[] array: core kernel and x86 changesYinghai Lu1-0/+9
Impact: new feature Problem on distro kernels: irq_desc[NR_IRQS] takes megabytes of RAM with NR_CPUS set to large values. The goal is to be able to scale up to much larger NR_IRQS value without impacting the (important) common case. To solve this, we generalize irq_desc[NR_IRQS] to an (optional) array of irq_desc pointers. When CONFIG_SPARSE_IRQ=y is used, we use kzalloc_node to get irq_desc, this also makes the IRQ descriptors NUMA-local (to the site that calls request_irq()). This gets rid of the irq_cfg[] static array on x86 as well: irq_cfg now uses desc->chip_data for x86 to store irq_cfg. Signed-off-by: Yinghai Lu <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
2008-11-06x86: remove VISWS and PARAVIRT around NR_IRQS puzzleYinghai Lu1-3/+3
Impact: fix warning message when PARAVIRT is set in config Remove stale #ifdef components from our IRQ sizing logic. x86/Voyager is the only holdout. Signed-off-by: Yinghai Lu <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
2008-11-06x86: size NR_IRQS on 32-bit systems the same way as 64-bitYinghai Lu1-14/+6
Impact: make NR_IRQS big enough for system with lots of apic/pins If lots of IO_APIC's are there (or can be there), size the same way as 64-bit, depending on MAX_IO_APICS and NR_CPUS. This fixes the boot problem reported by Ben Hutchings on a 32-bit server with 5 IO-APICs and 240 IO-APIC pins. Signed-off-by: Yinghai <[email protected]> Tested-by: Ben Hutchings <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
2008-10-22x86: Fix ASM_X86__ header guardsH. Peter Anvin1-3/+3
Change header guards named "ASM_X86__*" to "_ASM_X86_*" since: a. the double underscore is ugly and pointless. b. no leading underscore violates namespace constraints. Signed-off-by: H. Peter Anvin <[email protected]>
2008-10-22x86, um: ... and asm-x86 moveAl Viro1-0/+164
Signed-off-by: Al Viro <[email protected]> Signed-off-by: H. Peter Anvin <[email protected]>
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