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Add a dmaengine platform device to sh7724, fix DMA channel interrupt numbers.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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Signed-off-by: Valentin Sitdikov <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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Conflicts:
arch/sh/mm/cache-sh4.c
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Signed-off-by: Yoshihiro Shimoda <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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This paves the way for allowing individual CPUs to overload the
individual flushing routines that they care about without having to
depend on weak aliases. SH-4 is converted over initially, as it wires
up pretty much everything. The majority of the other CPUs will simply use
the default no-op implementation with their own region flushers wired up.
Signed-off-by: Paul Mundt <[email protected]>
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We use flush_cache_page() outright in copy_to_user_page(), and nothing
else needs it, so just kill it off. SH-5 still defines its own version,
but that too will go away in the same fashion once it converts over.
Signed-off-by: Paul Mundt <[email protected]>
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All of the flush_dcache_mmap_lock()/flush_dcache_mmap_unlock()
definitions are identical across all CPUs, so just provide them
generically in asm/cacheflush.h.
Signed-off-by: Paul Mundt <[email protected]>
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flush_dcache_all() is used internally by the SH-4 cache code, it is not
part of the exported cache API, so make it static and don't export it.
Signed-off-by: Paul Mundt <[email protected]>
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This provides a central point for CPU cache initialization routines.
This replaces the antiquated p3_cache_init() method, which the vast
majority of CPUs never cared about.
Signed-off-by: Paul Mundt <[email protected]>
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This does a bit of reorganizing for allowing nommu to use the new
and generic cache.c, no functional changes.
Signed-off-by: Paul Mundt <[email protected]>
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Signed-off-by: Kuninori Morimoto <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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This patch adds hwblk support for the sh7724 processor.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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This inverts the delayed dcache flush a bit to be more in line with other
platforms. At the same time this also gives us the ability to do some
more optimizations and cleanup. Now that the update_mmu_cache() callsite
only tests for the bit, the implementation can gradually be split out and
made generic, rather than relying on special implementations for each of
the peculiar CPU types.
SH7705 in 32kB mode and SH-4 still need slightly different handling, but
this is something that can remain isolated in the varying page copy/clear
routines. On top of that, SH-X3 is dcache coherent, so there is no need
to bother with any of these tests in the PTEAEX version of
update_mmu_cache(), so we kill that off too.
Signed-off-by: Paul Mundt <[email protected]>
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This patch adds hwblk support for the sh7723 processor.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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This patch contains the sh7722 specific hwblk implementation.
Hwblk ids are added to the processor specific header file,
module stop bits and areas are kept track of as hwblks,
clocks are converted to make use of the shared hwblk code.
Code to determine allowed sleep modes is also added.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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This patch adds sh7722 mode pin and pin function
controller comments.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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This patch adds comments for the sh7724 mode pins
and pin function controller.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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This patch is sh7723 mode pin V2. Mode pins and
pin function controller comments are added.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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This patch reworks the mode pin code to keep the pin
definitions in one place. The mode pins values are now
the value of the bit instead of bit number.
With this patch in place the sh7785 header file contains
mode pin comments. The sh7785 clock code and the sh7785lcr
board code are updated to reflect the new shared mode pins.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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Signed-off-by: Kuninori Morimoto <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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This patch adds sh7785 mode pin definitions. Mode pins and
pin function controller comments are added as well.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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This patch removes the old TMU driver (CONFIG_SH_TMU/timer-tmu.c)
As replacement, select the sh_tmu driver with CONFIG_SH_TIMER_TMU
and configure timer channel using platform data.
If multiple TMU channels are enabled using platform data, use the
earlytimer parameter on the kernel command line to select channel.
For instance, use "earlytimer=sh_tmu.0" to select the first channel.
To verify which timer is being used, look at printouts or the timer
irq count in /proc/interrupts.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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This implements initial support for the SH-Mobile R2R CPU.
Based on Rev 0.11 of the initial SH7724 hardware manual.
Signed-off-by: Kuninori Morimoto <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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Formatting and typo fix.
Signed-off-by: Kuninori Morimoto <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores
that implement the PTAEX register and respective functionality. Presently
only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs).
The main change is in how the PTE is written out when loading the entry
in to the TLB, as well as in how the TLB entry is selectively flushed.
While SH-X2 extended mode splits out the memory-mapped U and I-TLB data
arrays for extra bits, extended ASID mode splits out the address arrays.
While we don't use the memory-mapped data array access, the address
array accesses are necessary for selective TLB flushes, so these are
implemented newly and replace the generic SH-4 implementation.
With this, TLB flushes in switch_mm() are almost non-existent on newer
parts.
Signed-off-by: Paul Mundt <[email protected]>
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This adds DMA support for newer SH-4A CPUs, particularly SH7763/64/80/85.
This also enables multi IRQ support for platforms that have multiple
vectors bound to the same IRQ source.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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This adds preliminary support for the SH7786 CPU subtype.
While this is a dual-core CPU, only UP is supported for now. L2 cache
support is likewise not yet implemented.
More information on this particular CPU subtype is available at:
http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/
Signed-off-by: Kuninori Morimoto <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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Signed-off-by: Paul Mundt <[email protected]>
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This patch implements pinmux tables for the sh7785 processor.
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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These accidentally got placed in to cpu-sh4 instead of cpu-sh4/cpu, push
them down one more level.
Signed-off-by: Paul Mundt <[email protected]>
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Signed-off-by: Paul Mundt <[email protected]>
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This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac.
Most of the moving about was done with Sam's directions at:
http://marc.info/?l=linux-sh&m=121724823706062&w=2
with subsequent hacking and fixups entirely my fault.
Signed-off-by: Sam Ravnborg <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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