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2023-12-29RISC-V: KVM: add 'vlenb' Vector CSRDaniel Henrique Barboza1-0/+15
Userspace requires 'vlenb' to be able to encode it in reg ID. Otherwise it is not possible to retrieve any vector reg since we're returning EINVAL if reg_size isn't vlenb (see kvm_riscv_vcpu_vreg_addr()). Signed-off-by: Daniel Henrique Barboza <[email protected]> Reviewed-by: Anup Patel <[email protected]> Signed-off-by: Anup Patel <[email protected]>
2023-12-29RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context()Daniel Henrique Barboza1-0/+1
'vlenb', added to riscv_v_ext_state by commit c35f3aa34509 ("RISC-V: vector: export VLENB csr in __sc_riscv_v_state"), isn't being initialized in guest_context. If we export 'vlenb' as a KVM CSR, something we want to do in the next patch, it'll always return 0. Set 'vlenb' to riscv_v_size/32. Signed-off-by: Daniel Henrique Barboza <[email protected]> Reviewed-by: Anup Patel <[email protected]> Signed-off-by: Anup Patel <[email protected]>
2023-11-09riscv: Rearrange hwcap.h and cpufeature.hXiao Wang1-1/+1
Now hwcap.h and cpufeature.h are mutually including each other, and most of the variable/API declarations in hwcap.h are implemented in cpufeature.c, so, it's better to move them into cpufeature.h and leave only macros for ISA extension logical IDs in hwcap.h. BTW, the riscv_isa_extension_mask macro is not used now, so this patch removes it. Suggested-by: Andrew Jones <[email protected]> Signed-off-by: Xiao Wang <[email protected]> Reviewed-by: Andrew Jones <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
2023-08-08RISC-V: KVM: Improve vector save/restore functionsAndrew Jones1-27/+19
Make two nonfunctional changes to the vector get/set vector reg functions and their supporting function for simplification and readability. The first is to not pass KVM_REG_RISCV_VECTOR, but rather integrate it directly into the masking. The second is to rename reg_val to reg_addr where and address is used instead of a value. Also opportunistically touch up some of the code formatting for a third nonfunctional change. Signed-off-by: Andrew Jones <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Signed-off-by: Anup Patel <[email protected]>
2023-08-08RISC-V: KVM: Improve vector save/restore errorsAndrew Jones1-27/+33
kvm_riscv_vcpu_(get/set)_reg_vector() now returns ENOENT if V is not available, EINVAL if reg type is not of VECTOR type, and any error that might be thrown by kvm_riscv_vcpu_vreg_addr(). Signed-off-by: Andrew Jones <[email protected]> Signed-off-by: Anup Patel <[email protected]>
2023-06-08riscv: KVM: Add vector lazy save/restore supportVincent Chen1-0/+186
This patch adds vector context save/restore for guest VCPUs. To reduce the impact on KVM performance, the implementation imitates the FP context switch mechanism to lazily store and restore the vector context only when the kernel enters/exits the in-kernel run loop and not during the KVM world switch. Signed-off-by: Vincent Chen <[email protected]> Signed-off-by: Greentime Hu <[email protected]> Signed-off-by: Andy Chiu <[email protected]> Reviewed-by: Anup Patel <[email protected]> Acked-by: Anup Patel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
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