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2015-03-17powerpc/book3s: Fix flush_tlb cpu_spec hook to take a generic argument.Mahesh Salgaonkar1-2/+2
The flush_tlb hook in cpu_spec was introduced as a generic function hook to invalidate TLBs. But the current implementation of flush_tlb hook takes IS (invalidation selector) as an argument which is architecture dependent. Hence, It is not right to have a generic routine where caller has to pass non-generic argument. This patch fixes this and makes flush_tlb hook as high level API. Reported-by: Benjamin Herrenschmidt <[email protected]> Signed-off-by: Mahesh Salgaonkar <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2015-01-29powerpc: Add machine_check cpu function for e300c3 cpusEsben Haabendal1-0/+1
Signed-off-by: Esben Haabendal <[email protected]> Signed-off-by: Scott Wood <[email protected]>
2014-09-22powerpc/booke: Restrict SPE exception handlers to e200/e500 coresMihai Caraman1-0/+5
SPE exception handlers are now defined for 32-bit e500mc cores even though SPE unit is not present and CONFIG_SPE is undefined. Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE and consequently guard __stup_ivors and __setup_cpu functions. Signed-off-by: Mihai Caraman <[email protected]> Acked-by: Scott Wood <[email protected]> Signed-off-by: Alexander Graf <[email protected]>
2014-07-28powerpc: Remove CLASSIC_PPCMichael Ellerman1-2/+2
We have a strange #define in cputable.h called CLASSIC_PPC. Although it is defined for 32 & 64bit, it's only used for 32bit and it's basically a duplicate of CONFIG_PPC_BOOK3S_32, so let's use the latter. Signed-off-by: Michael Ellerman <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2014-07-28powerpc: Drop support for pre-POWER4 cpusMichael Ellerman1-90/+0
We inadvertently broke power3 support back in 3.4 with commit f5339277eb8d "powerpc: Remove FW_FEATURE ISERIES from arch code". No one noticed until at least 3.9. By then we'd also broken it with the optimised memcpy, copy_to/from_user and clear_user routines. We don't want to add any more complexity to those just to support ancient cpus, so it seems like it's a good time to drop support for power3 and earlier. Signed-off-by: Michael Ellerman <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2014-07-22powerpc: Disable doorbells on Power8 DD1.xJoel Stanley1-0/+20
These processors do not currently support doorbell IPIs, so remove them from the feature list if we are at DD 1.xx for the 0x004d part. This fixes a regression caused by d4e58e5928f8 (powerpc/powernv: Enable POWER8 doorbell IPIs). With that patch the kernel would hang at boot when calling smp_call_function_many, as the doorbell would not be received by the target CPUs: .smp_call_function_many+0x2bc/0x3c0 (unreliable) .on_each_cpu_mask+0x30/0x100 .cpuidle_register_driver+0x158/0x1a0 .cpuidle_register+0x2c/0x110 .powernv_processor_idle_init+0x23c/0x2c0 .do_one_initcall+0xd4/0x260 .kernel_init_freeable+0x25c/0x33c .kernel_init+0x1c/0x120 .ret_from_kernel_thread+0x58/0x7c Fixes: d4e58e5928f8 (powerpc/powernv: Enable POWER8 doorbell IPIs) Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2014-06-11powerpc: Remove platforms/wsp and associated piecesMichael Ellerman1-38/+0
__attribute__ ((unused)) WSP is the last user of CONFIG_PPC_A2, so we remove that as well. Although CONFIG_PPC_ICSWX still exists, it's no longer selectable for any Book3E platform, so we can remove the code in mmu-book3e.h that depended on it. Signed-off-by: Michael Ellerman <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2014-06-11powerpc: Add AT_HWCAP2 to indicate V.CRYPTO category supportBenjamin Herrenschmidt1-1/+2
The Vector Crypto category instructions are supported by current POWER8 chips, advertise them to userspace using a specific bit to properly differentiate with chips of the same architecture level that might not have them. Signed-off-by: Benjamin Herrenschmidt <[email protected]> CC: <[email protected]> [v3.10+]
2014-03-24powerpc: Add a cpu feature CPU_FTR_PMAO_BUGMichael Ellerman1-1/+1
Some power8 revisions have a hardware bug where we can lose a Performance Monitor (PMU) exception under certain circumstances. We will be adding a workaround for this case, see the next commit for details. The observed behaviour is that writing PMAO doesn't cause an exception as we would expect, hence the name of the feature. Signed-off-by: Michael Ellerman <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2013-12-05powerpc/book3s: Flush SLB/TLBs if we get SLB/TLB machine check errors on power8.Mahesh Salgaonkar1-0/+4
This patch handles the memory errors on power8. If we get a machine check exception due to SLB or TLB errors, then flush SLBs/TLBs and reload SLBs to recover. Signed-off-by: Mahesh Salgaonkar <[email protected]> Acked-by: Paul Mackerras <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2013-12-05powerpc/book3s: Flush SLB/TLBs if we get SLB/TLB machine check errors on power7.Mahesh Salgaonkar1-0/+4
If we get a machine check exception due to SLB or TLB errors, then flush SLBs/TLBs and reload SLBs to recover. We do this in real mode before turning on MMU. Otherwise we would run into nested machine checks. If we get a machine check when we are in guest, then just flush the SLBs and continue. This patch handles errors for power7. The next patch will handle errors for power8 Signed-off-by: Mahesh Salgaonkar <[email protected]> Signed-off-by: Paul Mackerras <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2013-12-05powerpc/book3s: Add flush_tlb operation in cpu_spec.Mahesh Salgaonkar1-0/+8
This patch introduces flush_tlb operation in cpu_spec structure. This will help us to invoke appropriate CPU-side flush tlb routine. This patch adds the foundation to invoke CPU specific flush routine for respective architectures. Currently this patch introduce flush_tlb for p7 and p8. Signed-off-by: Mahesh Salgaonkar <[email protected]> Acked-by: Paul Mackerras <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2013-08-09Merge remote-tracking branch 'scott/next' into nextBenjamin Herrenschmidt1-1/+1
Merge some Freescale updates from Scott Wood
2013-08-07powerpc/perf: add 2 additional performance monitor counters for e6500 coreLijun Pan1-1/+1
There are 6 counters in e6500 core instead of 4 in e500 core. Signed-off-by: Lijun Pan <[email protected]> Signed-off-by: Scott Wood <[email protected]>
2013-07-24powerpc: Add second POWER8 PVR entryMichael Neuling1-1/+19
POWER8 comes with two different PVRs. This patch enables the additional PVR in the cputable. The existing entry (PVR=0x4b) is renamed to POWER8E and the new entry (PVR=0x4d) is given POWER8. Signed-off-by: Michael Neuling <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2013-06-10powerpc/power8: Fix oprofile and perfMichael Neuling1-4/+4
In 2ac6f42 powerpc/cputable: Fix oprofile_cpu_type on power8 we broke all power8 hw events. This reverts this change and uses oprofile_type instead. Perf now works on POWER8 again and oprofile will revert to using timers on POWER8. Kudos to mpe this fix. Signed-off-by: Michael Neuling <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2013-06-01powerpc/cputable: Fix typo on P7+ cputable entryWill Schmidt1-1/+1
Fix a typo in setting COMMON_USER2_POWER7 bits to .cpu_user_features2 cpu specs table. Signed-off-by: Will Schmidt <[email protected]> Acked-by: Michael Neuling <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2013-06-01powerpc/cputable: Fix oprofile_cpu_type on power8Nishanth Aravamudan1-2/+2
Maynard informed me that neither the oprofile kernel module nor oprofile userspace has been updated to support that "legacy" oprofile module interface for power8, which is indicated by "ppc64/power8." This results in no samples. The solution is to default to the "timer" type, instead. The raw entry also should be updated, as "ppc64/ibm-compat-v1" indicates to oprofile userspace to use "compatibility events" which are obsolete in ISA 2.07. Signed-off-by: Nishanth Aravamudan <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2013-05-06powerpc/cputable: Advertise support for ISEL/HTM/DSCR/TAR on POWER8Nishanth Aravamudan1-0/+5
Signed-off-by: Nishanth Aravamudan <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2013-05-06powerpc/cputable: Advertise ISEL support on appropriate embedded processorsNishanth Aravamudan1-0/+5
Signed-off-by: Nishanth Aravamudan <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2013-05-06powerpc/cputable: Advertise DSCR support on P7/P7+Nishanth Aravamudan1-0/+4
Signed-off-by: Nishanth Aravamudan <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2013-04-30Merge remote-tracking branch 'kumar/next' into nextBenjamin Herrenschmidt1-3/+6
From Kumar Gala: << Add support for T4 and B4 SoC families from Freescale, e6500 altivec support, some various board fixes and other minor cleanups. >>
2013-03-13powerpc: Fix cputable entry for 970MP rev 1.0Benjamin Herrenschmidt1-1/+1
Commit 44ae3ab3358e962039c36ad4ae461ae9fb29596c forgot to update the entry for the 970MP rev 1.0 processor when moving some CPU features bits to the MMU feature bit mask. This breaks booting on some rare G5 models using that chip revision. Reported-by: Phileas Fogg <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]> CC: <[email protected]> [v3.0+]
2013-03-12powerpc/85xx: Add AltiVec support for e6500Kumar Gala1-3/+6
The e6500 core adds support for AltiVec on a Book-E class processor. Connect up all the various exception handling code and build config mechanisms to allow user spaces apps to utilize AltiVec. Signed-off-by: Kumar Gala <[email protected]>
2012-11-15powerpc: Add POWER8 architected mode to cputableMichael Neuling1-0/+15
A PVR of 0x0F000004 means we are arch v2.07 complicate ie, POWER8. Signed-off-by: Michael Neuling <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2012-11-15powerpc: POWER8 cputable entryMichael Neuling1-0/+21
Signed-off-by: Michael Neuling <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2012-11-15powerpc: Add POWER8 setup codeMichael Neuling1-0/+2
Just a copy of POWER7 for now. Will update with new code later. Signed-off-by: Michael Neuling <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2012-09-12powerpc/booke: Merge the 32 bit e5500/e500mc cpu setup code.Varun Sethi1-0/+4
Merge the 32 bit cpu setup code for e500mc/e5500 and define the "cpu_restore" routine (for e5500/e6500) only for the 64 bit case. The cpu_restore routine is used in the 64 bit case for setting up the secondary cores. Signed-off-by: Varun Sethi <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2012-03-28Disintegrate asm/system.h for PowerPCDavid Howells1-0/+1
Disintegrate asm/system.h for PowerPC. Signed-off-by: David Howells <[email protected]> Acked-by: Benjamin Herrenschmidt <[email protected]> cc: [email protected]
2012-03-21Merge remote-tracking branch 'kumar/next' into nextBenjamin Herrenschmidt1-0/+18
2012-03-17powerpc/44x: The bug fixed support for APM821xx SoC and Bluestone boardVinh Nguyen Huu Tuong1-1/+1
This patch consists of: - Fix the pvr mask for checking pvr in cputable.c - Fix the cpu name as consistent with cpu name is describled in dts file Signed-off-by: Vinh Nguyen Huu Tuong <[email protected]> Signed-off-by: Josh Boyer <[email protected]>
2012-03-15powerpc: Add initial e6500 cpu supportKumar Gala1-0/+18
Add basic support for e6500 core in its single threaded mode. Signed-off-by: Kumar Gala <[email protected]>
2011-12-09powerpc/476fpe: Add 476fpe SoC codeTony Breeds1-0/+14
Based on original work by David 'Shaggy' Kleikamp. Signed-off-by: Tony Breeds <[email protected]> Signed-off-by: Josh Boyer <[email protected]>
2011-11-30powerpc/40x: Add APM8018X SOC supportTanmay Inamdar1-0/+13
The AppliedMicro APM8018X embedded processor targets embedded applications that require low power and a small footprint. It features a PowerPC 405 processor core built in a 65nm low-power CMOS process with a five-stage pipeline executing up to one instruction per cycle. The family has 128-kbytes of on-chip memory, a 128-bit local bus and on-chip DDR2 SDRAM controller with 16-bit interface. Signed-off-by: Tanmay Inamdar <[email protected]> Signed-off-by: Josh Boyer <[email protected]>
2011-10-31powerpc: various straight conversions from module.h --> export.hPaul Gortmaker1-1/+1
All these files were including module.h just for the basic EXPORT_SYMBOL infrastructure. We can shift them off to the export.h header which is a way smaller footprint and thus realize some compile time gains. Signed-off-by: Paul Gortmaker <[email protected]>
2011-08-05powerpc: Return the_cpu_ spec from identify_cpuScott Wood1-5/+6
Commit af9eef3c7b1ed004c378c89b87642f4937337d50 caused cpu_setup to see the_cpu_spec, rather than the source struct. However, on 32-bit, the return value of identify_cpu was being used for feature fixups, and identify_cpu was returning the source struct. So if cpu_setup patches the feature bits, the update won't affect the fixups. Signed-off-by: Scott Wood <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2011-06-02powerpc/book3e: Fix CPU feature handling on e5500 in 32-bit modeKumar Gala1-1/+1
We are missing FPU feature bit that user space may require. In the 64-bit mode this gets set since we pull it in via COMMON_USER_PPC64. We just explicitly set it so user space will be happy again. Signed-off-by: Kumar Gala <[email protected]>
2011-04-27powerpc: Free up some CPU feature bits by moving out MMU-related featuresMatt Evans1-26/+19
Some of the 64bit PPC CPU features are MMU-related, so this patch moves them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to mmu_has_feature(), and seven feature bits are freed as a result. Signed-off-by: Matt Evans <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2011-04-27powerpc: Add A2 cpu supportBenjamin Herrenschmidt1-2/+23
Add the cputable entry, regs and setup & restore entries for the PowerPC A2 core. Signed-off-by: Benjamin Herrenschmidt <[email protected]> Signed-off-by: Michael Ellerman <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2011-04-20powerpc: Define CPU feature for Architected 2.06 HV modeBenjamin Herrenschmidt1-0/+6
This bit indicates that we are operating in hypervisor mode on a CPU compliant to architecture 2.06 or later (currently server only). We set it on POWER7 and have a boot-time CPU setup function that clears it if MSR:HV isn't set (booting under a hypervisor). Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2011-04-12powerpc/book3e: Fix CPU feature handling on 64-bit e5500Kumar Gala1-1/+1
The CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS defines did not encompass e5500 CPU features when built for 64-bit. This causes issues with cpu_has_feature() as it utilizes the POSSIBLE & ALWAYS defines as part of its check. Create a unique CPU_FTRS_E5500 (as its different from CPU_FTRS_E500MC), created a new group for 64-bit Book3e based CPUs and add CPU_FTRS_E5500 to that group. Signed-off-by: Kumar Gala <[email protected]>
2011-03-17Merge remote branch 'jwb/next' into nextBenjamin Herrenschmidt1-4/+18
2011-02-07powerpc: Pass the right cpu_spec to ->setup_cpu() on 64-bitBenjamin Herrenschmidt1-2/+2
When calling setup_cpu() on 64-bit, we pass a pointer to the cputable entry we have found. This used to be fine when cur_cpu_spec was a pointer to that entry, but nowadays, we copy the entry into a separate variable, and we do so before we call the setup_cpu() callback. That means that any attempt by that callback at patching the CPU table entry (to adjust CPU features for example) will patch the wrong table. Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2011-02-02powerpc/476: define specific cpu table entry DD2 coreDave Kleikamp1-4/+18
The DD2 core still has some unstability. Define CPU_FTR_476_DD2 to enable workarounds in later patches. This is based on an earlier, unreleased patch for DD1 by Ben Herrenschmidt. Signed-off-by: Dave Kleikamp <[email protected]> Signed-off-by: Josh Boyer <[email protected]>
2011-01-21powerpc: machine_check_generic is wrong on 64bitAnton Blanchard1-23/+0
Decoding machine checks is CPU specific and so machine_check_generic doesn't do the right thing on 64bit chips. Luckily we never call into this code because we call ppc_md.machine_check_exception instead if available. Since we check cur_cpu_spec->machine_check before calling it, we may as well remove machine_check_generic from 64bit archs. Signed-off-by: Anton Blanchard <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2010-11-29powerpc: Add POWER7+ cputable entryMichael Neuling1-0/+16
This adds the POWER7+ cputable entry for the PVR 0x004a0000. Rest is the same as vanilla POWER7. Signed-off-by: Michael Neuling <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2010-11-29powerpc: Remove POWER6 oprofile workarounds for POWER7Michael Neuling1-4/+0
These are not needed on POWER7 so remove them. Signed-off-by: Michael Neuling <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2010-11-29powerpc: Remove unneeded cpu_setup/restore from POWER7 cputable entryMichael Neuling1-2/+0
These are not needed so just remove them Signed-off-by: Michael Neuling <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2010-10-15Merge remote branch 'jwb/next' into nextBenjamin Herrenschmidt1-0/+15
2010-10-14powerpc/fsl-booke: Add support for FSL 64-bit e5500 coreKumar Gala1-1/+27
The new e5500 core is similar to the e500mc core but adds 64-bit support. We support running it in 32-bit mode as it is identical to the e500mc. Signed-off-by: Kumar Gala <[email protected]>
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