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2024-03-07mips: mt: make mt_class constantRicardo B. Marliere3-15/+9
Since commit 43a7206b0963 ("driver core: class: make class_register() take a const *"), the driver core allows for struct class to be in read-only memory, so move the mt_class structure to be declared at build time placing it into read-only memory, instead of having to be dynamically allocated at boot time. Cc: Greg Kroah-Hartman <[email protected]> Suggested-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Ricardo B. Marliere <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-03-07MIPS: ralink: Remove unused of_gpio.hAndy Shevchenko1-1/+0
of_gpio.h is deprecated and subject to remove. The driver doesn't use it, simply remove the unused header. Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-03-06arch: consolidate existing CONFIG_PAGE_SIZE_*KB definitionsArnd Bergmann2-68/+6
These four architectures define the same Kconfig symbols for configuring the page size. Move the logic into a common place where it can be shared with all other architectures. Reviewed-by: Thomas Gleixner <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
2024-02-28MIPS: mipsregs: Parse fp and sp register by name in parse_rJiaxun Yang1-2/+5
parse_r helper is used to parse register number from oprand, it only handles oprand which use number to refer register before. However compiler may use $gp and $sp to reference register 29 and 30. Handle this situation by adding relevant match name. Fixes compilation error: {standard input}: Assembler messages: {standard input}:1937: Error: Unable to parse register name $fp Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-23mips, crash: wrap crash dumping code into crash related ifdefsBaoquan He1-11/+6
Now crash codes under kernel/ folder has been split out from kexec code, crash dumping can be separated from kexec reboot in config items on mips with some adjustments. Here use IS_ENABLED(CONFIG_CRASH_RESERVE) check to decide if compiling in the crashkernel reservation code. Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Baoquan He <[email protected]> Cc: Al Viro <[email protected]> Cc: Eric W. Biederman <[email protected]> Cc: Hari Bathini <[email protected]> Cc: Pingfan Liu <[email protected]> Cc: Klara Modin <[email protected]> Cc: Michael Kelley <[email protected]> Cc: Nathan Chancellor <[email protected]> Cc: Stephen Rothwell <[email protected]> Cc: Yang Li <[email protected]> Signed-off-by: Andrew Morton <[email protected]>
2024-02-23mips: zboot: Fix "no previous prototype" build warningSerge Semin3-0/+6
Without having the putc() prototype forwardly declared the next build-warning is printed: arch/mips/boot/compressed/uart-prom.c:6:6: warning: no previous prototype for ‘putc’ [-Wmissing-prototypes] ... Fix that by adding the "decompress.h" header file with the putc() function declaration to the source files which have the method redefined. Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-23MIPS: mipsregs: Set proper ISA level for virt extensionsJiaxun Yang1-5/+8
c994a3ec7ecc ("MIPS: set mips32r5 for virt extensions") setted some instructions in virt extensions to ISA level mips32r5. However TLB related vz instructions was leftover, also this shouldn't be done to a R5 or R6 kernel buid. Reorg macros to set ISA level as needed when _ASM_SET_VIRT is called. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-23MIPS: Implement microMIPS MT ASE helpersJiaxun Yang4-112/+179
Implement various microMIPS MT ASE helpers accroading to: MIPS® Architecture for Programmers Volume IV-f: The MIPS® MT Module for the microMIPS32™ Architecture Fixes build error: {standard input}:2616: Error: branch to a symbol in another ISA mode This make MT ASE available on microMIPS as well. Boot tested on M5150 with microMIPS enabled on M5150. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-23MIPS: Limit MIPS_MT_SMP support by ISA reversionJiaxun Yang1-1/+2
MIPS MT ASE is only available on ISA between Release 1 and Release 5. Add ISA level dependency to Kconfig to fix build. Reported-by: Guenter Roeck <[email protected]> Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-23MIPS: Loongson64: test for -march=loongson3a cflagJiaxun Yang1-5/+2
Currently march flag is hardcoded to loongson3a for GCC and mips64r2 for clang. We can actually test it to simplify the code. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-23MIPS: BMIPS: Drop unnecessary assembler flagJiaxun Yang1-2/+2
Nowadays GCC will always pass -march flag to gas, so there is no need to pass another mips32 flag to assembler. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-23MIPS: Fallback CPU -march flag to ISA level if unsupportedJiaxun Yang1-13/+17
LLVM does not implement some of -march options. However those options are not mandatory for kernel to build for those CPUs. Fallback -march CFLAG to ISA level if unsupported by toolchain so we can get those kernel to build with LLVM. Link: https://github.com/ClangBuiltLinux/linux/issues/1544 Reported-by: Nathan Chancellor <[email protected]> Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-23MIPS: Remove cc-option checks for -march=octeonJiaxun Yang1-4/+1
Nowadays our minimal supported GCC/Clang all support -march=octeon. Remove cc-option checks to simplify code. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-23MIPS: Probe toolchain support of -msym32Jiaxun Yang1-1/+1
msym32 is not supported by LLVM toolchain. Workaround by probe toolchain support of msym32 for KBUILD_SYM32 feature. Link: https://github.com/ClangBuiltLinux/linux/issues/1544 Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-22Introduce cpu_dcache_is_aliasing() across all architecturesMathieu Desnoyers2-0/+10
Introduce a generic way to query whether the data cache is virtually aliased on all architectures. Its purpose is to ensure that subsystems which are incompatible with virtually aliased data caches (e.g. FS_DAX) can reliably query this. For data cache aliasing, there are three scenarios dependending on the architecture. Here is a breakdown based on my understanding: A) The data cache is always aliasing: * arc * csky * m68k (note: shared memory mappings are incoherent ? SHMLBA is missing there.) * sh * parisc B) The data cache aliasing is statically known or depends on querying CPU state at runtime: * arm (cache_is_vivt() || cache_is_vipt_aliasing()) * mips (cpu_has_dc_aliases) * nios2 (NIOS2_DCACHE_SIZE > PAGE_SIZE) * sparc32 (vac_cache_size > PAGE_SIZE) * sparc64 (L1DCACHE_SIZE > PAGE_SIZE) * xtensa (DCACHE_WAY_SIZE > PAGE_SIZE) C) The data cache is never aliasing: * alpha * arm64 (aarch64) * hexagon * loongarch (but with incoherent write buffers, which are disabled since commit d23b7795 ("LoongArch: Change SHMLBA from SZ_64K to PAGE_SIZE")) * microblaze * openrisc * powerpc * riscv * s390 * um * x86 Require architectures in A) and B) to select ARCH_HAS_CPU_CACHE_ALIASING and implement "cpu_dcache_is_aliasing()". Architectures in C) don't select ARCH_HAS_CPU_CACHE_ALIASING, and thus cpu_dcache_is_aliasing() simply evaluates to "false". Note that this leaves "cpu_icache_is_aliasing()" to be implemented as future work. This would be useful to gate features like XIP on architectures which have aliasing CPU dcache-icache but not CPU dcache-dcache. Use "cpu_dcache" and "cpu_cache" rather than just "dcache" and "cache" to clarify that we really mean "CPU data cache" and "CPU cache" to eliminate any possible confusion with VFS "dentry cache" and "page cache". Link: https://lore.kernel.org/lkml/[email protected]/ Link: https://lkml.kernel.org/r/[email protected] Fixes: d92576f1167c ("dax: does not work correctly with virtual aliasing caches") Signed-off-by: Mathieu Desnoyers <[email protected]> Cc: Dan Williams <[email protected]> Cc: Vishal Verma <[email protected]> Cc: Dave Jiang <[email protected]> Cc: Matthew Wilcox <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: Russell King <[email protected]> Cc: Alasdair Kergon <[email protected]> Cc: Christoph Hellwig <[email protected]> Cc: Dave Chinner <[email protected]> Cc: Heiko Carstens <[email protected]> Cc: kernel test robot <[email protected]> Cc: Michael Sclafani <[email protected]> Cc: Mike Snitzer <[email protected]> Cc: Mikulas Patocka <[email protected]> Signed-off-by: Andrew Morton <[email protected]>
2024-02-20MIPS: vdso: Use generic union vdso_data_storeAnna-Maria Behnsen2-6/+1
There is already a generic union definition for vdso_data_store in the vdso datapage header. Use this definition to prevent code duplication. Signed-off-by: Anna-Maria Behnsen <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Vincenzo Frascino <[email protected]> Reviewed-by: Kees Cook <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-02-20MIPS: TXx9: Use PCI_SET_ERROR_RESPONSE()Ilpo Järvinen1-1/+1
Instead of literal, PCI error value should be set with PCI_SET_ERROR_RESPONSE(). Use it in tx4927_pci_config_read(). Signed-off-by: Ilpo Järvinen <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: PCI: Return PCIBIOS_* from tx4927_pci_config_read/write()Ilpo Järvinen1-6/+10
pci_ops .read/.write must return PCIBIOS_* codes but tx4927_pci_config_read/write() return -1 when mkaddr() cannot find devfn from the root bus. Return PCIBIOS_DEVICE_NOT_FOUND instead and pass that onward in the call chain instead of overwriting the return value. Also converts 0 -> PCIBIOS_SUCCESSFUL which has only cosmetic impact. Signed-off-by: Ilpo Järvinen <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: ath79: Don't return PCIBIOS_* code from pcibios_enable_device()Ilpo Järvinen1-1/+1
pcibios_plat_dev_init() is called from pcibios_enable_device() that should return normal errnos, not PCIBIOS return codes. In this case the impact is only cosmetic because PCIBIOS_SUCCESSFUL equals 0 that is success code with errnos as well. Nonetheless, remove the inconsistency by replacing the PCIBIOS_SUCCESSFUL with 0. Signed-off-by: Ilpo Järvinen <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: lantiq: Remove unused function pointer variablesIlpo Järvinen1-9/+0
Ever since introduction in the commit e47d488935ed ("MIPS: Lantiq: Add PCI controller support.") ltqpci_plat_dev_init has been unused. In 57c8cb8f2429 ("MIPS: pci: convert lantiq driver to OF") also ltq_pci_plat_arch_init was introduced. With those commit being more than 10 years ago, it seem neither is going to get used anytime soon. Thus, remove both unused function pointer variables. Signed-off-by: Ilpo Järvinen <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20mips: bus: make mips_cdmm_bustype constRicardo B. Marliere1-1/+1
Now that the driver core can properly handle constant struct bus_type, move the mips_cdmm_bustype variable to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Cc: Greg Kroah-Hartman <[email protected]> Suggested-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Ricardo B. Marliere <[email protected]> Reviewed-by: Greg Kroah-Hartman <[email protected]> Tested-by: Serge Semin <[email protected]> Acked-by: Serge Semin <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20mips: txx9: make txx9_sramc_subsys constRicardo B. Marliere1-1/+1
Now that the driver core can properly handle constant struct bus_type, move the txx9_sramc_subsys variable to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Cc: Greg Kroah-Hartman <[email protected]> Suggested-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Ricardo B. Marliere <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20mips: sgi-ip22: make gio_bus_type constRicardo B. Marliere1-2/+2
Now that the driver core can properly handle constant struct bus_type, move the gio_bus_type variable to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Cc: Greg Kroah-Hartman <[email protected]> Suggested-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Ricardo B. Marliere <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: move unselectable entries out of the "CPU type" choiceMasahiro Yamada1-38/+38
Move the following entries out of the "CPU type" choice: - LOONGSON3_ENHANCEMENT - CPU_LOONGSON3_WORKAROUNDS - CPU_LOONGSON3_CPUCFG_EMULATION These entries cannot be selected from the choice because they depend on CPU_LOONGSON64, which is also located in the same choice. In fact, Kconfig does not consider them as choice values because they become children of CPU_LOOONGSON64 due to the automatic submenu creation in menu_finalize(). However, it is hard to understand this behavior unless you are familiar with the Kconfig internals. "choice" should contain only selectable entries. Signed-off-by: Masahiro Yamada <[email protected]> Reviewed-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: Alchemy: Use kcalloc() instead of kzalloc()Erick Archer1-1/+1
As noted in the "Deprecated Interfaces, Language Features, Attributes, and Conventions" documentation [1], size calculations (especially multiplication) should not be performed in memory allocator (or similar) function arguments due to the risk of them overflowing. This could lead to values wrapping around and a smaller allocation being made than the caller was expecting. Using those allocations could lead to linear overflows of heap memory and other misbehaviors. So, use the purpose specific kcalloc() function instead of the argument size * count in the kzalloc() function. Link: https://www.kernel.org/doc/html/next/process/deprecated.html#open-coded-arithmetic-in-allocator-arguments [1] Link: https://github.com/KSPP/linux/issues/162 Signed-off-by: Erick Archer <[email protected]> Reviewed-by: Gustavo A. R. Silva <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: Add support for Mobileye EyeQ5Gregory CLEMENT7-0/+234
Introduce support for the MIPS based Mobileye EyeQ5 SoCs. Reviewed-by: Jiaxun Yang <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: Share generic kernel code with other architectureGregory CLEMENT3-3/+10
Some architectures might seek to utilize a significant portion of the generic kernel code while maintaining independence from the generic kernel due to specific peculiarities. This patch allows for the reuse of core code, preventing unnecessary duplication. Suggested-by: Thomas Bogendoerfer <[email protected]> Reviewed-by: Jiaxun Yang <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: mobileye: Add EPM5 device treeGregory CLEMENT2-0/+27
Add a device tree for the Mobileye EPM5 evaluation board. Reviewed-by: Jiaxun Yang <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: mobileye: Add EyeQ5 dtsiGregory CLEMENT3-0/+417
Add a device tree include file for the Mobileye EyeQ5 SoC. Based on the work of Slava Samsonov <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: cps-vec: Use macros for 64bits accessGregory CLEMENT1-3/+3
Some access are 32 bits only while they seems better to be done in 64bis for 64 bit kernel. This was extract from an initial patch from Jiaxun Co-developed-by: Jiaxun Yang <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: traps: Give more explanations if ebase doesn't belong to KSEG0Gregory CLEMENT1-1/+4
With the expanded support for placing the kernel in XPHYS rather than just KSEG0, scenarios where ebase doesn't belong to KSEG0 are more likely to occur. In such cases, we currently experience a substantial and perplexing stack dump without any accompanying explanation. To rectify this, we aim to replace the uninformative stack dump with a warning that offers a clear explanation of the issue. Reviewed-by: Jiaxun Yang <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: Allows relocation exception vectors everywhereJiaxun Yang4-66/+133
Now the exception vector for CPS systems are allocated on-fly with memblock as well. It will try to allocate from KSEG1 first, and then try to allocate in low 4G if possible. The main reset vector is now generated by uasm, to avoid tons of patches to the code. Other vectors are copied to the location later. move 64bits fix in an other patch fix cache issue with mips_cps_core_entry rewrite the patch to reduce the diff stat move extern in header use cache address for copying vector gc: use the new macro CKSEG[0A1]DDR_OR_64BIT() Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: Fix set_uncached_handler for ebase in XKPHYSJiaxun Yang1-1/+1
ebase might reside in XKPHYS if memblock is unable to allocate memory within the KSEG0 physical range. To map EBASE into uncached space, we convert it back to its physical address and utilize the new CKSEG1ADDR_OR_64BIT helper for mapping. Co-developed-by: Vladimir Kondratiev <[email protected]> Signed-off-by: Vladimir Kondratiev <[email protected]> Co-developed-by: Gregory CLEMENT <[email protected]> Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: spaces: Define a couple of handy macrosGregory CLEMENT2-0/+9
Define CKSEGX_SIZE to represent the size of each KSEG segment. Introduce CKSEG0ADDR_OR_64BIT and CKSEG1ADDR_OR_64BIT to get an XPHYS address in 64bits and CKSEG[01]ADDR() in 32 bits mode. Co-developed-by: Jiaxun Yang <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: pm-cps: Use GPR number macrosJiaxun Yang1-70/+64
Use GPR number macros in uasm code generation parts to reduce code duplication. There are functional change due to difference in register symbolic names between OABI and NABI, while existing code is only using definitions from OABI. Code pieces are carefully inspected to ensure register usages are safe on NABI as well. We changed register allocation of r_pcohctl from T7 to T8 as T7 is not available on NABI and we just want a caller saved scratch register here. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: kvm/entry: Use GPR number macrosJiaxun Yang1-217/+187
Use GPR number macros in uasm code generation parts to reduce code duplication. No functional change. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: tlbex: Use GPR number macrosJiaxun Yang1-99/+97
Use GPR number macros in uasm code generation parts to reduce code duplication. No functional change. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: page: Use GPR number macrosJiaxun Yang1-107/+95
Use GPR number macros in uasm code generation parts to reduce code duplication. No functional change. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: traps: Use GPR number macrosJiaxun Yang1-3/+3
Use GPR number macros in uasm code generation parts to reduce code duplication. No functional change. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: regdefs.h: Define a set of register numbersJiaxun Yang1-0/+89
Define a set of register numbers with their symbolic names to help with uasm code. All names are prefixed by GPR_ to prevent naming clash. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: regdefs.h: Guard all defines with __ASSEMBLY__Jiaxun Yang1-0/+2
Those definitions are only meant to be used in pure assembly code. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-20MIPS: Unify define of CP0 registers for uasm codeJiaxun Yang3-94/+200
Definitions of uasm variant of CP0 registers are unified to mipsregs.h, so they lay together with uasm variant of the code. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-12MIPS: Clear Cause.BD in instruction_pointer_setJiaxun Yang1-0/+1
Clear Cause.BD after we use instruction_pointer_set to override EPC. This can prevent exception_epc check against instruction code at new return address. It won't be considered as "in delay slot" after epc being overridden anyway. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-12ptrace: Introduce exception_ip arch hookJiaxun Yang2-0/+9
On architectures with delay slot, architecture level instruction pointer (or program counter) in pt_regs may differ from where exception was triggered. Introduce exception_ip hook to invoke architecture code and determine actual instruction pointer to the exception. Link: https://lore.kernel.org/lkml/[email protected]/ Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-12MIPS: Add 'memory' clobber to csum_ipv6_magic() inline assemblerGuenter Roeck1-1/+2
After 'lib: checksum: Use aligned accesses for ip_fast_csum and csum_ipv6_magic tests' was applied, the test_csum_ipv6_magic unit test started failing for all mips platforms, both little and bit endian. Oddly enough, adding debug code into test_csum_ipv6_magic() made the problem disappear. The gcc manual says: "The "memory" clobber tells the compiler that the assembly code performs memory reads or writes to items other than those listed in the input and output operands (for example, accessing the memory pointed to by one of the input parameters) " This is definitely the case for csum_ipv6_magic(). Indeed, adding the 'memory' clobber fixes the problem. Cc: Charlie Jenkins <[email protected]> Cc: Palmer Dabbelt <[email protected]> Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Guenter Roeck <[email protected]> Reviewed-by: Charlie Jenkins <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2024-02-09work around gcc bugs with 'asm goto' with outputsLinus Torvalds1-2/+2
We've had issues with gcc and 'asm goto' before, and we created a 'asm_volatile_goto()' macro for that in the past: see commits 3f0116c3238a ("compiler/gcc4: Add quirk for 'asm goto' miscompilation bug") and a9f180345f53 ("compiler/gcc4: Make quirk for asm_volatile_goto() unconditional"). Then, much later, we ended up removing the workaround in commit 43c249ea0b1e ("compiler-gcc.h: remove ancient workaround for gcc PR 58670") because we no longer supported building the kernel with the affected gcc versions, but we left the macro uses around. Now, Sean Christopherson reports a new version of a very similar problem, which is fixed by re-applying that ancient workaround. But the problem in question is limited to only the 'asm goto with outputs' cases, so instead of re-introducing the old workaround as-is, let's rename and limit the workaround to just that much less common case. It looks like there are at least two separate issues that all hit in this area: (a) some versions of gcc don't mark the asm goto as 'volatile' when it has outputs: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98619 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110420 which is easy to work around by just adding the 'volatile' by hand. (b) Internal compiler errors: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110422 which are worked around by adding the extra empty 'asm' as a barrier, as in the original workaround. but the problem Sean sees may be a third thing since it involves bad code generation (not an ICE) even with the manually added 'volatile'. but the same old workaround works for this case, even if this feels a bit like voodoo programming and may only be hiding the issue. Reported-and-tested-by: Sean Christopherson <[email protected]> Link: https://lore.kernel.org/all/[email protected]/ Cc: Nick Desaulniers <[email protected]> Cc: Uros Bizjak <[email protected]> Cc: Jakub Jelinek <[email protected]> Cc: Andrew Pinski <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2024-02-08Merge branch 'kvm-kconfig'Paolo Bonzini2-10/+10
Cleanups to Kconfig definitions for KVM * replace HAVE_KVM with an architecture-dependent symbol, when CONFIG_KVM may or may not be available depending on CPU capabilities (MIPS) * replace HAVE_KVM with IS_ENABLED(CONFIG_KVM) for host-side code that is not part of the KVM module, so that it is completely compiled out * factor common "select" statements in common code instead of requiring each architecture to specify it
2024-02-08treewide: remove CONFIG_HAVE_KVMPaolo Bonzini1-9/+0
It has no users anymore. Signed-off-by: Paolo Bonzini <[email protected]>
2024-02-08MIPS: introduce Kconfig for MIPS VZPaolo Bonzini2-1/+10
Since MIPS/KVM only supports hardware virtualization using MIPS VZ, do not enable KVM blindly. Use a new Kconfig symbol CPU_SUPPORTS_VZ and do not enable it for R2 processors. Cc: Thomas Bogendoerfer <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2024-02-08kvm: replace __KVM_HAVE_READONLY_MEM with Kconfig symbolPaolo Bonzini2-2/+1
KVM uses __KVM_HAVE_* symbols in the architecture-dependent uapi/asm/kvm.h to mask unused definitions in include/uapi/linux/kvm.h. __KVM_HAVE_READONLY_MEM however was nothing but a misguided attempt to define KVM_CAP_READONLY_MEM only on architectures where KVM_CHECK_EXTENSION(KVM_CAP_READONLY_MEM) could possibly return nonzero. This however does not make sense, and it prevented userspace from supporting this architecture-independent feature without recompilation. Therefore, these days __KVM_HAVE_READONLY_MEM does not mask anything and is only used in virt/kvm/kvm_main.c. Userspace does not need to test it and there should be no need for it to exist. Remove it and replace it with a Kconfig symbol within Linux source code. Signed-off-by: Paolo Bonzini <[email protected]>
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