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2013-09-03MIPS: ath79: Use local variables for clock ratesGabor Juhos1-52/+106
Use local variables for ref, cpu, ddr and ahb rates in SoC specific clock init functions. The patch has no functional changes, it is an interim change in preparation of the next patch. Signed-off-by: Gabor Juhos <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5781/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: ath79: Use ath79_get_sys_clk_rate to get basic clock ratesGabor Juhos2-11/+12
Instead of accessing the rate field of the static clock devices directly, use the recently introduced helper function to get the rate of the basic clocks. The static ath79_{ahb,cpu,ddr,ref}_clk variables will be removed by a subsequent patch. The actual change is in preparation of that. Also move the clock frequency printing code into the plat_time_init function. We are getting the cpu clock rate there already so we can save an extra call of the helper. Signed-off-by: Gabor Juhos <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5782/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: ath79: Use a helper function to get system clock ratesGabor Juhos4-11/+25
The ath79 platform uses similar code to get the rate of various clocks during init. Separate the similar code into a new helper function and use that to avoid code duplication. Signed-off-by: Gabor Juhos <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5778/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: ath79: Use local ref clock rate in ar934x_get_pll_freqGabor Juhos1-2/+2
The reference clock rate is passed in the first argument of the function. Use that instead of the rate of the global ath79_ref_clk variable. Signed-off-by: Gabor Juhos <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5779/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: ath79: Fix ar933x watchdog clockFelix Fietkau1-1/+1
The watchdog device on the AR933x is connected to the AHB clock, however the current code uses the reference clock. Due to the wrong rate, the watchdog driver can't calculate correct register values for a given timeout value and the watchdog unexpectedly restarts the system. The code uses the wrong value since the initial commit 04225e1d227c8e68d685936ecf42ac175fec0e54 (MIPS: ath79: add AR933X specific clock init) The patch fixes the code to use the correct clock rate to avoid the problem. Cc: [email protected] Signed-off-by: Felix Fietkau <[email protected]> Signed-off-by: Gabor Juhos <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5777/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: ath79: Don't hardwire cpu_has_dsp{2} to 0Gabor Juhos1-2/+0
The ath79 code supports various SoCs which are using either a 24Kc or a 74Kc core. The 74Kc core has DSP support, so don't hardwire the values to zero. Commit 00dc5ce2a653a332190aa29b2e1f3bceaa7d5b8d (MIPS: ath79: don't hardcode the unavailability of the DSP ASE) has fixed this already, but that change got reverted by 475032564ed96c94c085e3e7a90e07d150a7cec9 (MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.) Reported-by: Helmut Schaa <[email protected]> Signed-off-by: Gabor Juhos <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5750/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: Lantiq: Add defconfig for xway SoCJohn Crispin1-0/+159
This add a default config for the Lantiq XWAY SoC. Signed-off-by: John Crispin <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5796/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: Lantiq: Falcon: fix asc clock definitionThomas Langer1-1/+4
The clocks of the serial ports were not setup properly. Signed-off-by: Thomas Langer <[email protected]> Acked-by: John Crispin <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5659/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: Lantiq: Falcon: add cpu-feature-override.hThomas Langer1-0/+58
Add cpu-feature-override.h for the GPON SoC Signed-off-by: Thomas Langer <[email protected]> Acked-by: John Crispin <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5658/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: Lantiq: Adds minimal dcdc driverJohn Crispin2-1/+64
This driver so far only reads the core voltage. Signed-off-by: John Crispin <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5677/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03Merge tag 'tty-3.12-rc1' of ↵Linus Torvalds1-1/+0
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty Pull tty/serial driver patches from Greg KH: "Here's the big tty/serial driver pull request for 3.12-rc1. Lots of n_tty reworks to resolve some very long-standing issues, removing the 3-4 different locks that were taken for every character. This code has been beaten on for a long time in linux-next with no reported regressions. Other than that, a range of serial and tty driver updates and revisions. Full details in the shortlog" * tag 'tty-3.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (226 commits) hvc_xen: Remove unnecessary __GFP_ZERO from kzalloc serial: imx: initialize the local variable tty: ar933x_uart: add device tree support and binding documentation tty: ar933x_uart: allow to build the driver as a module ARM: dts: msm: Update uartdm compatible strings devicetree: serial: Document msm_serial bindings serial: unify serial bindings into a single dir serial: fsl-imx-uart: Cleanup duplicate device tree binding tty: ar933x_uart: use config_enabled() macro to clean up ifdefs tty: ar933x_uart: remove superfluous assignment of ar933x_uart_driver.nr tty: ar933x_uart: use the clk API to get the uart clock tty: serial: cpm_uart: Adding proper request of GPIO used by cpm_uart driver serial: sirf: fix the amount of serial ports serial: sirf: define macro for some magic numbers of USP serial: icom: move array overflow checks earlier TTY: amiserial, remove unnecessary platform_set_drvdata() serial: st-asc: remove unnecessary platform_set_drvdata() msm_serial: Send more than 1 character on the console w/ UARTDM msm_serial: Add support for non-GSBI UARTDM devices msm_serial: Switch clock consumer strings and simplify code ...
2013-09-03Merge tag 'driver-core-3.12-rc1' of ↵Linus Torvalds2-10/+13
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core patches from Greg KH: "Here's the big driver core pull request for 3.12-rc1. Lots of tiny changes here fixing up the way sysfs attributes are created, to try to make drivers simpler, and fix a whole class race conditions with creations of device attributes after the device was announced to userspace. All the various pieces are acked by the different subsystem maintainers" * tag 'driver-core-3.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (119 commits) firmware loader: fix pending_fw_head list corruption drivers/base/memory.c: introduce help macro to_memory_block dynamic debug: line queries failing due to uninitialized local variable sysfs: sysfs_create_groups returns a value. debugfs: provide debugfs_create_x64() when disabled rbd: convert bus code to use bus_groups firmware: dcdbas: use binary attribute groups sysfs: add sysfs_create/remove_groups for when SYSFS is not enabled driver core: add #include <linux/sysfs.h> to core files. HID: convert bus code to use dev_groups Input: serio: convert bus code to use drv_groups Input: gameport: convert bus code to use drv_groups driver core: firmware: use __ATTR_RW() driver core: core: use DEVICE_ATTR_RO driver core: bus: use DRIVER_ATTR_WO() driver core: create write-only attribute macros for devices and drivers sysfs: create __ATTR_WO() driver-core: platform: convert bus code to use dev_groups workqueue: convert bus code to use dev_groups MEI: convert bus code to use dev_groups ...
2013-09-03MIPS: Move declaration of Octeon function fixup_irqs() to header.Ralf Baechle3-4/+4
Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: Add uImage build targetJames Hogan3-0/+22
Add a uImage build target for MIPS, which builds uImage.gz (a U-Boot image of vmlinux.bin.gz), and then symlinks it to uImage. This allows for the use of other compression algorithms in future, and is how a few other architectures do it. It's enabled conditionally on load-y >= 0xffffffff80000000 which hopefully allows 64bit kernels to also work as long as the load and entry address can be represented by the 32bit addresses in the U-Boot image format. Signed-off-by: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5795/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: Refactor load/entry address calculationsJames Hogan3-8/+13
The vmlinux load address and entry address is calculated in multiple places: - arch/mips/Makefile defines load-y from CONFIG_PHYSICAL_START (or defined by the platform) and passes it to arch/mips/boot/compressed/Makefile. - arch/mips/boot/compressed/Makefile calculates kernel entry using nm. - arch/mips/lasat/image/Makefile calculates both load and entry address using nm. Lets combine these in the main Makefile and then pass them as Make parameters to each of the three boot image Makefiles (in boot/, boot/compressed, lasat/image/). The boot/ Makefile doesn't currently use them, but will soon need to for U-Boot image targets. The existing load-y definition is used in preference to calculating the load address using nm. Signed-off-by: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5794/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: Refactor boot and boot/compressed rulesJames Hogan1-2/+13
Split out the arch/mips/boot/ and arch/mips/boot/compressed/ targets into boot-y and bootz-y variables. This makes it slightly cleaner to add new targets. Signed-off-by: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5793/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: add <dt-bindings/> symlinkJames Hogan1-0/+1
Add symlink to include/dt-bindings from arch/mips/boot/dts/include/ to match the ones in ARM and Meta architectures so that preprocessed device tree files can include various useful constant definitions. See commit c58299a (kbuild: create an "include chroot" for DT bindings) merged in v3.10-rc1 for details. MIPS structures it's dts files a little differently to other architectures, having a separate dts directory for each SoC/platform, but most of the definitions in the dt-bindings/ directory are common so for now lets just have a single "include chroot" for all MIPS platforms. Signed-off-by: James Hogan <[email protected]> Reviewed-by: Steven. J. Hill <[email protected]> Cc: Michal Marek <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Ian Campbell <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Pawel Moll <[email protected]> Cc: Rob Herring <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Acked-by: Stephen Warren <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/5745/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: powertv: Drop BOOTLOADER_DRIVER Kconfig symbolMarkos Chandras4-35/+2
The kbldr.h header file required for this was neither committed in the original submission in a3a0f8c8ed2e2470f4dcd6da95020d41fed84747 "MIPS: PowerTV: Base files for Cisco PowerTV platform" nor was it ever present in the git tree so this option never worked. Fixes the following build problem: arch/mips/powertv/reset.c:25:36: fatal error: asm/mach-powertv/kbldr.h: No such file or directory compilation terminated. Cc: David VomLehn <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Acked-by: Steven J. Hill <[email protected]> Cc: [email protected] Cc: David VomLehn <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/5801/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: Kconfig: Drop obsolete NR_CPUS_DEFAULT_{1,2} optionsMarkos Chandras1-14/+1
The NR_CPUS_DEFAULT_1 introduced as an aid for the QEMU platform in 72ede9b18967e7a8a62a88f164f003193f6d891f "[MIPS] Qemu: Fix Symmetric Uniprocessor support" which was later removed in 302922e5f6901eb6f29c58539631f71b3d9746b8 "[MIPS] Qemu: Remove platform." On certain randconfigs it may happen for NR_CPUS to have an empty value because not all SMP platforms select a suitable NR_CPUS_DEFAULT_* value. We fix this by restoring the range of NR_CPUS to 2..64 and drop the NR_CPUS_DEFAULT_{1,2} symbols. The first one is no longer used and the latter is not needed since NR_CPUS=2 is now the default value. Fixes the following problem on a randconfig: .config:164:warning: symbol value '' invalid for NR_CPUS Signed-off-by: Markos Chandras <[email protected]> Acked-by: Steven J. Hill <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5747/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: TXx9: Fix build error if CONFIG_TOSHIBA_JMR3927 is not selectedMarkos Chandras1-1/+1
The jmr3927_vec txx9_board_vec struct is defined in txx9/jmr3927/setup.c which is only built if CONFIG_TOSHIBA_JMR3927 is selected. This patch fixes the following build problem: arch/mips/txx9/generic/setup.c: In function 'select_board': arch/mips/txx9/generic/setup.c:354:20: error: 'jmr3927_vec' undeclared (first use in this function) arch/mips/txx9/generic/setup.c:354:20: note: each undeclared identifier is reported only once for each function it appears in make[3]: *** [arch/mips/txx9/generic/setup.o] Error 1 Signed-off-by: Markos Chandras <[email protected]> Acked-by: Steven J. Hill <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5713/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: Loongson: Hide the pci code behind CONFIG_PCIMarkos Chandras1-1/+2
The pci.c code depends on symbols which are only visible if CONFIG_PCI is selected. Also fixes the following problem on loongson allnoconfig: arch/mips/built-in.o: In function `pcibios_init': pci.c:(.init.text+0x528): undefined reference to `register_pci_controller' arch/mips/built-in.o:(.data+0xc): undefined reference to `loongson_pci_ops' Signed-off-by: Markos Chandras <[email protected]> Acked-by: Steven J. Hill <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5584/ Signed-off-by: Ralf Baechle <[email protected]>
2013-09-03MIPS: Ftrace: Fix function tracing return address to matchCorey Minyard1-1/+1
Dynamic function tracing was not working on MIPS. When doing dynamic tracing, the tracer attempts to match up the passed in address with the one the compiler creates in the mcount tables. The MIPS code was passing in the return address from the tracing function call, but the compiler tables were the address of the function call. So they wouldn't match. Just subtracting 8 from the return address will give the address of the function call. Easy enough. Signed-off-by: Corey Minyard <[email protected]> [[email protected]: Adjusted code comment and patch Subject.] Signed-off-by: David Daney <[email protected]> Cc: [email protected] Cc: Steven Rostedt <[email protected]> Signed-off-by: Ralf Baechle <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/5592/
2013-09-03MIPS: R4k clock source initialization bug fixMaciej W. Rozycki1-1/+9
This is a fix for a bug introduced with commit 447cdf2628b59aa513a42785450b348dced26d8a, submitted as archived here: http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20080312235002.c717dde3.yoichi_yuasa%40tripeaks.co.jp regrettably with no further explanation. The issue is with the CP0 Count register read erratum present on R4000 and some R4400 processors. If this erratum is present, then a read from this register that happens around the time it reaches the value stored in the CP0 Compare register causes a CP0 timer interrupt that is supposed to happen when the values in the two registers match to be missed. The implication for the chips affected is the CP0 timer can be used either as a source of a timer interrupt (a clock event) or as a source of a high-resolution counter (a clock source), but not both at a time. The erratum does not affect timer interrupt operation itself, because in this case the CP0 Count register is only read while the timer interrupt has already been raised, while high-resolution counter references happen at random times. Additionally some systems apparently have issues with the timer interrupt line being routed externally and not following the usual CP0 Count/Compare semantics. In this case we don't want to use the R4k clock event. We've meant to address the erratum and the timer interrupt routing issue in time_init, however the commit referred to above broke our solution. What we currently have is we enable the R4k clock source if the R4k clock event initialization has succeeded (the timer is present and has no timer interrupt routing issue) or there is no CP0 Count register read erratum. Which gives the following boolean matrix: clock event | count erratum => clock source ------------+---------------+-------------- 0 | 0 | 1 (OK) 0 | 1 | 0 (bug!) -> no interference, could use 1 | 0 | 1 (OK) 1 | 1 | 1 (bug!) -> can't use, interference What we want instead is to enable the R4k clock source if there is no CP0 Count register read erratum (obviously) or the R4k clock event initialization has *failed* -- because in the latter case we won't be using the timer interrupt anyway, so we don't care about any interference CP0 Count reads might cause with the interrupt. This corresponds to the following boolean matrix: clock event | count erratum => clock source ------------+---------------+-------------- 0 | 0 | 1 0 | 1 | 1 1 | 0 | 1 1 | 1 | 0 This is implemented here, effectively reverting the problematic commit, and a short explanation is given next to code modified so that the rationale is known to future readers and confusion is prevented from happening here again. It is worth noting that mips_clockevent_init returns 0 upon success while cpu_has_mfc0_count_bug returns 0 upon failure. This is because the former function returns an error code while the latter returns a boolean value. To signify the difference I have therefore chosen to compare the result of the former call explicitly against 0. Signed-off-by: Maciej W. Rozycki <[email protected]> Signed-off-by: Ralf Baechle <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5799/
2013-08-28Merge tag 'v3.11-rc7' into devicetree/nextGrant Likely11-16/+60
Linux 3.11-rc7
2013-08-26MIPS: Discard .eh_frame sections in linker script.David Daney1-0/+1
Some toolchains (including Cavium OCTEON SDK) are emitting .eh_frame sections by default. Discard them as they are useless in the kernel. Signed-off-by: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5684/ Signed-off-by: Ralf Baechle <[email protected]>
2013-08-26MIPS: OCTEON: Select ARCH_REQUIRE_GPIOLIBDavid Daney2-0/+22
... and create asm/mach-cavium-octeon/gpio.h so that things continue to build. This allows us to use the existing I2C connected GPIO expanders. Signed-off-by: David Daney <[email protected]> Acked-by: Linus Walleij <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5632/ Signed-off-by: Ralf Baechle <[email protected]>
2013-08-26MIPS: Remove unreachable break statements from cp1emu.cDavid Daney1-27/+0
There were many cases of: return something; break; All those break statements are unreachable and thus redundant. Signed-off-by: David Daney <[email protected]> Reviewed-by: Aaro Koskinen <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5727/ Signed-off-by: Ralf Baechle <[email protected]>
2013-08-26MIPS: BMIPS: Fix compilation for BMIPS5000Ralf Baechle1-33/+22
Commit 02b849f7613003fe5f9e58bf233d49b0ebd4a5e8 ("MIPS: Get rid of the use of .macro in C code.") replaced the macro usage but missed the accessors in bmips.h, causing the following build error: CC arch/mips/kernel/smp-bmips.o {standard input}: Assembler messages: {standard input}:951: Error: Unrecognized opcode `_ssnop' {standard input}:952: Error: Unrecognized opcode `_ssnop' (...) make[6]: *** [arch/mips/kernel/smp-bmips.o] Error 1 Fix by rewriting the inline assembler using existing inline functions. The generated code should stay unchanged. Signed-off-by: Ralf Baechle <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/5644/ Reviewed-by: Jonas Gorski <[email protected]>
2013-08-26MIPS: cavium-octeon: fix I/O space setup on non-PCI systemsAaro Koskinen2-4/+33
Fix I/O space setup, so that on non-PCI systems using inb()/outb() won't crash the system. Some drivers may try to probe I/O space and for that purpose we can just allocate some normal memory initially. Drivers trying to reserve a region will fail early as we set the size to 0. If a real I/O space is present, the PCI/PCIe support code will re-adjust the values accordingly. Tested with EdgeRouter Lite by enabling CONFIG_SERIO_I8042 that caused the originally reported crash. Reported-by: Faidon Liambotis <[email protected]> Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5626/ Signed-off-by: Ralf Baechle <[email protected]>
2013-08-26MIPS:Netlogic: Remove redundant value in operation.Alexandru Juncu1-2/+1
Removed parameters checked twice in logical OR operation. Suggested by coccinelle and manually verified. Signed-off-by: Alexandru Juncu <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5627/ Signed-off-by: Ralf Baechle <[email protected]>
2013-08-26MIPS: OCTEON: Set L1 cache parameters for OCTEON3 CPUs.David Daney1-0/+14
Signed-off-by: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5638/ Signed-off-by: Ralf Baechle <[email protected]>
2013-08-26MIPS: Generate OCTEON3 TLB handlers with the same features as OCTEON2.David Daney1-0/+2
OCTEON2 need the same code. Signed-off-by: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5637/ Signed-off-by: Ralf Baechle <[email protected]>
2013-08-26MIPS: Use r4k_wait for OCTEON3 CPUs.David Daney1-0/+1
Signed-off-by: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5636/ Signed-off-by: Ralf Baechle <[email protected]>
2013-08-26MIPS: Probe for new OCTEON CPU/SoC types.David Daney1-0/+7
Add probing for CNF71XX, CN78XX and CN70XX. Signed-off-by: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5635/ Signed-off-by: Ralf Baechle <[email protected]>
2013-08-26MIPS: Add CPU identifiers for more OCTEON family members.David Daney1-1/+4
Needed to support new SOCs. Signed-off-by: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5634/ Signed-off-by: Ralf Baechle <[email protected]>
2013-08-26MIPS: use generic-y where possibleJames Hogan17-58/+16
Use generic-y and remove headers in arch/mips/include/[uapi/]asm/Kbuild where the header just includes or is identical to the corresponding <asm-generic/*.h>. We can't do the same for uapi/asm/kvm_para.h because it's presence is explicitly checked in include/uapi/linux/Kbuild to decide whether to add kvm_para.h to header-y. Signed-off-by: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: Christoph Lameter <[email protected]> Cc: Tejun Heo <[email protected]> Cc: Dave Jones <[email protected]> Cc: David Howells <[email protected]> Cc: David Sharp <[email protected]> Cc: Paul E. McKenney <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5581/ Signed-off-by: Ralf Baechle <[email protected]>
2013-08-26MIPS: tlbex: Guard tlbmiss_handler_setup_pgdTony Wu1-0/+2
tlbmiss_handler_setup_pgd* are only referenced when CONFIG_MIPS_PGD_C0_CONTEXT is defined. Signed-off-by: Tony Wu <[email protected]> Cc: Jayachandran C. <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5601/ Signed-off-by: Ralf Baechle <[email protected]>
2013-08-26MIPS: Fix get_user_page_fast() for mips with cache aliasKamal Dasu1-1/+2
get_user_pages_fast() is missing cache flushes for MIPS platforms with cache aliases. Filesystem failures observed with DirectIO operations due to missing flush_anon_page() that use page coloring logic to work with cache aliases. This fix falls through to take slow_irqon path that calls get_user_pages() that has required logic for platforms where cpu_has_dc_aliases is true. [[email protected]: Explicity include <asm/cpu-features.h>.] Signed-off-by: Kamal Dasu <[email protected]> Cc: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/5469/ Signed-off-by: Ralf Baechle <[email protected]>
2013-08-26mips/kvm: Make kvm_locore.S 64-bit buildable/safe.David Daney1-27/+27
We need to use more of the Macros in asm.h to allow kvm_locore.S to build in a 64-bit kernel. For 32-bit there is no change in the generated object code. Signed-off-by: David Daney <[email protected]> Acked-by: Ralf Baechle <[email protected]> Acked-by: Paolo Bonzini <[email protected]> Signed-off-by: Gleb Natapov <[email protected]>
2013-08-26mips/kvm: Cleanup .push/.pop directives in kvm_locore.SDavid Daney1-13/+1
There are: .set push .set noreorder .set noat . . . .set pop Sequences all over the place in this file, but in some places the final ".set pop" is erroneously converted to ".set push", so none of these really do what they appear to. Clean up the whole mess by moving ".set noreorder", ".set noat" to the top, and get rid of everything else. Generated object code is unchanged. Signed-off-by: David Daney <[email protected]> Acked-by: Paolo Bonzini <[email protected]> Signed-off-by: Gleb Natapov <[email protected]>
2013-08-26mips/kvm: Improve code formatting in arch/mips/kvm/kvm_locore.SDavid Daney1-484/+491
No code changes, just reflowing some comments and consistently using tabs and spaces. Object code is verified to be unchanged. Signed-off-by: David Daney <[email protected]> Acked-by: Ralf Baechle <[email protected]> Acked-by: Paolo Bonzini <[email protected]> Reviewed-by: James Hogan <[email protected]> Signed-off-by: Gleb Natapov <[email protected]>
2013-08-22Kconfig: Remove hotplug enable hints in CONFIG_KEXEC help textsGeert Uytterhoeven1-3/+3
commit 40b313608ad4ea655addd2ec6cdd106477ae8e15 ("Finally eradicate CONFIG_HOTPLUG") removed remaining references to CONFIG_HOTPLUG, but missed a few plain English references in the CONFIG_KEXEC help texts. Remove them, too. Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Stephen Rothwell <[email protected]> Acked-by: Ingo Molnar <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2013-08-21Merge tag 'tegra-for-3.12-soc' of ↵Kevin Hilman2-7/+0
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From: Stephen Warren: ARM: tegra: core SoC enhancements for 3.12 This branch includes a number of enhancements to core SoC support for Tegra devices. The major new features are: * Adds a new CPU-power-gated cpuidle state for Tegra114. * Adds initial system suspend support for Tegra114, initially supporting just CPU-power-gating during suspend. * Adds "LP1" suspend mode support for all of Tegra20/30/114. This mode both gates CPU power, and places the DRAM into self-refresh mode. * A new DT-driven PCIe driver to Tegra20/30. The driver is also moved from arch/arm/mach-tegra/ to drivers/pci/host/. The PCIe driver work depends on the following tag from Thomas Petazzoni: git://git.infradead.org/linux-mvebu.git mis-3.12.2 ... which is merged into the middle of this pull request. * tag 'tegra-for-3.12-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (33 commits) ARM: tegra: disable LP2 cpuidle state if PCIe is enabled MAINTAINERS: Add myself as Tegra PCIe maintainer PCI: tegra: set up PADS_REFCLK_CFG1 PCI: tegra: Add Tegra 30 PCIe support PCI: tegra: Move PCIe driver to drivers/pci/host PCI: msi: add default MSI operations for !HAVE_GENERIC_HARDIRQS platforms ARM: tegra: add LP1 suspend support for Tegra114 ARM: tegra: add LP1 suspend support for Tegra20 ARM: tegra: add LP1 suspend support for Tegra30 ARM: tegra: add common LP1 suspend support clk: tegra114: add LP1 suspend/resume support ARM: tegra: config the polarity of the request of sys clock ARM: tegra: add common resume handling code for LP1 resuming ARM: pci: add ->add_bus() and ->remove_bus() hooks to hw_pci of: pci: add registry of MSI chips PCI: Introduce new MSI chip infrastructure PCI: remove ARCH_SUPPORTS_MSI kconfig option PCI: use weak functions for MSI arch-specific functions ARM: tegra: unify Tegra's Kconfig a bit more ARM: tegra: remove the limitation that Tegra114 can't support suspend ... Signed-off-by: Kevin Hilman <[email protected]>
2013-08-20MIPS: Handle OCTEON BBIT instructions in FPU emulator.David Daney1-0/+26
The branch emulation needs to handle the OCTEON BBIT instructions, otherwise we get SIGILL instead of emulation. Signed-off-by: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5726/ Signed-off-by: Ralf Baechle <[email protected]>
2013-08-19mips: convert vpe_class to use dev_groupsGreg Kroah-Hartman1-7/+10
The dev_attrs field of struct class is going away soon, dev_groups should be used instead. This converts the MIPS vpe_class code to use the correct field. Cc: Ralf Baechle <[email protected]> Cc: John Crispin <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2013-08-12PCI: remove ARCH_SUPPORTS_MSI kconfig optionThomas Petazzoni1-2/+0
Now that we have weak versions for each of the PCI MSI architecture functions, we can actually build the MSI support for all platforms, regardless of whether they provide or not architecture-specific versions of those functions. For this reason, the ARCH_SUPPORTS_MSI hidden kconfig boolean becomes useless, and this patch gets rid of it. Signed-off-by: Thomas Petazzoni <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Acked-by: Benjamin Herrenschmidt <[email protected]> Tested-by: Daniel Price <[email protected]> Tested-by: Thierry Reding <[email protected]> Cc: Benjamin Herrenschmidt <[email protected]> Cc: Paul Mackerras <[email protected]> Cc: [email protected] Cc: Martin Schwidefsky <[email protected]> Cc: Heiko Carstens <[email protected]> Cc: [email protected] Cc: [email protected] Cc: Thomas Gleixner <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: H. Peter Anvin <[email protected]> Cc: [email protected] Cc: Russell King <[email protected]> Cc: Tony Luck <[email protected]> Cc: Fenghua Yu <[email protected]> Cc: [email protected] Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: David S. Miller <[email protected]> Cc: [email protected] Cc: Chris Metcalf <[email protected]> Signed-off-by: Jason Cooper <[email protected]>
2013-08-12PCI: use weak functions for MSI arch-specific functionsThomas Petazzoni1-5/+0
Until now, the MSI architecture-specific functions could be overloaded using a fairly complex set of #define and compile-time conditionals. In order to prepare for the introduction of the msi_chip infrastructure, it is desirable to switch all those functions to use the 'weak' mechanism. This commit converts all the architectures that were overidding those MSI functions to use the new strategy. Note that we keep two separate, non-weak, functions default_teardown_msi_irqs() and default_restore_msi_irqs() for the default behavior of the arch_teardown_msi_irqs() and arch_restore_msi_irqs(), as the default behavior is needed by x86 PCI code. Signed-off-by: Thomas Petazzoni <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Acked-by: Benjamin Herrenschmidt <[email protected]> Tested-by: Daniel Price <[email protected]> Tested-by: Thierry Reding <[email protected]> Cc: Benjamin Herrenschmidt <[email protected]> Cc: Paul Mackerras <[email protected]> Cc: [email protected] Cc: Martin Schwidefsky <[email protected]> Cc: Heiko Carstens <[email protected]> Cc: [email protected] Cc: [email protected] Cc: Thomas Gleixner <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: H. Peter Anvin <[email protected]> Cc: [email protected] Cc: Russell King <[email protected]> Cc: Tony Luck <[email protected]> Cc: Fenghua Yu <[email protected]> Cc: [email protected] Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: David S. Miller <[email protected]> Cc: [email protected] Cc: Chris Metcalf <[email protected]> Signed-off-by: Jason Cooper <[email protected]>
2013-08-05MIPS: BCM63XX: export PSI size from nvramJonas Gorski2-0/+13
Signed-off-by: Jonas Gorski <[email protected]> Acked-by: Florian Fainelli <[email protected]> Signed-off-by: Artem Bityutskiy <[email protected]> Signed-off-by: David Woodhouse <[email protected]>
2013-08-05MIPS: BMIPS: fix hardware interrupt routing for boot CPU != 0Florian Fainelli1-2/+8
The hardware interrupt routing for boot CPU != 0 is wrong because it will route all the hardware interrupts to TP0 which is not the one we booted from. Fix this by properly checking which boot CPU we are booting from and updating the right interrupt mask for the boot CPU. This fixes booting on BCM3368 with bmips_smp_emabled = 0. Signed-off-by: Florian Fainelli <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5650/ Signed-off-by: Ralf Baechle <[email protected]>
2013-08-05MIPS: oprofile: Fix BUG due to smp_processor_id() in preemptible code.Ralf Baechle2-1/+3
current_cpu_type() is not preemption-safe. If CONFIG_PREEMPT is enabled then mipsxx_reg_setup() can be called from preemptible state. Added get_cpu()/put_cpu() pair to make it preemption-safe. This was found while testing oprofile with CONFIG_DEBUG_PREEMPT enable. /usr/zntestsuite # opcontrol --init /usr/zntestsuite # opcontrol --setup --event=L2_CACHE_ACCESSES:500 --event=L2_CACHE_MISSES:500 --no-vmlinux /usr/zntestsuite # opcontrol --start Using 2.6+ OProfile kernel interface. BUG: using smp_processor_id() in preemptible [00000000] code: oprofiled/1362 caller is mipsxx_reg_setup+0x11c/0x164 CPU: 0 PID: 1362 Comm: oprofiled Not tainted 3.10.4 #18 Stack : 00000006 70757465 00000000 00000000 00000000 00000000 80b173f6 00000037 80b10000 00000000 80b21614 88f5a220 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 89c49c00 89c49c2c 80721254 807b7927 8012c1d0 80b10000 80721254 00000000 00000552 88f5a220 80b1335c 807b78e6 89c49ba8 ... Call Trace: [<801099a4>] show_stack+0x64/0x7c [<80665520>] dump_stack+0x20/0x2c [<803a2250>] debug_smp_processor_id+0xe0/0xf0 [<8052df24>] mipsxx_reg_setup+0x11c/0x164 [<8052cd70>] op_mips_setup+0x24/0x4c [<80529cfc>] oprofile_setup+0x5c/0x12c [<8052b9f8>] event_buffer_open+0x78/0xf8 [<801c3150>] do_dentry_open.isra.15+0x2b8/0x3b0 [<801c3270>] finish_open+0x28/0x4c [<801d49b8>] do_last.isra.41+0x2cc/0xd00 [<801d54a0>] path_openat+0xb4/0x4c4 [<801d5c44>] do_filp_open+0x3c/0xac [<801c4744>] do_sys_open+0x110/0x1f4 [<8010f47c>] stack_done+0x20/0x44 Bug reported and original patch by Jerin Jacob <[email protected]>. Signed-off-by: Ralf Baechle <[email protected]> Acked-by: Jerin Jacob <[email protected]>
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