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2020-07-19Merge tag 'irq-urgent-2020-07-19' of ↵Linus Torvalds1-2/+3
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip into master Pull irq fixes from Thomas Gleixner: "Two fixes for the interrupt subsystem: - Make the handling of the firmware node consistent and do not free the node after the domain has been created successfully. The core code stores a pointer to it which can lead to a use after free or double free. This used to "work" because the pointer was not stored when the initial code was written, but at some point later it was required to store it. Of course nobody noticed that the existing users break that way. - Handle affinity setting on inactive interrupts correctly when hierarchical irq domains are enabled. When interrupts are inactive with the modern hierarchical irqdomain design, the interrupt chips are not necessarily in a state where affinity changes can be handled. The legacy irq chip design allowed this because interrupts are immediately fully initialized at allocation time. X86 has a hacky workaround for this, but other implementations do not. This cased malfunction on GIC-V3. Instead of playing whack a mole to find all affected drivers, change the core code to store the requested affinity setting and then establish it when the interrupt is allocated, which makes the X86 hack go away" * tag 'irq-urgent-2020-07-19' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: genirq/affinity: Handle affinity setting on inactive interrupts correctly irqdomain/treewide: Keep firmware node unconditionally allocated
2020-07-19dma-mapping: make support for dma ops optionalChristoph Hellwig1-0/+1
Avoid the overhead of the dma ops support for tiny builds that only use the direct mapping. Signed-off-by: Christoph Hellwig <[email protected]> Tested-by: Alexey Kardashevskiy <[email protected]> Reviewed-by: Alexey Kardashevskiy <[email protected]>
2020-07-16treewide: Remove uninitialized_var() usageKees Cook3-5/+5
Using uninitialized_var() is dangerous as it papers over real bugs[1] (or can in the future), and suppresses unrelated compiler warnings (e.g. "unused variable"). If the compiler thinks it is uninitialized, either simply initialize the variable or make compiler changes. In preparation for removing[2] the[3] macro[4], remove all remaining needless uses with the following script: git grep '\buninitialized_var\b' | cut -d: -f1 | sort -u | \ xargs perl -pi -e \ 's/\buninitialized_var\(([^\)]+)\)/\1/g; s:\s*/\* (GCC be quiet|to make compiler happy) \*/$::g;' drivers/video/fbdev/riva/riva_hw.c was manually tweaked to avoid pathological white-space. No outstanding warnings were found building allmodconfig with GCC 9.3.0 for x86_64, i386, arm64, arm, powerpc, powerpc64le, s390x, mips, sparc64, alpha, and m68k. [1] https://lore.kernel.org/lkml/[email protected]/ [2] https://lore.kernel.org/lkml/CA+55aFw+Vbj0i=1TGqCR5vQkCzWJ0QxK6CernOU6eedsudAixw@mail.gmail.com/ [3] https://lore.kernel.org/lkml/CA+55aFwgbgqhbp1fkxvRKEpzyR5J8n1vKT1VZdz9knmPuXhOeg@mail.gmail.com/ [4] https://lore.kernel.org/lkml/CA+55aFz2500WfbKXAx8s67wrm9=yVJu65TpLgN_ybYNv0VEOKA@mail.gmail.com/ Reviewed-by: Leon Romanovsky <[email protected]> # drivers/infiniband and mlx4/mlx5 Acked-by: Jason Gunthorpe <[email protected]> # IB Acked-by: Kalle Valo <[email protected]> # wireless drivers Reviewed-by: Chao Yu <[email protected]> # erofs Signed-off-by: Kees Cook <[email protected]>
2020-07-16MIPS: Prevent READ_IMPLIES_EXEC propagationTiezhu Yang1-0/+1
In the MIPS architecture, we should clear the security-relevant flag READ_IMPLIES_EXEC in the function SET_PERSONALITY2() of the file arch/mips/include/asm/elf.h. Otherwise, with this flag set, PROT_READ implies PROT_EXEC for mmap to make memory executable that is not safe, because this condition allows an attacker to simply jump to and execute bytes that are considered to be just data [1]. In mm/mmap.c: unsigned long do_mmap(struct file *file, unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, vm_flags_t vm_flags, unsigned long pgoff, unsigned long *populate, struct list_head *uf) { [...] if ((prot & PROT_READ) && (current->personality & READ_IMPLIES_EXEC)) if (!(file && path_noexec(&file->f_path))) prot |= PROT_EXEC; [...] } By the way, x86 and ARM64 have done the similar thing. After commit 250c22777fe1 ("x86_64: move kernel"), in the file arch/x86/kernel/process_64.c: void set_personality_64bit(void) { [...] current->personality &= ~READ_IMPLIES_EXEC; } After commit 48f99c8ec0b2 ("arm64: Preventing READ_IMPLIES_EXEC propagation"), in the file arch/arm64/include/asm/elf.h: #define SET_PERSONALITY(ex) \ ({ \ clear_thread_flag(TIF_32BIT); \ current->personality &= ~READ_IMPLIES_EXEC; \ }) [1] https://insights.sei.cmu.edu/cert/2014/02/feeling-insecure-blame-your-parent.html Reported-by: Juxin Gao <[email protected]> Co-developed-by: Juxin Gao <[email protected]> Signed-off-by: Juxin Gao <[email protected]> Signed-off-by: Tiezhu Yang <[email protected]> Reviewed-by: Kees Cook <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16mips/vdso: Fix resource leaks in genvdso.cPeng Fan1-0/+10
Close "fd" before the return of map_vdso() and close "out_file" in main(). Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: CU1000-Neo: Refresh defconfig to support LED.周琰杰 (Zhou Yanjie)1-0/+4
Refresh CU1000-Neo's defconfig to support LED. Tested-by: 周正 (Zhou Zheng) <[email protected]> Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: Ingenic: Fix bugs and add missing LED node for X1000.周琰杰 (Zhou Yanjie)2-122/+118
1.The CU1000-Neo board actually uses X1000E instead of X1000, so the wrongly written "ingenic,x1000" in compatible should be changed to "ingenic,x1000e". 2.Adjust the order of nodes according to the corresponding address value. 3.Drop unnecessary node in "wlan_pwrseq". 4.Add the leds node to "cu1000-neo.dts". Tested-by: 周正 (Zhou Zheng) <[email protected]> Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: Ingenic: Add YSH & ATIL CU Neo board support.周琰杰 (Zhou Yanjie)4-0/+296
Add a device tree and a defconfig for the Ingenic X1830 based YSH & ATIL CU Neo board. Tested-by: 周正 (Zhou Zheng) <[email protected]> Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: Ingenic: Add Ingenic X1830 support.周琰杰 (Zhou Yanjie)2-0/+306
Support the Ingenic X1830 SoC using the code under arch/mips/jz4740. This is left unselectable in Kconfig until a X1830 based board is added in a later commit. Tested-by: 周正 (Zhou Zheng) <[email protected]> Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: fix vdso different address spacesSunguoyun1-1/+1
sparse report build warning as follows: arch/mips/vdso/vdso-n32-image.c:13:35: incorrect type in assignment (different address spaces) @@ expected void *[usertype] vdso @@ got void [noderef] <asn:1> * @@ Reported-by: kernel test robot <[email protected]> Signed-off-by: Sunguoyun <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16mips: Replace HTTP links with HTTPS onesAlexander A. Klimov2-2/+2
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: Loongson64: Load LS7A dtbsJiaxun Yang1-22/+34
Load correct devicetree according to PRID and PCH type. Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Jiaxun Yang <[email protected]> Tested-by: Tiezhu Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: Loongson64: DeviceTree for LS7A PCHJiaxun Yang6-1/+512
Add DeviceTree files for Classic Loongson64 Quad Core + LS7A boards and Generic Loongson64 Quad Core + LS7A boards. Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Jiaxun Yang <[email protected]> Tested-by: Tiezhu Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: Loongson64: Fix machine namingHuacai Chen2-2/+2
From previous commits, the machine names with "loongson3-" prefix have renamed to "loongson64c-" prefix in documents, but the .dts files have not been updated as well. So fix it. Signed-off-by: Huacai Chen <[email protected]> Tested-by: Tiezhu Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: ingenic: RS90: Added defconfigPaul Cercueil1-0/+182
Add a basic default config for the RS-90 RetroMini board. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: ingenic: Add support for the RS90 boardPaul Cercueil3-0/+316
The RS-90, better known as RetroMini, is a small and pocketable handheld gaming console from YLMChina. It has little more than a JZ4725B SoC, a NAND, a screen, some buttons and a speaker. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: ingenic: Add support for the JZ4725B SoCPaul Cercueil3-0/+342
Add preliminary support for boards based on the JZ4725B SoC from Ingenic. The JZ4725B SoC is supposed to be older than the JZ4740 SoC, but its internals are much closer to what can be found on the JZ4750 and newer SoCs. It is low-power SoC with a MIPS32r1 SoC running at ~360 MHz, and no FPU. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: ingenic: Use enum instead of macros for Ingenic SoCsPaul Cercueil1-6/+16
Use an enum instead of macros to represent the various versions of the Ingenic SoCs, and add some of the SoC versions that were previously missing. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-14irqdomain/treewide: Keep firmware node unconditionally allocatedThomas Gleixner1-2/+3
Quite some non OF/ACPI users of irqdomains allocate firmware nodes of type IRQCHIP_FWNODE_NAMED or IRQCHIP_FWNODE_NAMED_ID and free them right after creating the irqdomain. The only purpose of these FW nodes is to convey name information. When this was introduced the core code did not store the pointer to the node in the irqdomain. A recent change stored the firmware node pointer in irqdomain for other reasons and missed to notice that the usage sites which do the alloc_fwnode/create_domain/free_fwnode sequence are broken by this. Storing a dangling pointer is dangerous itself, but in case that the domain is destroyed later on this leads to a double free. Remove the freeing of the firmware node after creating the irqdomain from all affected call sites to cure this. Fixes: 711419e504eb ("irqdomain: Add the missing assignment of domain->fwnode for named fwnode") Reported-by: Andy Shevchenko <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Acked-by: Marc Zyngier <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected]
2020-07-11Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netDavid S. Miller5-13/+18
All conflicts seemed rather trivial, with some guidance from Saeed Mameed on the tc_ct.c one. Signed-off-by: David S. Miller <[email protected]>
2020-07-10seccomp: Use -1 marker for end of mode 1 syscall listKees Cook1-2/+2
The terminator for the mode 1 syscalls list was a 0, but that could be a valid syscall number (e.g. x86_64 __NR_read). By luck, __NR_read was listed first and the loop construct would not test it, so there was no bug. However, this is fragile. Replace the terminator with -1 instead, and make the variable name for mode 1 syscall lists more descriptive. Cc: Andy Lutomirski <[email protected]> Cc: Will Drewry <[email protected]> Signed-off-by: Kees Cook <[email protected]>
2020-07-10mips: Remove compiler check in unroll macroNathan Chancellor1-3/+1
CONFIG_CC_IS_GCC is undefined when Clang is used, which breaks the build (see our Travis link below). Clang 8 was chosen as a minimum version for this check because there were some improvements around __builtin_constant_p in that release. In reality, MIPS was not even buildable until clang 9 so that check was not technically necessary. Just remove all compiler checks and just assume that we have a working compiler. Fixes: d4e60453266b ("Restore gcc check in mips asm/unroll.h") Link: https://travis-ci.com/github/ClangBuiltLinux/continuous-integration/jobs/359642821 Signed-off-by: Nathan Chancellor <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2020-07-10Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds1-0/+4
Pull vkm fixes from Paolo Bonzini: "Two simple but important bugfixes" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: MIPS: Fix build errors for 32bit kernel KVM: nVMX: fixes for preemption timer migration
2020-07-10KVM: MIPS: Fix build errors for 32bit kernelHuacai Chen1-0/+4
Commit dc6d95b153e78ed70b1b2c04a ("KVM: MIPS: Add more MMIO load/store instructions emulation") introduced some 64bit load/store instructions emulation which are unavailable on 32bit platform, and it causes build errors: arch/mips/kvm/emulate.c: In function 'kvm_mips_emulate_store': arch/mips/kvm/emulate.c:1734:6: error: right shift count >= width of type [-Werror] ((vcpu->arch.gprs[rt] >> 56) & 0xff); ^ arch/mips/kvm/emulate.c:1738:6: error: right shift count >= width of type [-Werror] ((vcpu->arch.gprs[rt] >> 48) & 0xffff); ^ arch/mips/kvm/emulate.c:1742:6: error: right shift count >= width of type [-Werror] ((vcpu->arch.gprs[rt] >> 40) & 0xffffff); ^ arch/mips/kvm/emulate.c:1746:6: error: right shift count >= width of type [-Werror] ((vcpu->arch.gprs[rt] >> 32) & 0xffffffff); ^ arch/mips/kvm/emulate.c:1796:6: error: left shift count >= width of type [-Werror] (vcpu->arch.gprs[rt] << 32); ^ arch/mips/kvm/emulate.c:1800:6: error: left shift count >= width of type [-Werror] (vcpu->arch.gprs[rt] << 40); ^ arch/mips/kvm/emulate.c:1804:6: error: left shift count >= width of type [-Werror] (vcpu->arch.gprs[rt] << 48); ^ arch/mips/kvm/emulate.c:1808:6: error: left shift count >= width of type [-Werror] (vcpu->arch.gprs[rt] << 56); ^ cc1: all warnings being treated as errors make[3]: *** [arch/mips/kvm/emulate.o] Error 1 So, use #if defined(CONFIG_64BIT) && defined(CONFIG_KVM_MIPS_VZ) to guard the 64bit load/store instructions emulation. Reported-by: kernel test robot <[email protected]> Fixes: dc6d95b153e78ed70b1b2c04a ("KVM: MIPS: Add more MMIO load/store instructions emulation") Signed-off-by: Huacai Chen <[email protected]> Message-Id: <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2020-07-10KVM: MIPS: clean up redundant 'kvm_run' parametersTianjia Zhang5-151/+87
In the current kvm version, 'kvm_run' has been included in the 'kvm_vcpu' structure. For historical reasons, many kvm-related function parameters retain the 'kvm_run' and 'kvm_vcpu' parameters at the same time. This patch does a unified cleanup of these remaining redundant parameters. Signed-off-by: Tianjia Zhang <[email protected]> Reviewed-by: Huacai Chen <[email protected]> Message-Id: <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2020-07-10MIPS: KVM: Remove outdated READMEJiaxun Yang1-31/+0
This file was created long ago and information inside is obviously outdated. Signed-off-by: Jiaxun Yang <[email protected]> Message-Id: <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2020-07-10MIPS: KVM: Limit Trap-and-Emulate to MIPS32R2 onlyJiaxun Yang2-1/+3
After tons of fixes to get Trap-and-Emulate build on Loongson64, I've got panic on host machine when trying to run a VM. I found that it can never work on 64bit systems. Revewing the code, it looks like R6 can't supportrd by TE as well. Signed-off-by: Jiaxun Yang <[email protected]> Message-Id: <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2020-07-09Restore gcc check in mips asm/unroll.hCesar Eduardo Barros1-1/+2
While raising the gcc version requirement to 4.9, the compile-time check in the unroll macro was accidentally changed from being used on gcc and clang to being used on clang only. Restore the gcc check, changing it from "gcc >= 4.7" to "all gcc". [ We should probably remove this all entirely: if we remove the check for CLANG, then the check for GCC can go away. Older versions of clang are not really appropriate or supported for kernel builds - Linus ] Fixes: 6ec4476ac825 ("Raise gcc version requirement to 4.9") Signed-off-by: Cesar Eduardo Barros <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2020-07-09KVM: MIPS: Use common KVM implementation of MMU memory cachesSean Christopherson4-47/+12
Move to the common MMU memory cache implementation now that the common code and MIPS's existing code are semantically compatible. No functional change intended. Suggested-by: Christoffer Dall <[email protected]> Signed-off-by: Sean Christopherson <[email protected]> Message-Id: <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2020-07-09KVM: MIPS: Account pages used for GPA page tablesSean Christopherson1-1/+1
Use GFP_KERNEL_ACCOUNT instead of GFP_KERNEL when allocating pages for the the GPA page tables. The primary motivation for accounting the allocations is to align with the common KVM memory cache helpers in preparation for moving to the common implementation in a future patch. The actual accounting is a bonus side effect. Signed-off-by: Sean Christopherson <[email protected]> Message-Id: <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2020-07-09KVM: MIPS: Drop @max param from mmu_topup_memory_cache()Sean Christopherson1-8/+4
Replace the @max param in mmu_topup_memory_cache() and instead use ARRAY_SIZE() to terminate the loop to fill the cache. This removes a BUG_ON() and sets the stage for moving MIPS to the common memory cache implementation. No functional change intended. Signed-off-by: Sean Christopherson <[email protected]> Message-Id: <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2020-07-09KVM: Move x86's version of struct kvm_mmu_memory_cache to common codeSean Christopherson1-0/+1
Move x86's 'struct kvm_mmu_memory_cache' to common code in anticipation of moving the entire x86 implementation code to common KVM and reusing it for arm64 and MIPS. Add a new architecture specific asm/kvm_types.h to control the existence and parameters of the struct. The new header is needed to avoid a chicken-and-egg problem with asm/kvm_host.h as all architectures define instances of the struct in their vCPU structs. Add an asm-generic version of kvm_types.h to avoid having empty files on PPC and s390 in the long term, and for arm64 and mips in the short term. Suggested-by: Christoffer Dall <[email protected]> Reviewed-by: Ben Gardon <[email protected]> Signed-off-by: Sean Christopherson <[email protected]> Message-Id: <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2020-07-08KVM: MIPS: fix spelling mistake "Exteneded" -> "Extended"Colin Ian King1-2/+2
There is a spelling mistake in a couple of kvm_err messages. Fix them. Signed-off-by: Colin Ian King <[email protected]> Message-Id: <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2020-07-08Raise gcc version requirement to 4.9Linus Torvalds1-4/+3
I realize that we fairly recently raised it to 4.8, but the fact is, 4.9 is a much better minimum version to target. We have a number of workarounds for actual bugs in pre-4.9 gcc versions (including things like internal compiler errors on ARM), but we also have some syntactic workarounds for lacking features. In particular, raising the minimum to 4.9 means that we can now just assume _Generic() exists, which is likely the much better replacement for a lot of very convoluted built-time magic with conditionals on sizeof and/or __builtin_choose_expr() with same_type() etc. Using _Generic also means that you will need to have a very recent version of 'sparse', but thats easy to build yourself, and much less of a hassle than some old gcc version can be. The latest (in a long string) of reasons for minimum compiler version upgrades was commit 5435f73d5c4a ("efi/x86: Fix build with gcc 4"). Ard points out that RHEL 7 uses gcc-4.8, but the people who stay back on old RHEL versions persumably also don't build their own kernels anyway. And maybe they should cross-built or just have a little side affair with a newer compiler? Acked-by: Ard Biesheuvel <[email protected]> Acked-by: Peter Zijlstra <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2020-07-08MIPS: Loongson: Update dts file for RS780EHuacai Chen1-2/+2
The size of ioports in the current RS780E dts file is not enough, which sometimes causes device initialize fail. So we increase the size of ISA/ LPC ioports to 0x4000, and increase the size of PCI ioports to 0x8000. Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-08MIPS: Loongson: Rename CPU device-tree bindingHuacai Chen6-7/+7
Loongson-3A R1/R2/R3 and Loongson-3B R1/R2 use the same package naming in dts, and Loongson-3A R4 will be different. In cpu.h the classic 64bit Loongson processors are called Loongson64C (C for classic, pre Loongson- 3A R4), and the new 64bit Loongson processors are called Loongson64G (G for generic, Loongson-3A R4+). To keep consistency and make extensible, we rename the classic "loongson3" prefix to "loongson64c", and the new prefix for Loongson-3A R4+ will be "loongson64g". Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-08MIPS: Loongson64: Adjust IRQ layoutHuacai Chen1-1/+5
Adjust IRQ layout in order to use IRQ resources more efficiently, which is done by adjusting NR_IRQS and MIPS_CPU_IRQ_BASE. Before this patch: 0~15: ISA/LPC IRQs; 16~55: Dynamic IRQs; 56~63: MIPS CPU IRQs; 64~127: PCH IRQs; 128~255: Dynamic IRQs. After this patch: 0~15: ISA/LPC IRQs; 16~23: MIPS CPU IRQs; 24~87: PCH IRQs; 88~280: Dynamic IRQs. Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-08MIPS: Unify naming style of vendor CP0.Config6 bitsHuacai Chen5-27/+27
Other vendor-defined registers use the vendor name as a prefix, not an infix, so unify the naming style of CP0.Config6 bits. Suggested-by: Maciej W. Rozycki" <[email protected]> Signed-off-by: Huacai Chen <[email protected]> Reviewed-by: Maciej W. Rozycki <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-07kbuild: remove cc-option test of -fno-stack-protectorMasahiro Yamada1-2/+1
Some Makefiles already pass -fno-stack-protector unconditionally. For example, arch/arm64/kernel/vdso/Makefile, arch/x86/xen/Makefile. No problem report so far about hard-coding this option. So, we can assume all supported compilers know -fno-stack-protector. GCC 4.8 and Clang support this option (https://godbolt.org/z/_HDGzN) Get rid of cc-option from -fno-stack-protector. Remove CONFIG_CC_HAS_STACKPROTECTOR_NONE, which is always 'y'. Note: arch/mips/vdso/Makefile adds -fno-stack-protector twice, first unconditionally, and second conditionally. I removed the second one. Signed-off-by: Masahiro Yamada <[email protected]> Reviewed-by: Kees Cook <[email protected]> Acked-by: Ard Biesheuvel <[email protected]> Reviewed-by: Nick Desaulniers <[email protected]>
2020-07-05Merge tag 'mips_fixes_5.8_1' of ↵Linus Torvalds3-8/+11
git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS fixes from Thomas Bogendoerfer: - fix for missing hazard barrier - DT fix for ingenic - DT fix of GPHY names for lantiq - fix usage of smp_processor_id() while preemption is enabled * tag 'mips_fixes_5.8_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: Do not use smp_processor_id() in preemptible code MIPS: Add missing EHB in mtc0 -> mfc0 sequence for DSPen MIPS: ingenic: gcw0: Fix HP detection GPIO. MIPS: lantiq: xway: sysctrl: fix the GPHY clock alias names
2020-07-05MIPS: Do not use smp_processor_id() in preemptible codeXingxing Su1-3/+5
Use preempt_disable() to fix the following bug under CONFIG_DEBUG_PREEMPT. [ 21.915305] BUG: using smp_processor_id() in preemptible [00000000] code: qemu-system-mip/1056 [ 21.923996] caller is do_ri+0x1d4/0x690 [ 21.927921] CPU: 0 PID: 1056 Comm: qemu-system-mip Not tainted 5.8.0-rc2 #3 [ 21.934913] Stack : 0000000000000001 ffffffff81370000 ffffffff8071cd60 a80f926d5ac95694 [ 21.942984] a80f926d5ac95694 0000000000000000 98000007f0043c88 ffffffff80f2fe40 [ 21.951054] 0000000000000000 0000000000000000 0000000000000001 0000000000000000 [ 21.959123] ffffffff802d60cc 98000007f0043dd8 ffffffff81f4b1e8 ffffffff81f60000 [ 21.967192] ffffffff81f60000 ffffffff80fe0000 ffff000000000000 0000000000000000 [ 21.975261] fffffffff500cce1 0000000000000001 0000000000000002 0000000000000000 [ 21.983331] ffffffff80fe1a40 0000000000000006 ffffffff8077f940 0000000000000000 [ 21.991401] ffffffff81460000 98000007f0040000 98000007f0043c80 000000fffba8cf20 [ 21.999471] ffffffff8071cd60 0000000000000000 0000000000000000 0000000000000000 [ 22.007541] 0000000000000000 0000000000000000 ffffffff80212ab4 a80f926d5ac95694 [ 22.015610] ... [ 22.018086] Call Trace: [ 22.020562] [<ffffffff80212ab4>] show_stack+0xa4/0x138 [ 22.025732] [<ffffffff8071cd60>] dump_stack+0xf0/0x150 [ 22.030903] [<ffffffff80c73f5c>] check_preemption_disabled+0xf4/0x100 [ 22.037375] [<ffffffff80213b84>] do_ri+0x1d4/0x690 [ 22.042198] [<ffffffff8020b828>] handle_ri_int+0x44/0x5c [ 24.359386] BUG: using smp_processor_id() in preemptible [00000000] code: qemu-system-mip/1072 [ 24.368204] caller is do_ri+0x1a8/0x690 [ 24.372169] CPU: 4 PID: 1072 Comm: qemu-system-mip Not tainted 5.8.0-rc2 #3 [ 24.379170] Stack : 0000000000000001 ffffffff81370000 ffffffff8071cd60 a80f926d5ac95694 [ 24.387246] a80f926d5ac95694 0000000000000000 98001007ef06bc88 ffffffff80f2fe40 [ 24.395318] 0000000000000000 0000000000000000 0000000000000001 0000000000000000 [ 24.403389] ffffffff802d60cc 98001007ef06bdd8 ffffffff81f4b818 ffffffff81f60000 [ 24.411461] ffffffff81f60000 ffffffff80fe0000 ffff000000000000 0000000000000000 [ 24.419533] fffffffff500cce1 0000000000000001 0000000000000002 0000000000000000 [ 24.427603] ffffffff80fe0000 0000000000000006 ffffffff8077f940 0000000000000020 [ 24.435673] ffffffff81460020 98001007ef068000 98001007ef06bc80 000000fffbbbb370 [ 24.443745] ffffffff8071cd60 0000000000000000 0000000000000000 0000000000000000 [ 24.451816] 0000000000000000 0000000000000000 ffffffff80212ab4 a80f926d5ac95694 [ 24.459887] ... [ 24.462367] Call Trace: [ 24.464846] [<ffffffff80212ab4>] show_stack+0xa4/0x138 [ 24.470029] [<ffffffff8071cd60>] dump_stack+0xf0/0x150 [ 24.475208] [<ffffffff80c73f5c>] check_preemption_disabled+0xf4/0x100 [ 24.481682] [<ffffffff80213b58>] do_ri+0x1a8/0x690 [ 24.486509] [<ffffffff8020b828>] handle_ri_int+0x44/0x5c Signed-off-by: Xingxing Su <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-05MIPS: Add missing EHB in mtc0 -> mfc0 sequence for DSPenHauke Mehrtens1-0/+1
This resolves the hazard between the mtc0 in the change_c0_status() and the mfc0 in configure_exception_vector(). Without resolving this hazard configure_exception_vector() could read an old value and would restore this old value again. This would revert the changes change_c0_status() did. I checked this by printing out the read_c0_status() at the end of per_cpu_trap_init() and the ST0_MX is not set without this patch. The hazard is documented in the MIPS Architecture Reference Manual Vol. III: MIPS32/microMIPS32 Privileged Resource Architecture (MD00088), rev 6.03 table 8.1 which includes: Producer | Consumer | Hazard ----------|----------|---------------------------- mtc0 | mfc0 | any coprocessor 0 register I saw this hazard on an Atheros AR9344 rev 2 SoC with a MIPS 74Kc CPU. There the change_c0_status() function would activate the DSPen by setting ST0_MX in the c0_status register. This was reverted and then the system got a DSP exception when the DSP registers were saved in save_dsp() in the first process switch. The crash looks like this: [ 0.089999] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) [ 0.097796] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) [ 0.107070] Kernel panic - not syncing: Unexpected DSP exception [ 0.113470] Rebooting in 1 seconds.. We saw this problem in OpenWrt only on the MIPS 74Kc based Atheros SoCs, not on the 24Kc based SoCs. We only saw it with kernel 5.4 not with kernel 4.19, in addition we had to use GCC 8.4 or 9.X, with GCC 8.3 it did not happen. In the kernel I bisected this problem to commit 9012d011660e ("compiler: allow all arches to enable CONFIG_OPTIMIZE_INLINING"), but when this was reverted it also happened after commit 172dcd935c34b ("MIPS: Always allocate exception vector for MIPSr2+"). Commit 0b24cae4d535 ("MIPS: Add missing EHB in mtc0 -> mfc0 sequence.") does similar changes to a different file. I am not sure if there are more places affected by this problem. Signed-off-by: Hauke Mehrtens <[email protected]> Cc: <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-04arch: rename copy_thread_tls() back to copy_thread()Christian Brauner1-2/+3
Now that HAVE_COPY_THREAD_TLS has been removed, rename copy_thread_tls() back simply copy_thread(). It's a simpler name, and doesn't imply that only tls is copied here. This finishes an outstanding chunk of internal process creation work since we've added clone3(). Cc: [email protected] Acked-by: Thomas Bogendoerfer <[email protected]>A Acked-by: Stafford Horne <[email protected]> Acked-by: Greentime Hu <[email protected]> Acked-by: Geert Uytterhoeven <[email protected]>A Reviewed-by: Kees Cook <[email protected]> Signed-off-by: Christian Brauner <[email protected]>
2020-07-04arch: remove HAVE_COPY_THREAD_TLSChristian Brauner1-1/+0
All architectures support copy_thread_tls() now, so remove the legacy copy_thread() function and the HAVE_COPY_THREAD_TLS config option. Everyone uses the same process creation calling convention based on copy_thread_tls() and struct kernel_clone_args. This will make it easier to maintain the core process creation code under kernel/, simplifies the callpaths and makes the identical for all architectures. Cc: [email protected] Acked-by: Thomas Bogendoerfer <[email protected]> Acked-by: Greentime Hu <[email protected]> Acked-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Kees Cook <[email protected]> Signed-off-by: Christian Brauner <[email protected]>
2020-06-29Merge 5.8-rc3 into usb-nextGreg Kroah-Hartman2-3/+5
We want the USB fixes in here, and this resolves a merge issue found in linux-next. Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-06-25Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netDavid S. Miller2-3/+5
Minor overlapping changes in xfrm_device.c, between the double ESP trailing bug fix setting the XFRM_INIT flag and the changes in net-next preparing for bonding encryption support. Signed-off-by: David S. Miller <[email protected]>
2020-06-25mips: Return proper error code from console ->setup() hookAndy Shevchenko1-1/+3
For unifying console ->setup() handling, which is poorly documented, return error code, rather than non-zero arbitrary number. Signed-off-by: Andy Shevchenko <[email protected]> Reviewed-by: Petr Mladek <[email protected]> Acked-by: Thomas Bogendoerfer <[email protected]> Signed-off-by: Petr Mladek <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-06-25MIPS: checksum: fix sparse flooding on asm/checksum.hAlexander Lobakin1-2/+2
csum_fold() in MIPS' asm/checksum.h is another source of sparse flooding when building different networking source code. The thing is that only half of __wsum <--> u32 casts inside the function is forced, which is insufficient. Add all necessary forced typecasting to stop floods and simplify actual bug hunting. Signed-off-by: Alexander Lobakin <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-06-25MIPS: io: fix sparse flood on asm/io.hAlexander Lobakin7-24/+30
MIPS MMIO macros for byteswapping from/to hardware endianness are a bit tricky because they use cpu_to_le{16,32,64}() in both directions. This generates a lot of questions from sparse as __le{16,32,64} types are 'restricted' and direct cast is forbidden in order to prevent messing up the byteorder. As MMIO ops are used in almost every single driver, this leads to console flooding and complicates bug hunting. We could fix it in a more proper way, i.e. separate from device / to device byteswap macros and expand __BUILD_MEMORY_*(), but this seems redundant and will produce code duplication. Instead, just expand the existing *ioswab*() macros with forced typecasting to stop floods. Signed-off-by: Alexander Lobakin <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-06-25MIPS: generic/ip32: io: fix __mem_ioswabq()Alexander Lobakin2-2/+2
*readq() family operates with u64 arguments, so they need 64-bit byteswaps. Correct macros for Generic MIPS and IP-32 to match other machines' implementations. Signed-off-by: Alexander Lobakin <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
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