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2019-10-16rtc: ds1685: add indirect access method and remove plat_read/plat_writeThomas Bogendoerfer1-1/+1
SGI Octane (IP30) doesn't have RTC register directly mapped into CPU address space, but accesses RTC registers with an address and data register. This is now supported by additional access functions, which are selected by a new field in platform data. Removed plat_read/plat_write since there is no user and their usage could introduce lifetime issue, when functions are placed in different modules. Signed-off-by: Thomas Bogendoerfer <[email protected]> Acked-by: Joshua Kinard <[email protected]> Reviewed-by: Joshua Kinard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Alexandre Belloni <[email protected]>
2019-10-12Merge tag 'usb-5.4-rc3' of ↵Linus Torvalds2-2/+0
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB fixes from Greg KH: "Here are a lot of small USB driver fixes for 5.4-rc3. syzbot has stepped up its testing of the USB driver stack, now able to trigger fun race conditions between disconnect and probe functions. Because of that we have a lot of fixes in here from Johan and others fixing these reported issues that have been around since almost all time. We also are just deleting the rio500 driver, making all of the syzbot bugs found in it moot as it turns out no one has been using it for years as there is a userspace version that is being used instead. There are also a number of other small fixes in here, all resolving reported issues or regressions. All have been in linux-next without any reported issues" * tag 'usb-5.4-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (65 commits) USB: yurex: fix NULL-derefs on disconnect USB: iowarrior: use pr_err() USB: iowarrior: drop redundant iowarrior mutex USB: iowarrior: drop redundant disconnect mutex USB: iowarrior: fix use-after-free after driver unbind USB: iowarrior: fix use-after-free on release USB: iowarrior: fix use-after-free on disconnect USB: chaoskey: fix use-after-free on release USB: adutux: fix use-after-free on release USB: ldusb: fix NULL-derefs on driver unbind USB: legousbtower: fix use-after-free on release usb: cdns3: Fix for incorrect DMA mask. usb: cdns3: fix cdns3_core_init_role() usb: cdns3: gadget: Fix full-speed mode USB: usb-skeleton: drop redundant in-urb check USB: usb-skeleton: fix use-after-free after driver unbind USB: usb-skeleton: fix NULL-deref on disconnect usb:cdns3: Fix for CV CH9 running with g_zero driver. usb: dwc3: Remove dev_err() on platform_get_irq() failure usb: dwc3: Switch to platform_get_irq_byname_optional() ...
2019-10-12MIPS: Make builtin_cmdline const & variable lengthPaul Burton1-1/+1
We have no need for the builtin_cmdline array to be fixed at the length of COMMAND_LINE_SIZE - we'll only copy out the string it contains up to its NULL terminator anyway, and cap the size at COMMAND_LINE_SIZE when copying into or concatenating with boot_command_line. The string value is also constant, so we can declare it as such to place it in the .init.rodata section. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected]
2019-10-12MIPS: Fix CONFIG_OF_EARLY_FLATTREE=n buildsPaul Burton1-0/+6
Configurations with CONFIG_OF_EARLY_FLATTREE=n fail to build since commit 7784cac69735 ("MIPS: cmdline: Clean up boot_command_line initialization") because of_scan_flat_dt() & of_scan_flat_dt() are not defined in these configurations. Fix this by #ifdef'ing the affected code... Signed-off-by: Paul Burton <[email protected]> Fixes: 7784cac69735 ("MIPS: cmdline: Clean up boot_command_line initialization") Reported-by: kbuild test robot <[email protected]> Cc: [email protected]
2019-10-12MIPS: Always define builtin_cmdlinePaul Burton1-0/+2
Commit 7784cac69735 ("MIPS: cmdline: Clean up boot_command_line initialization") made use of builtin_cmdline conditional upon plain C if statements rather than preprocessor #ifdef's. This caused build failures for configurations with CONFIG_CMDLINE_BOOL=n where builtin_cmdline wasn't defined, for example: arch/mips/kernel/setup.c: In function 'bootcmdline_init': >> arch/mips/kernel/setup.c:582:30: error: 'builtin_cmdline' undeclared (first use in this function); did you mean 'builtin_driver'? strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE); ^~~~~~~~~~~~~~~ builtin_driver arch/mips/kernel/setup.c:582:30: note: each undeclared identifier is reported only once for each function it appears in Fix this by defining builtin_cmdline as an empty string in the affected configurations. All of the paths that use it should be optimized out anyway so the data itself gets optimized away too. Signed-off-by: Paul Burton <[email protected]> Fixes: 7784cac69735 ("MIPS: cmdline: Clean up boot_command_line initialization") Reported-by: kbuild test robot <[email protected]> Reported-by: Nathan Chancellor <[email protected]> Cc: [email protected]
2019-10-10mips: Fix unroll macro when building with ClangNathan Chancellor1-1/+2
Building with Clang errors after commit 6baaeadae911 ("MIPS: Provide unroll() macro, use it for cache ops") since the GCC_VERSION macro is defined in include/linux/compiler-gcc.h, which is only included in compiler.h when using GCC: In file included from arch/mips/kernel/mips-mt.c:20: ./arch/mips/include/asm/r4kcache.h:254:1: error: use of undeclared identifier 'GCC_VERSION'; did you mean 'S_VERSION'? __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, ) ^ ./arch/mips/include/asm/r4kcache.h:219:4: note: expanded from macro '__BUILD_BLAST_CACHE' cache_unroll(32, kernel_cache, indexop, ^ ./arch/mips/include/asm/r4kcache.h:203:2: note: expanded from macro 'cache_unroll' unroll(times, _cache_op, insn, op, (addr) + (i++ * (lsize))); ^ ./arch/mips/include/asm/unroll.h:28:15: note: expanded from macro 'unroll' BUILD_BUG_ON(GCC_VERSION >= 40700 && \ ^ Use CONFIG_GCC_VERSION, which will always be set by Kconfig. Additionally, Clang 8 had improvements around __builtin_constant_p so use that as a lower limit for this check with Clang (although MIPS wasn't buildable until Clang 9); building a kernel with Clang 9.0.0 has no issues after this change. Fixes: 6baaeadae911 ("MIPS: Provide unroll() macro, use it for cache ops") Link: https://github.com/ClangBuiltLinux/linux/issues/736 Signed-off-by: Nathan Chancellor <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: Nick Desaulniers <[email protected]>
2019-10-10MIPS: Disable Loongson MMI instructions for kernel buildPaul Burton2-0/+5
GCC 9.x automatically enables support for Loongson MMI instructions when using some -march= flags, and then errors out when -msoft-float is specified with: cc1: error: ‘-mloongson-mmi’ must be used with ‘-mhard-float’ The kernel shouldn't be using these MMI instructions anyway, just as it doesn't use floating point instructions. Explicitly disable them in order to fix the build with GCC 9.x. Signed-off-by: Paul Burton <[email protected]> Fixes: 3702bba5eb4f ("MIPS: Loongson: Add GCC 4.4 support for Loongson2E") Fixes: 6f7a251a259e ("MIPS: Loongson: Add basic Loongson 2F support") Fixes: 5188129b8c9f ("MIPS: Loongson-3: Improve -march option and move it to Platform") Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected] # v2.6.32+ Cc: [email protected]
2019-10-10MIPS: elf_hwcap: Export userspace ASEsJiaxun Yang2-0/+44
A Golang developer reported MIPS hwcap isn't reflecting instructions that the processor actually supported so programs can't apply optimized code at runtime. Thus we export the ASEs that can be used in userspace programs. Reported-by: Meng Zhuo <[email protected]> Signed-off-by: Jiaxun Yang <[email protected]> Cc: [email protected] Cc: Paul Burton <[email protected]> Cc: <[email protected]> # 4.14+ Signed-off-by: Paul Burton <[email protected]>
2019-10-10MIPS: cmdline: Clean up boot_command_line initializationPaul Burton1-42/+83
Our current code to initialize boot_command_line is a mess. Some of this is due to the addition of too many options over the years, and some of this is due to workarounds for early_init_dt_scan_chosen() performing actions specific to options from other architectures that probably shouldn't be in generic code. Clean this up by introducing a new bootcmdline_init() function that simplifies the initialization somewhat. The major changes are: - Because bootcmdline_init() is a function it can return early in the CONFIG_CMDLINE_OVERRIDE case. - We clear boot_command_line rather than inheriting whatever early_init_dt_scan_chosen() may have left us. This means we no longer need to set boot_command_line to a space character in an attempt to prevent early_init_dt_scan_chosen() from copying CONFIG_CMDLINE into boot_command_line without us knowing about it. - Indirection via USE_PROM_CMDLINE, USE_DTB_CMDLINE, EXTEND_WITH_PROM & BUILTIN_EXTEND_WITH_PROM macros is removed; they seemingly served only to obfuscate the code. - The logic is cleaner, clearer & commented. Two minor drawbacks of this approach are: 1) We call of_scan_flat_dt(), which means we scan through the DT again. The overhead is fairly minimal & shouldn't be noticeable. 2) cmdline_scan_chosen() duplicates a small amount of the logic from early_init_dt_scan_chosen(). Alternatives might be to allow the generic FDT code to keep & expose a copy of the arguments taken from the /chosen node's bootargs property, or to introduce a function like early_init_dt_scan_chosen() that retrieves them without modification to handle CONFIG_CMDLINE. Neither of these sounds particularly cleaner though, and this way we at least keep the extra work in arch/mips. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected]
2019-10-09MIPS: cmdline: Remove redundant Kconfig defaultsPaul Burton1-3/+0
CMDLINE, CMDLINE_BOOL & CMDLINE_FORCE all explicitly specify default values that are the same as the default value for their respective types anyway (ie. n for booleans, and the empty string for strings). Remove the redundant defaults. Signed-off-by: Paul Burton <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Cc: [email protected]
2019-10-09MIPS: SGI-IP22/28: Use PROM for memory detectionThomas Bogendoerfer5-79/+34
EARLY_PRINTK uses ArcWrite (via prom_putchar) on IP22/28, which needs to not mess up PROMs data structures. ARC PROM gives out a list of memory chunks, which are used and which are free. This fixes the problem of not working early printk. By using XKPHYS spaces more than 256MB memory on Indigo2 R4k machines is working now, too. Signed-off-by: Thomas Bogendoerfer <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected]
2019-10-09MIPS: SGI-IP22: set PHYS_OFFSET to memory startThomas Bogendoerfer1-2/+1
IP22 started at physical 0x08000000. To avoid wasting memory for page structs set PHYS_OFFSET. Signed-off-by: Thomas Bogendoerfer <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected]
2019-10-09MIPS: fw: arc: workaround 64bit kernel/32bit ARC problemsThomas Bogendoerfer1-4/+21
Pointer arguments for 32bit ARC PROMs must reside in CKSEG0/1. While the initial stack resides in CKSEG0 the first kernel thread stack is already placed at a XKPHYS address, which ARC32 can't handle. The workaround here is to use static variables, which are placed into BSS and linked to a CKSEG0 address. Signed-off-by: Thomas Bogendoerfer <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected]
2019-10-09MIPS: Kconfig: always select ARC_MEMORY and ARC_PROMLIB for platformThomas Bogendoerfer1-4/+8
Instead of having a default y option with depends simply select options for the platforms where they are needed. Signed-off-by: Thomas Bogendoerfer <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected]
2019-10-09MIPS: fw: arc: use call_o32 to call ARC prom from 64bit kernelThomas Bogendoerfer2-73/+35
When using a 64bit kernel with generic spaces setup stack is also placed in XKPYHS, which the 32bit PROM can't handle. By using call_o32 for ARC_CALLs a stack placed in KSEG0 is used when calling PROM. Signed-off-by: Thomas Bogendoerfer <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected]
2019-10-09MIPS: fw: arc: remove unused ARC codeThomas Bogendoerfer9-304/+6
Current kernel uses only a few ARC calls. Drop all unused ARC functions. Signed-off-by: Thomas Bogendoerfer <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected]
2019-10-09MIPS: Drop 32-bit asm string functionsPaul Burton1-123/+0
We have assembly implementations of strcpy(), strncpy(), strcmp() & strncmp() which: - Are simple byte-at-a-time loops with no particular optimizations. As a comment in the code describes, they're "rather naive". - Offer no clear performance advantage over the generic C implementations - in microbenchmarks performed by Alexander Lobakin the asm functions sometimes win & sometimes lose, but generally not by large margins in either direction. - Don't support 64-bit kernels, where we already make use of the generic C implementations. - Tend to bloat kernel code size due to inlining. - Don't support CONFIG_FORTIFY_SOURCE. - Won't support nanoMIPS without rework. For all of these reasons, delete the asm implementations & make use of the generic C implementations for 32-bit kernels just like we already do for 64-bit kernels. Signed-off-by: Paul Burton <[email protected]> URL: https://lore.kernel.org/linux-mips/[email protected]/ Cc: Alexander Lobakin <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Cc: [email protected]
2019-10-09MIPS: Provide unroll() macro, use it for cache opsPaul Burton3-343/+103
Currently we have a lot of duplication in asm/r4kcache.h to handle manually unrolling loops of cache ops for various line sizes, and we have to explicitly handle the difference in cache op immediate width between MIPSr6 & earlier ISA revisions with further duplication. Introduce an unroll() macro in asm/unroll.h which expands to a switch statement which is used to call a function or expand a preprocessor macro a compile-time constant number of times in a row - effectively explicitly unrolling a loop. We make use of this here to remove the cache op duplication & will use it further in later patches. A nice side effect of this is that calculating the cache op offset immediate is now the compiler's responsibility, so we're no longer sensitive to the width change of that immediate in MIPSr6 & will be similarly agnostic to immediate width in any future supported ISA. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected]
2019-10-09MIPS: fw: sni: Fix out of bounds init of o32 stackThomas Bogendoerfer1-1/+1
Use ARRAY_SIZE to caluculate the top of the o32 stack. Signed-off-by: Thomas Bogendoerfer <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected]
2019-10-09MIPS: include: Mark __xchg as __always_inlineThomas Bogendoerfer1-2/+2
Commit ac7c3e4ff401 ("compiler: enable CONFIG_OPTIMIZE_INLINING forcibly") allows compiler to uninline functions marked as 'inline'. In cace of __xchg this would cause to reference function __xchg_called_with_bad_pointer, which is an error case for catching bugs and will not happen for correct code, if __xchg is inlined. Signed-off-by: Thomas Bogendoerfer <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected]
2019-10-08MIPS: generic: Use __initconst for const init dataTiezhu Yang1-3/+3
Fix the following checkpatch errors: $ ./scripts/checkpatch.pl --no-tree -f arch/mips/generic/init.c ERROR: Use of const init definition must use __initconst #23: FILE: arch/mips/generic/init.c:23: +static __initdata const void *fdt; ERROR: Use of const init definition must use __initconst #24: FILE: arch/mips/generic/init.c:24: +static __initdata const struct mips_machine *mach; ERROR: Use of const init definition must use __initconst #25: FILE: arch/mips/generic/init.c:25: +static __initdata const void *mach_match_data; Fixes: eed0eabd12ef ("MIPS: generic: Introduce generic DT-based board support") Signed-off-by: Tiezhu Yang <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2019-10-07MIPS: futex: Restore \n after sync instructionsPaul Burton1-3/+3
Commit 3c1d3f097972 ("MIPS: futex: Emit Loongson3 sync workarounds within asm") inadvertently removed the newlines following __WEAK_LLSC_MB, which causes build failures for configurations in which __WEAK_LLSC_MB expands to a sync instruction: {standard input}: Assembler messages: {standard input}:9346: Error: symbol `sync3' is already defined {standard input}:9380: Error: symbol `sync3' is already defined ... Fix this by restoring the newlines to separate the sync instruction from anything following it (such as the 3: label), preventing inadvertent concatenation. Signed-off-by: Paul Burton <[email protected]> Fixes: 3c1d3f097972 ("MIPS: futex: Emit Loongson3 sync workarounds within asm")
2019-10-07mips: check for dsp presence only once before save/restoreAurabindo Jayamohanan1-4/+4
{save,restore}_dsp() internally checks if the cpu has dsp support. Therefore, explicit check is not required before calling them in {save,restore}_processor_state() Signed-off-by: Aurabindo Jayamohanan <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2019-10-07MIPS: PCI: use information from 1-wire PROM for IOC3 detectionThomas Bogendoerfer4-8/+175
IOC3 chips in SGI system are conntected to a bridge ASIC, which has a 1-wire prom attached with part number information. This changeset uses this information to create PCI subsystem information, which the MFD driver uses for further platform device setup. Signed-off-by: Thomas Bogendoerfer <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: Jonathan Corbet <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: Lee Jones <[email protected]> Cc: David S. Miller <[email protected]> Cc: Srinivas Kandagatla <[email protected]> Cc: Alessandro Zummo <[email protected]> Cc: Alexandre Belloni <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: Jiri Slaby <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2019-10-07MIPS: CI20: DTS: Add LedsAlexandre GRIVEAUX1-0/+28
Adding leds and related triggers. Signed-off-by: Alexandre GRIVEAUX <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2019-10-07MIPS: CI20: DTS: Add IW8103 Wifi + bluetoothAlexandre GRIVEAUX1-0/+39
Add IW8103 Wifi + bluetooth module to device tree and related power domain. Signed-off-by: Alexandre GRIVEAUX <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2019-10-07MIPS: CI20: DTS: Add I2C nodesAlexandre GRIVEAUX1-0/+147
Adding missing I2C nodes and some peripheral: - PMU - RTC Signed-off-by: Alexandre GRIVEAUX <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2019-10-07MIPS: JZ4780: DTS: Add I2C nodesAlexandre GRIVEAUX1-0/+86
Add the devicetree nodes for the I2C core of the JZ4780 SoC, disabled by default. Signed-off-by: Alexandre GRIVEAUX <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2019-10-07mips: Kconfig: Add ARCH_HAS_FORTIFY_SOURCEDmitry Korotin2-0/+3
FORTIFY_SOURCE detects various overflows at compile and run time. (6974f0c4555e ("include/linux/string.h: add the option of fortified string.h functions) ARCH_HAS_FORTIFY_SOURCE means that the architecture can be built and run with CONFIG_FORTIFY_SOURCE. Since mips can be built and run with that flag, select ARCH_HAS_FORTIFY_SOURCE as default. Signed-off-by: Dmitry Korotin <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: [email protected]
2019-10-07MIPS: Loongson-3: Add CSR IPI supportHuacai Chen1-8/+62
CSR IPI and legacy MMIO use the same infrastructure, but CSR IPI is faster than legacy MMIO IPI. This patch enable CSR IPI if possible (except for MailBox, because CSR IPI is too complicated for MailBox). Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected] Cc: Fuxin Zhang <[email protected]> Cc: Zhangjin Wu <[email protected]> Cc: Huacai Chen <[email protected]>
2019-10-07MIPS: Loongson: Add Loongson-3A R4 basic supportHuacai Chen7-50/+96
All Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3A R2.1 Loongson-3A2000 0x630c Loongson-3A R3 Loongson-3A3000 0x6309 Loongson-3A R3.1 Loongson-3A3000 0x630d Loongson-3A R4 Loongson-3A4000 0xc000 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R4 revision of Loongson-3A: - All R2/R3 features, including SFB, V-Cache, FTLB, RIXI, DSP, etc. - Support variable ASID bits. - Support MSA and VZ extensions. - Support CPUCFG (CPU config) and CSR (Control and Status Register) extensions. - 64 entries of VTLB (classic TLB), 2048 entries of FTLB (8-way set-associative). Now 64-bit Loongson processors has three types of PRID.IMP: 0x6300 is the classic one so we call it PRID_IMP_LOONGSON_64C (e.g., Loongson-2E/ 2F/3A1000/3B1000/3B1500/3A2000/3A3000), 0x6100 is for some processors which has reduced capabilities so we call it PRID_IMP_LOONGSON_64R (e.g., Loongson-2K), 0xc000 is supposed to cover all new processors in general (e.g., Loongson-3A4000+) so we call it PRID_IMP_LOONGSON_64G. Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected] Cc: Fuxin Zhang <[email protected]> Cc: Zhangjin Wu <[email protected]> Cc: Huacai Chen <[email protected]>
2019-10-07MIPS: Loongson: Add CFUCFG&CSR supportHuacai Chen1-0/+227
Loongson-3A R4+ (Loongson-3A4000 and newer) has CPUCFG (CPU config) and CSR (Control and Status Register) extensions. This patch add read/write functionalities for them. Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected] Cc: Fuxin Zhang <[email protected]> Cc: Zhangjin Wu <[email protected]> Cc: Huacai Chen <[email protected]>
2019-10-07mips: sgi-ip27: switch from DISCONTIGMEM to SPARSEMEMMike Rapoport2-14/+4
The memory initialization of SGI-IP27 is already half-way to support SPARSEMEM. It only had free_bootmem_with_active_regions() left-overs interfering with sparse_memory_present_with_active_regions(). Replace these calls with simpler memblocks_present() call in prom_meminit() and adjust arch/mips/Kconfig to enable SPARSEMEM and SPARSEMEM_EXTREME for SGI-IP27. Co-developed-by: Thomas Bogendoerfer <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]> Signed-off-by: Mike Rapoport <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: [email protected]
2019-10-07MIPS: Check Loongson3 LL/SC errata workaround correctnessPaul Burton5-1/+325
When Loongson3 LL/SC errata workarounds are enabled (ie. CONFIG_CPU_LOONGSON3_WORKAROUNDS=y) run a tool to scan through the compiled kernel & ensure that the workaround is applied correctly. That is, ensure that: - Every LL or LLD instruction is preceded by a sync instruction. - Any branches from within an LL/SC loop to outside of that loop target a sync instruction. Reasoning for these conditions can be found by reading the comment above the definition of __SYNC_loongson3_war in arch/mips/include/asm/sync.h. This tool will help ensure that we don't inadvertently introduce code paths that miss the required workarounds. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected]
2019-10-07MIPS: genex: Don't reload address unnecessarilyPaul Burton1-2/+2
In ejtag_debug_handler() we must reload the address of ejtag_debug_buffer_spinlock if an sc fails, since the address in k0 will have been clobbered by the result of the sc instruction. In the case where we simply load a non-zero value (ie. there's contention for the lock) the address will not be clobbered & we can simply branch back to repeat the load from memory without reloading the address into k0. The primary motivation for this change is that it moves the target of the bnez instruction to an instruction within the LL/SC loop (the LL itself), which we know contains no other memory accesses & therefore isn't affected by Loongson3 LL/SC errata. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected]
2019-10-07MIPS: genex: Add Loongson3 LL/SC workaround to ejtag_debug_handlerPaul Burton1-0/+2
In ejtag_debug_handler we use LL & SC instructions to acquire & release an open-coded spinlock. For Loongson3 systems affected by LL/SC errata this requires that we insert a sync instruction prior to the LL in order to ensure correct behavior of the LL/SC loop. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected]
2019-10-07MIPS: barrier: Make __smp_mb__before_atomic() a no-op for Loongson3Paul Burton1-1/+11
Loongson3 systems with CONFIG_CPU_LOONGSON3_WORKAROUNDS enabled already emit a full completion barrier as part of the inline assembly containing LL/SC loops for atomic operations. As such the barrier emitted by __smp_mb__before_atomic() is redundant, and we can remove it. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected]
2019-10-07MIPS: barrier: Remove loongson_llsc_mb()Paul Burton2-41/+1
The loongson_llsc_mb() macro is no longer used - instead barriers are emitted as part of inline asm using the __SYNC() macro. Remove the now-defunct loongson_llsc_mb() macro. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected]
2019-10-07MIPS: syscall: Emit Loongson3 sync workarounds within asmPaul Burton1-1/+2
Generate the sync instructions required to workaround Loongson3 LL/SC errata within inline asm blocks, which feels a little safer than doing it from C where strictly speaking the compiler would be well within its rights to insert a memory access between the separate asm statements we previously had, containing sync & ll instructions respectively. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected]
2019-10-07MIPS: futex: Emit Loongson3 sync workarounds within asmPaul Burton2-14/+14
Generate the sync instructions required to workaround Loongson3 LL/SC errata within inline asm blocks, which feels a little safer than doing it from C where strictly speaking the compiler would be well within its rights to insert a memory access between the separate asm statements we previously had, containing sync & ll instructions respectively. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected]
2019-10-07MIPS: cmpxchg: Omit redundant barriers for Loongson3Paul Burton1-3/+23
When building a kernel configured to support Loongson3 LL/SC workarounds (ie. CONFIG_CPU_LOONGSON3_WORKAROUNDS=y) the inline assembly in __xchg_asm() & __cmpxchg_asm() already emits completion barriers, and as such we don't need to emit extra barriers from the xchg() or cmpxchg() macros. Add compile-time constant checks causing us to omit the redundant memory barriers. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected]
2019-10-07MIPS: cmpxchg: Emit Loongson3 sync workarounds within asmPaul Burton1-7/+6
Generate the sync instructions required to workaround Loongson3 LL/SC errata within inline asm blocks, which feels a little safer than doing it from C where strictly speaking the compiler would be well within its rights to insert a memory access between the separate asm statements we previously had, containing sync & ll instructions respectively. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected]
2019-10-07MIPS: bitops: Use smp_mb__before_atomic in test_* opsPaul Burton1-3/+3
Use smp_mb__before_atomic() rather than smp_mb__before_llsc() in test_and_set_bit(), test_and_clear_bit() & test_and_change_bit(). The _atomic() versions make semantic sense in these cases, and will allow a later patch to omit redundant barriers for Loongson3 systems that already include a barrier within __test_bit_op(). Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected]
2019-10-07MIPS: bitops: Emit Loongson3 sync workarounds within asmPaul Burton1-9/+2
Generate the sync instructions required to workaround Loongson3 LL/SC errata within inline asm blocks, which feels a little safer than doing it from C where strictly speaking the compiler would be well within its rights to insert a memory access between the separate asm statements we previously had, containing sync & ll instructions respectively. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected]
2019-10-07MIPS: bitops: Use BIT_WORD() & BITS_PER_LONGPaul Burton3-34/+25
Rather than using custom SZLONG_LOG & SZLONG_MASK macros to shift & mask a bit index to form word & bit offsets respectively, make use of the standard BIT_WORD() & BITS_PER_LONG macros for the same purpose. volatile is added to the definition of pointers to the long-sized word we'll operate on, in order to prevent the compiler complaining that we cast away the volatile qualifier of the addr argument. This should have no effect on generated code, which in the LL/SC case is inline asm anyway & in the non-LLSC case access is constrained by compiler barriers provided by raw_local_irq_{save,restore}(). Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected]
2019-10-07MIPS: bitops: Abstract LL/SC loopsPaul Burton1-204/+63
Introduce __bit_op() & __test_bit_op() macros which abstract away the implementation of LL/SC loops. This cuts down on a lot of duplicate boilerplate code, and also allows R10000_LLSC_WAR to be handled outside of the individual bitop functions. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected]
2019-10-07MIPS: bitops: Avoid redundant zero-comparison for non-LLSCPaul Burton1-6/+12
The IRQ-disabling non-LLSC fallbacks for bitops on UP systems already return a zero or one, so there's no need to perform another comparison against zero. Move these comparisons into the LLSC paths to avoid the redundant work. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected]
2019-10-07MIPS: bitops: Use the BIT() macroPaul Burton1-15/+16
Use the BIT() macro in asm/bitops.h rather than open-coding its equivalent. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected]
2019-10-07MIPS: bitops: Allow immediates in test_and_{set,clear,change}_bitPaul Burton1-6/+6
The logical operations or & xor used in the test_and_set_bit_lock(), test_and_clear_bit() & test_and_change_bit() functions currently force the value 1<<bit to be placed in a register. If the bit is compile-time constant & fits within the immediate field of an or/xor instruction (ie. 16 bits) then we can make use of the ori/xori instruction variants & avoid the use of an extra register. Add the extra "i" constraints in order to allow use of these immediate encodings. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected]
2019-10-07MIPS: bitops: Implement test_and_set_bit() in terms of _lock variantPaul Burton2-79/+13
The only difference between test_and_set_bit() & test_and_set_bit_lock() is memory ordering barrier semantics - the former provides a full barrier whilst the latter only provides acquire semantics. We can therefore implement test_and_set_bit() in terms of test_and_set_bit_lock() with the addition of the extra memory barrier. Do this in order to avoid duplicating logic. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Huacai Chen <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: [email protected]
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