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2014-05-30MIPS: uasm: Add lh uam instructionMarkos Chandras3-6/+9
It will be used later on by bpf-jit [[email protected]: Resolved conflict.] Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/6733/ Signed-off-by: Ralf Baechle <[email protected]>
2014-05-30MIPS: uasm: Add wsbh uasm instructionMarkos Chandras3-1/+4
It will be used later on by bpf-jit [[email protected]: Resolved conflict.] Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/6732/ Signed-off-by: Ralf Baechle <[email protected]>
2014-05-30MIPS: uasm: Add sltu uasm instructionMarkos Chandras3-1/+4
It will be used later on by bpf-jit [[email protected]: Resolved conflict.] Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/6731/ Signed-off-by: Ralf Baechle <[email protected]>
2014-05-30MIPS: uasm: Add sltiu uasm instructionMarkos Chandras3-4/+7
It will be used later on by bpf-jit [[email protected]: Resolved conflict.] Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/6730/ Signed-off-by: Ralf Baechle <[email protected]>
2014-05-30MIPS: uasm: Add jalr uasm instructionMarkos Chandras1-0/+1
It will be used later on by bpf-jit [[email protected]: Resolved conflict.] Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/6729/ Signed-off-by: Ralf Baechle <[email protected]>
2014-05-30MIPS: uasm: Add mfhi uasm instructionMarkos Chandras3-4/+8
It will be used later on by bpf-jit [[email protected]: Resolved conflict.] Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Cc: Markos Chandras <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/6728/ Signed-off-by: Ralf Baechle <[email protected]>
2014-05-30MIPS: uasm: Add divu uasm instructionMarkos Chandras3-1/+4
It will be used later on by bpf-jit [[email protected]: Resolved conflict.] Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/6727/ Signed-off-by: Ralf Baechle <[email protected]>
2014-05-30MIPS: uasm: Add srlv uasm instructionMarkos Chandras3-3/+6
It will be used later on by bpf-jit [[email protected]: Fixed conflict due to other preceeding conflicts.] Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/6726/ Signed-off-by: Ralf Baechle <[email protected]>
2014-05-30MIPS: uasm: Add sllv uasm instructionMarkos Chandras3-3/+6
It will be used later on by bpf-jit [[email protected]: Fixed conflict with 49e9529b9d43773307b8c73bd251b71784830c3d [MIPS: uasm: add jalr instruction]. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/6725/ Signed-off-by: Ralf Baechle <[email protected]>
2014-05-30MIPS: Export local_flush_icache_range for KVMJames Hogan1-0/+1
Export the local_flush_icache_range function pointer for GPL modules so that it can be used by KVM for syncing the icache after binary translation of trapping instructions. Signed-off-by: James Hogan <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: Gleb Natapov <[email protected]> Cc: [email protected] Cc: [email protected] Cc: Sanjay Lal <[email protected]> Acked-by: Ralf Baechle <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2014-05-30MIPS: uasm: Add u3u2u1 instruction buildersMarkos Chandras1-0/+7
It will be used later on by the sllv and srlv instructions. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/6723/ Signed-off-by: Ralf Baechle <[email protected]>
2014-05-29Merge branch 'wip-mips-pm' of https://github.com/paulburton/linux into ↵Ralf Baechle6-9/+100
mips-for-linux-next
2014-05-28MIPS: uasm: add MT ASE yield instructionPaul Burton2-1/+10
This patch allows use of the MT ASE yield instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <[email protected]>
2014-05-28MIPS: uasm: add wait instructionPaul Burton3-1/+4
This patch allows use of the wait instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <[email protected]>
2014-05-28MIPS: uasm: add sync instructionPaul Burton3-2/+5
This patch allows use of the sync instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <[email protected]>
2014-05-28MIPS: uasm: add jalr instructionPaul Burton2-4/+6
This patch allows use of the jalr instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <[email protected]>
2014-05-28MIPS: uasm: add a label variant of beqPaul Burton1-0/+8
This patch allows for use of the beq instruction with labels from uasm, much as bne & others already do. It will be used by a subsequent patch. Signed-off-by: Paul Burton <[email protected]>
2014-05-28MIPS: add kmap_noncoherent to wire a cached non-coherent TLB entryPaul Burton1-2/+12
This is identical to kmap_coherent apart from the cache coherency attribute used for the TLB entry, so kmap_coherent is abstracted to kmap_prot which is then called for both kmap_coherent & kmap_noncoherent. This will be used by a subsequent patch. Suggested-by: Leonid Yegoshin <[email protected]> Signed-off-by: Paul Burton <[email protected]>
2014-05-28MIPS: R46000: Fix Micro-assembler field overflow for R4600 V2Thomas Bogendoerfer1-2/+2
Fix uasm warning, which triggered because of workaround for R4600 V2 CPUs. Signed-off-by: Thomas Bogendoerfer <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6716/ Signed-off-by: Ralf Baechle <[email protected]>
2014-05-24MIPS: MT: Remove SMTC supportRalf Baechle3-103/+23
Nobody is maintaining SMTC anymore and there also seems to be no userbase. Which is a pity - the SMTC technology primarily developed by Kevin D. Kissell <[email protected]> is an ingenious demonstration for the MT ASE's power and elegance. Based on Markos Chandras <[email protected]> patch https://patchwork.linux-mips.org/patch/6719/ which while very similar did no longer apply cleanly when I tried to merge it plus some additional post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to merge once upon a time. Signed-off-by: Ralf Baechle <[email protected]>
2014-05-23MIPS: c-r4k: Call R4600_HIT_CACHEOP_WAR_IMPL only for 32 byte cache lines.Ralf Baechle1-1/+0
R4600_HIT_CACHEOP_WAR_IMPL is only needed on R4600 v1.6 and the R4600 has data cache lines that are always 32 bytes so the call is pointless in r4k_blast_dcache_page_dc64. Signed-off-by: Ralf Baechle <[email protected]>
2014-05-14MIPS: mm: Fix broken microMIPS kernel regression.Steven J. Hill2-4/+7
Commit f4ae17aa0f2122b52f642985b46210a1f2eceb0a [MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT] broke microMIPS kernel builds. This patch refactors that code similar to what was done for the 'clear_page' and 'copy_page' functions. Signed-off-by: Steven J. Hill <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6744/ Signed-off-by: Ralf Baechle <[email protected]>
2014-05-02MIPS: tlb-r4k: Add CPU PM callback to reconfigure TLBJames Hogan1-1/+33
Add a CPU power management callback for the r4k TLB which reconfigures it after the CPU leaves a powered down state. Signed-off-by: James Hogan <[email protected]> Signed-off-by: Paul Burton <[email protected]>
2014-05-02MIPS: c-r4k: Add CPU PM callback for coherencyJames Hogan1-0/+24
Implement a CPU power management callback for the r4k cache, to set up coherency again after leaving a powered down state. Signed-off-by: James Hogan <[email protected]> Signed-off-by: Paul Burton <[email protected]>
2014-04-18mips: export flush_icache_rangeKees Cook1-2/+2
The lkdtm module performs tests against executable memory ranges, so it needs to flush the icache for proper behaviors. Other architectures already export this, so do the same for MIPS. [[email protected]: relocate export sites] Signed-off-by: Kees Cook <[email protected]> Cc: Paul Gortmaker <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: Sanjay Lal <[email protected]> Cc: John Crispin <[email protected]> Cc: Sergei Shtylyov <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2014-03-31MIPS: Loongson: Add basic Loongson-3 CPU supportHuacai Chen3-2/+63
Basic Loongson-3 CPU support include CPU probing and TLB/cache initializing. Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Hongliang Tao <[email protected]> Signed-off-by: Hua Yan <[email protected]> Tested-by: Alex Smith <[email protected]> Reviewed-by: Alex Smith <[email protected]> Cc: John Crispin <[email protected]> Cc: Steven J. Hill <[email protected]> Cc: Aurelien Jarno <[email protected]> Cc: [email protected] Cc: Fuxin Zhang <[email protected]> Cc: Zhangjin Wu <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/6630 Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: Use current_cpu_type() instead of c->cputypeWu Zhangjin1-1/+1
If current_cpu_type() is pre-defined in cpu-feature-overrides.h, This may save about 10k for the compressed kernel image(vmlinuz). Signed-off-by: Wu Zhangjin <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/1901/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Add support for the M5150 processorLeonid Yegoshin2-0/+2
The M5150 core is a 32-bit MIPS RISC which implements the MIPS Architecture Release-5 in a 5-stage pipeline. In addition, it includes the MIPS Architecture Virtualization Module that enables virtualization of operating systems, which provides a scalable, trusted, and secure execution environment. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6596/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Extend DMA_MAYBE_COHERENT logic to DMA_NONCOHERENT useManuel Lauss2-5/+5
Setting DMA_MAYBE_COHERENT gives a platform the opportunity to select use of cache ops at boot. Signed-off-by: Manuel Lauss <[email protected]> Cc: Linux-MIPS <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/6575/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: mm: c-r4k: Flush scache to avoid cache aliasesLeonid Yegoshin1-0/+11
There is a chance for the secondary cache to have memory aliases. This can happen if the bootloader is in a non-EVA mode (or even in EVA mode but with different mapping from the kernel) and the kernel switching to EVA afterwards. It's best to flush the icache to avoid having the secondary CPUs fetching stale data from it. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2014-03-26MIPS: mm: c-r4k: Add support for flushing user pages from cacheMarkos Chandras1-2/+4
Use the userspace cache flushing functions if the interrupted process is a userspace one. Signed-off-by: Markos Chandras <[email protected]>
2014-03-26MIPS: mm: c-r4k: Build EVA {d,i}cache flushing functionsLeonid Yegoshin1-0/+47
Build EVA specific cache flushing functions (ie cachee). They will be used by a subsequent patch. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2014-03-26MIPS: mm: init: Add free_init_pages() callback for EVAMarkos Chandras1-1/+11
A core in EVA mode can have any possible segment mapping, so the default free_initmem_default() function may not always work as expected. Therefore, add a callback that platforms can use to free up the init section. Signed-off-by: Markos Chandras <[email protected]>
2014-03-26MIPS: Add cases for CPU_P5600James Hogan3-0/+3
Add a CPU_P5600 case to various switch statements, doing the same thing as for CPU_PROAPTIV. Signed-off-by: James Hogan <[email protected]> Reviewed-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6408/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Coherent Processing System SMP implementationPaul Burton1-1/+1
This patch introduces a new SMP implementation for systems implementing the MIPS Coherent Processing System architecture. The kernel will make use of the Coherence Manager, Cluster Power Controller & Global Interrupt Controller in order to detect, bring up & make use of other cores in the system. SMTC is not supported, so only a single TC per VPE in the system is used. That is, this option enables an SMVP style setup but across multiple cores. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6362/ Patchwork: https://patchwork.linux-mips.org/patch/6611/ Patchwork: https://patchwork.linux-mips.org/patch/6651/ Patchwork: https://patchwork.linux-mips.org/patch/6652/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-06MIPS: Add 1074K CPU support explicitly.Steven J. Hill3-1/+4
The 1074K is a multiprocessing coherent processing system (CPS) based on modified 74K cores. This patch makes the 1074K an actual unique CPU type, instead of a 74K derivative, which it is not. Signed-off-by: Steven J. Hill <[email protected]> Reviewed-by: Leonid Yegoshin <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6389/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-06MIPS: mm: c-r4k: Detect instruction cache aliasesMarkos Chandras1-3/+8
The *Aptiv cores can use the CONF7/IAR bit to detect if the core has hardware support to remove instruction cache aliasing. This also defines the CONF7/AR bit in order to avoid using the '16' magic number. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6499/ Signed-off-by: Ralf Baechle <[email protected]>
2014-01-30Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds17-38/+55
Pull MIPS updates from Ralf Baechle: "The most notable new addition inside this pull request is the support for MIPS's latest and greatest core called "inter/proAptiv". The patch series describes this core as follows. "The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit." The platform specific patches touch all 3 Broadcom families. It adds support for the new Broadcom/Netlogix XLP9xx Soc, building a common BCM63XX SMP kernel for all BCM63XX SoCs regardless of core type/count and full gpio button/led descriptions for BCM47xx. The rest of the series are cleanups and bug fixes that are MIPS generic and consist largely of changes that Imgtec/MIPS had published in their linux-mti-3.10.git stable tree. Random other cleanups and patches preparing code to be merged in 3.15" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits) mips: select ARCH_MIGHT_HAVE_PC_SERIO mips: delete non-required instances of include <linux/init.h> MIPS: KVM: remove shadow_tlb code MIPS: KVM: use common EHINV aware UNIQUE_ENTRYHI mips/ide: flush dcache also if icache does not snoop dcache MIPS: BCM47XX: fix position of cpu_wait disabling MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N> MIPS: introduce MIPS_L1_CACHE_SHIFT_<N> MIPS: ZBOOT: gather string functions into string.c arch/mips/pci: don't check resource with devm_ioremap_resource arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource bcma: gpio: don't cast u32 to unsigned long ssb: gpio: add own IRQ domain MIPS: BCM47XX: fix sparse warnings in board.c MIPS: BCM47XX: add board detection for Linksys WRT54GS V1 MIPS: BCM47XX: fix detection for some boards MIPS: BCM47XX: Enable buttons support on SSB MIPS: BCM47XX: Convert WNDR4500 to new syntax MIPS: BCM47XX: Use "timer" trigger for status LEDs ...
2014-01-24mips: delete non-required instances of include <linux/init.h>Paul Gortmaker12-12/+0
None of these files are actually using any __init type directives and hence don't need to include <linux/init.h>. Most are just a left over from __devinit and __cpuinit removal, or simply due to code getting copied from one driver to the next. Signed-off-by: Paul Gortmaker <[email protected]> Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/6320/
2014-01-22MIPS: improve checks for noncoherent DMAFelix Fietkau1-0/+2
Only one MIPS development board actually supports enabling/disabling DMA coherency at runtime, so it's not a good idea to push the overhead of checking that configuration setting onto every other supported target as well. Signed-off-by: Felix Fietkau <[email protected]> Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/5912/
2014-01-22MIPS: Add support for interAptiv coresLeonid Yegoshin2-0/+2
The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/6163/
2014-01-22MIPS: Add support for FTLBsLeonid Yegoshin1-7/+22
The Fixed Page Size TLB (FTLB) is a set-associative dual entry TLB. Its purpose is to reduce the number of TLB misses by increasing the effective TLB size and keep the implementation complexity to minimum levels. A supported core can have both VTLB and FTLB. Reviewed-by: James Hogan <[email protected]> Reviewed-by: Paul Burton <[email protected]> Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/6139/
2014-01-22MIPS: mm: Use the TLBINVF instruction to flush the VTLBLeonid Yegoshin1-6/+12
The TLBINVF instruction can be used to flush the entire VTLB. This eliminates the need for the TLBWI loop and improves performance. Reviewed-by: Paul Burton <[email protected]> Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/6138/
2014-01-22MIPS: Add support for the proAptiv coresLeonid Yegoshin3-0/+3
The proAptiv Multiprocessing System is a power efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The proAptiv Multiprocessing System combines a deep pipeline with multi-issue out of order execution for improved computational throughput. The proAptiv Multiprocessing System can contain one to six MIPS32r3 proAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/6134/
2014-01-22MIPS: mm: Move UNIQUE_ENTRYHI macro to a header fileMarkos Chandras2-8/+1
The UNIQUE_ENTRYHI definition was duplicated whenever there was the need to flush the TLB entries. We move this common definition to a header file. Signed-off-by: Markos Chandras <[email protected]> Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/6129/
2014-01-22MIPS: mm: c-r4k: Panic if IL or DL fields have a reserved valueMarkos Chandras1-8/+16
According to MIPS32 and MIPS64 PRA documents, a value of 7 in IL and DL fields is marked as "Reserved" so panic if the core uses this value in the config1 register. Also simplify the code a little bit. Signed-off-by: Markos Chandras <[email protected]> Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/5861/
2014-01-15MIPS: fix blast_icache32 on loongson2Aaro Koskinen1-0/+7
Commit 14bd8c082016 ("MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips") failed to add Loongson2 specific blast_icache32 functions. Fix that. The patch fixes the following crash seen with 3.13-rc1: Reserved instruction in kernel code[#1]: [...] Call Trace: blast_icache32_page+0x8/0xb0 r4k_flush_cache_page+0x19c/0x200 do_wp_page.isra.97+0x47c/0xe08 handle_mm_fault+0x938/0x1118 __do_page_fault+0x140/0x540 resume_userspace_check+0x0/0x10 Code: 00200825 64834000 00200825 <bc900000> bc900020 bc900040 bc900060 bc900080 bc9000a0 Signed-off-by: Aaro Koskinen <[email protected]> Reviewed-by: Aurelien Jarno <[email protected]> Acked-by: John Crispin <[email protected]> Cc: Ralf Baechle <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2014-01-15MIPS: fix case mismatch in local_r4k_flush_icache_range()Huacai Chen1-2/+2
Currently, Loongson-2 call protected_blast_icache_range() and others call protected_loongson23_blast_icache_range(), but I think the correct behavior should be the opposite. BTW, Loongson-3's cache-ops is compatible with MIPS64, but not compatible with Loongson-2. So, rename xxx_loongson23_yyy things to xxx_loongson2_yyy. The patch fixes early boot hang with 3.13-rc1, introduced in commit 14bd8c082016 ("MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips"). Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Aaro Koskinen <[email protected]> Reviewed-by: Aurelien Jarno <[email protected]> Acked-by: John Crispin <[email protected]> Cc: Ralf Baechle <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2013-11-12Merge branch 'sched-core-for-linus' of ↵Linus Torvalds1-3/+2
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull scheduler changes from Ingo Molnar: "The main changes in this cycle are: - (much) improved CONFIG_NUMA_BALANCING support from Mel Gorman, Rik van Riel, Peter Zijlstra et al. Yay! - optimize preemption counter handling: merge the NEED_RESCHED flag into the preempt_count variable, by Peter Zijlstra. - wait.h fixes and code reorganization from Peter Zijlstra - cfs_bandwidth fixes from Ben Segall - SMP load-balancer cleanups from Peter Zijstra - idle balancer improvements from Jason Low - other fixes and cleanups" * 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (129 commits) ftrace, sched: Add TRACE_FLAG_PREEMPT_RESCHED stop_machine: Fix race between stop_two_cpus() and stop_cpus() sched: Remove unnecessary iteration over sched domains to update nr_busy_cpus sched: Fix asymmetric scheduling for POWER7 sched: Move completion code from core.c to completion.c sched: Move wait code from core.c to wait.c sched: Move wait.c into kernel/sched/ sched/wait: Fix __wait_event_interruptible_lock_irq_timeout() sched: Avoid throttle_cfs_rq() racing with period_timer stopping sched: Guarantee new group-entities always have weight sched: Fix hrtimer_cancel()/rq->lock deadlock sched: Fix cfs_bandwidth misuse of hrtimer_expires_remaining sched: Fix race on toggling cfs_bandwidth_used sched: Remove extra put_online_cpus() inside sched_setaffinity() sched/rt: Fix task_tick_rt() comment sched/wait: Fix build breakage sched/wait: Introduce prepare_to_wait_event() sched/wait: Add ___wait_cond_timeout() to wait_event*_timeout() too sched: Remove get_online_cpus() usage sched: Fix race in migrate_swap_stop() ...
2013-10-29MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips.Ralf Baechle3-119/+139
It was ugly. Signed-off-by: Ralf Baechle <[email protected]>
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