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2015-01-16MIPS: Fix restart of indirect syscallsEd Swierk2-0/+2
When 32-bit MIPS userspace invokes a syscall indirectly via syscall(number, arg1, ..., arg7), the kernel looks up the actual syscall based on the given number, shifts the other arguments to the left, and jumps to the syscall. If the syscall is interrupted by a signal and indicates it needs to be restarted by the kernel (by returning ERESTARTNOINTR for example), the syscall must be called directly, since the number is no longer the first argument, and the other arguments are now staged for a direct call. Before shifting the arguments, store the syscall number in pt_regs->regs[2]. This gets copied temporarily into pt_regs->regs[0] after the syscall returns. If the syscall needs to be restarted, handle_signal()/do_signal() copies the number back to pt_regs->reg[2], which ends up in $v0 once control returns to userspace. Signed-off-by: Ed Swierk <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8929/ Signed-off-by: Ralf Baechle <[email protected]>
2015-01-15MIPS: ELF: fix loading o32 binaries on 64-bit kernelsJames Cowgill1-4/+4
Commit 90cee759f08a ("MIPS: ELF: Set FP mode according to .MIPS.abiflags") introduced checking of the .MIPS.abiflags ELF section but did so through the native sized "elfhdr" and "elf_phdr" structures regardless whether the ELF was actually 32-bit or 64-bit. This produces wrong results when trying to use a 64-bit kernel to load o32 ELF files. Change the uses of the generic elf structures to their 32-bit versions. Since the code bails out on any 64-bit cases, this is OK until they are implemented. Fixes: 90cee759f08a ("MIPS: ELF: Set FP mode according to .MIPS.abiflags") Signed-off-by: James Cowgill <[email protected]> Cc: [email protected] Cc: Paul Burton <[email protected]> Reviewed-by: Maciej W. Rozycki <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/8932/ Signed-off-by: Ralf Baechle <[email protected]>
2015-01-13MIPS: Wire up execveat(2).Ralf Baechle4-0/+4
Signed-off-by: Ralf Baechle <[email protected]>
2014-12-12MIPS: Use phys_addr_t instead of phys_tJaedon Shin1-1/+1
Ralf Baechle says: "This should have been part of the merge commit c0222ac08666 (Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/- ralf/upstream-linus) but I forgot to mention the need for this in my pull request" Signed-off-by: Jaedon Shin <[email protected]> Signed-off-by: Ralf Baechle <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2014-12-11Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds26-700/+550
Pull MIPS updates from Ralf Baechle: "This is an unusually large pull request for MIPS - in parts because lots of patches missed the 3.18 deadline but primarily because some folks opened the flood gates. - Retire the MIPS-specific phys_t with the generic phys_addr_t. - Improvments for the backtrace code used by oprofile. - Better backtraces on SMP systems. - Cleanups for the Octeon platform code. - Cleanups and fixes for the Loongson platform code. - Cleanups and fixes to the firmware library. - Switch ATH79 platform to use the firmware library. - Grand overhault to the SEAD3 and Malta interrupt code. - Move the GIC interrupt code to drivers/irqchip - Lots of GIC cleanups and updates to the GIC code to use modern IRQ infrastructures and features of the kernel. - OF documentation updates for the GIC bindings - Move GIC clocksource driver to drivers/clocksource - Merge GIC clocksource driver with clockevent driver. - Further updates to bring the GIC clocksource driver up to date. - R3000 TLB code cleanups - Improvments to the Loongson 3 platform code. - Convert pr_warning to pr_warn. - Merge a bunch of small lantiq and ralink fixes that have been staged/lingering inside the openwrt tree for a while. - Update archhelp for IP22/IP32 - Fix a number of issues for Loongson 1B. - New clocksource and clockevent driver for Loongson 1B. - Further work on clk handling for Loongson 1B. - Platform work for Broadcom BMIPS. - Error handling cleanups for TurboChannel. - Fixes and optimization to the microMIPS support. - Option to disable the FTLB. - Dump more relevant information on machine check exception - Change binfmt to allow arch to examine PT_*PROC headers - Support for new style FPU register model in O32 - VDSO randomization. - BCM47xx cleanups - BCM47xx reimplement the way the kernel accesses NVRAM information. - Random cleanups - Add support for ATH25 platforms - Remove pointless locking code in some PCI platforms. - Some improvments to EVA support - Minor Alchemy cleanup" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (185 commits) MIPS: Add MFHC0 and MTHC0 instructions to uasm. MIPS: Cosmetic cleanups of page table headers. MIPS: Add CP0 macros for extended EntryLo registers MIPS: Remove now unused definition of phys_t. MIPS: Replace use of phys_t with phys_addr_t. MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT PCMCIA: Alchemy Don't select 64BIT_PHYS_ADDR in Kconfig. MIPS: lib: memset: Clean up some MIPS{EL,EB} ifdefery MIPS: iomap: Use __mem_{read,write}{b,w,l} for MMIO MIPS: <asm/types.h> fix indentation. MAINTAINERS: Add entry for BMIPS multiplatform kernel MIPS: Enable VDSO randomization MIPS: Remove a temporary hack for debugging cache flushes in SMTC configuration MIPS: Remove declaration of obsolete arch_init_clk_ops() MIPS: atomic.h: Reformat to fit in 79 columns MIPS: Apply `.insn' to fixup labels throughout MIPS: Fix microMIPS LL/SC immediate offsets MIPS: Kconfig: Only allow 32-bit microMIPS builds MIPS: signal.c: Fix an invalid cast in ISA mode bit handling MIPS: mm: Only build one microassembler that is suitable ...
2014-11-24MIPS: Replace use of phys_t with phys_addr_t.Ralf Baechle3-13/+13
Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Enable VDSO randomizationPrem Karat1-1/+14
Based on commit 1091458d09e1a (mmap randomization) For 32-bit address spaces randomize within a 16MB space, for 64-bit within a 256MB space. Test Results: ------------ Without Patch (VDSO is not randomized) --------------------------------------- root@Maleo:~# ./aslr vdso FAIL: ASLR not functional (vdso always at 0x7fff7000) root@Maleo:~# ./aslr rekey vdso pre_val==cur_val value=0x7fff7000 With patch:(VDSO is randmoized and doesn't interfere with stack) ---------------------------------------------------------------- root@cavium-octeon2:~# ./aslr rekey vdso pre_val!=cur_val previous_value=0x7f830ea2 current_value=0x776e2000 root@cavium-octeon2:~# ./aslr rekey vdso pre_val!=cur_val previous_value=0x7fb0cea2 current_value=0x77209000 root@cavium-octeon2:~# ./aslr rekey vdso pre_val!=cur_val previous_value=0x7f985ea2 current_value=0x7770c000 root@cavium-octeon2:~# ./aslr rekey vdso pre_val!=cur_val previous_value=0x7fbc6ea2 current_value=0x7fe25000 Maps file output: ------------------------- root@cavium-octeon2:~# ./aslr rekey maps 78584000-785a5000 rwxp 00000000 00:00 0 [heap] 7f9d0000-7f9f1000 rw-p 00000000 00:00 0 [stack] 7ffa5000-7ffa6000 r-xp 00000000 00:00 0 [vdso] root@cavium-octeon2:~# ./aslr rekey maps 77de0000-77e01000 rwxp 00000000 00:00 0 [heap] 7f91b000-7f93c000 rw-p 00000000 00:00 0 [stack] 7ff99000-7ff9a000 r-xp 00000000 00:00 0 [vdso] root@cavium-octeon2:~# ./aslr rekey maps 77d7f000-77da0000 rwxp 00000000 00:00 0 [heap] 7fc2a000-7fc4b000 rw-p 00000000 00:00 0 [stack] 7fe09000-7fe0a000 r-xp 00000000 00:00 0 [vdso] root@cavium-octeon2:~# ./aslr rekey maps 7794c000-7794d000 r-xp 00000000 00:00 0 [vdso] 77e4b000-77e6c000 rwxp 00000000 00:00 0 [heap] 7f6e7000-7f708000 rw-p 00000000 00:00 0 [stack] root@cavium-octeon2:~# Signed-off-by: Prem Karat <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6812 Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Apply `.insn' to fixup labels throughoutMaciej W. Rozycki1-0/+2
Fix the issue with the ISA bit being lost in fixups that jump to labels placed just before a section switch. Such a switch leads to the ISA bit being lost, because GAS concludes there is no code that follows and therefore the label refers to data. Use the `.insn' pseudo-op to convince the tool this is not the case. This lack of label annotation leads to microMIPS compilation errors like: mips-linux-gnu-ld: arch/mips/built-in.o: .fixup+0x3b8: Unsupported jump between ISA modes; consider recompiling with interlinking enabled. mips-linux-gnu-ld: final link failed: Bad value Signed-off-by: Maciej W. Rozycki <[email protected]> Signed-off-by: Steven J. Hill <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8483/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: signal.c: Fix an invalid cast in ISA mode bit handlingMaciej W. Rozycki1-1/+1
Fix: arch/mips/kernel/signal.c: In function 'handle_signal': arch/mips/kernel/signal.c:533:21: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] unsigned int tmp = (unsigned int)current->mm->context.vdso; ^ arch/mips/kernel/signal.c:536:9: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] vdso = (void *)tmp; ^ cc1: all warnings being treated as errors when building a 64-bit kernel. This is not really a supported configuration, but the cast is wrong either way, Linux makes the assumption that sizeof(void *) equals sizeof(unsigned long) and therefore the latter type is expected to be used where integer operations have to be applied to pointers for some reason. Signed-off-by: Maciej W. Rozycki <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8480/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: traps: Dump the PageGrain and Wired registers on MCMarkos Chandras1-0/+2
They can be useful to determine how the MMU is configured on a MC exception. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8401/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: traps: Dump the HTW registers on a MC exceptionMarkos Chandras1-0/+5
The HTW registers can be useful to debug a MC exception. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8400/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: traps: Replace printk with pr_err for MC exceptionsMarkos Chandras1-6/+6
printk should not be used without a KERN_ facility level Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8399/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24clocksource: mips-gic: Combine with GIC clockevent driverAndrew Bresticker2-104/+0
Combine the GIC clocksource driver with the GIC clockevent driver from arch/mips/kernel/cevt-gic.c and remove the clockevent driver's separate Kconfig symbol. Signed-off-by: Andrew Bresticker <[email protected]> Cc: Daniel Lezcano <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Jason Cooper <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: Paul Burton <[email protected]> Cc: Qais Yousef <[email protected]> Cc: John Crispin <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8132/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Move GIC clocksource driver to drivers/clocksource/Andrew Bresticker2-33/+0
Move the GIC clocksource driver to drivers/clocksource/mips-gic-timer.c. Signed-off-by: Andrew Bresticker <[email protected]> Cc: Daniel Lezcano <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Jason Cooper <[email protected]> Cc: Paul Burton <[email protected]> Cc: Qais Yousef <[email protected]> Cc: John Crispin <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8133/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Create a helper function for DT setupKevin Cernekee1-0/+18
A couple of platforms register two buses and call of_platform_populate(). Move this into a common function to reduce duplication. Signed-off-by: Kevin Cernekee <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8167/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind)Kevin Cernekee1-0/+1
This is a dual core (quad thread) BMIPS5000. It needs a little extra code to boot the second core (CPU2/CPU3), but for now we can treat it the same as a single core BMIPS5000. Signed-off-by: Kevin Cernekee <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8166/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: BMIPS: Let each platform customize the CPU1 IRQ maskKevin Cernekee1-2/+4
On some chips like bcm3384, "other stuff" gets wired up to CPU1's IE_IRQ1 input, generating spurious IRQs. In this case we want the platform code to be able to mask it off. Signed-off-by: Kevin Cernekee <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8163/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: BMIPS: Explicitly configure reset vectors prior to secondary bootKevin Cernekee1-21/+8
The secondary CPU's reset vector needs to be set to KSEG1 for a cold boot (release from reset), or KSEG0 for a warm restart. On a cold boot KSEG0 may be unavailable (BMIPS4380), and on a warm restart KSEG1 may be unavailable (XKS01 mode on 4380 or 5000). Signed-off-by: Kevin Cernekee <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8161/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: BMIPS: Mask off timer IRQs when hot-unplugging a CPUJon Fraser1-0/+1
CPU interrupts need to be disabled on a cpu being taken down. When a cpu is hot-plugged out of the system the following sequence occurs. On the CPU where the hotplug sequence was initiated: cpu_down _cpu_down { __cpu_notify(CPU_DOWN_PREPARE __stop_machine(take_cpu_down wait for cpu to run disable code. __cpu_die } On the CPU being disabled: take_cpu_down __cpu_disable { mp_ops->cpu_disable bmips_cpu_disable clear_c0_status(IE_IRQ5) (added) cpu_notify(CPU_DYING... } Before the cpu_notifier is called with CPU_DYING, all interrupts on the dying cpu must be disabled. This guarantees that before tick_notify is called with the CPU_DYING event and sets the clock device pointer to NULL, there can not be any more clock interrupts. When this wasn't done, an unfortunately-timed timer interrupt sometimes caused hangs immediately prior to system suspend: Debug PM is not enabled. To enable partial suspend, rebuild kernel with CONFIG_PM_DEBUG Pass 1 out of 1,PM: Syncing filesystems ... mode=none, tp1=done. 1, flags=5, cycle_tp=, sleep= Freezing user space processes ... (elapsed 0.01 seconds) done. Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done. PM: suspend of devices complete after 54.199 msecs PM: late suspend of devices complete after 0.172 msecs Disabling non-boot CPUs ... SMP: CPU1 is offline INFO: rcu_sched detected stalls on CPUs/tasks: { 3} (detected by 0, t=62537 jiffies) Call Trace: [<804baa78>] dump_stack+0x8/0x34 [<8008a2d8>] __rcu_pending+0x4b8/0x55c [<8008adf4>] rcu_check_callbacks+0x78/0x180 [<80037830>] update_process_times+0x40/0x6c [<80072fe4>] tick_sched_timer+0x74/0xe4 [<80050180>] __run_hrtimer.clone.30+0x64/0x140 [<80051150>] hrtimer_interrupt+0x19c/0x4bc [<8000cdb8>] c0_compare_interrupt+0x50/0x88 [<80081b18>] handle_irq_event_percpu+0x5c/0x2f4 [<80086490>] handle_percpu_irq+0x8c/0xc0 [<800811b4>] generic_handle_irq+0x34/0x54 [<800067dc>] do_IRQ+0x18/0x2c [<8000375c>] plat_irq_dispatch+0xd0/0x128 [<80004a04>] ret_from_irq+0x0/0x4 [<80004c40>] r4k_wait+0x20/0x40 [<80006b6c>] cpu_idle+0x98/0xf0 [<805d3988>] start_kernel+0x424/0x440 Signed-off-by: Jon Fraser <[email protected]> Signed-off-by: Kevin Cernekee <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8160/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: BMIPS: Allow BMIPS3300 to utilize SMP ebase relocation codeJon Fraser1-0/+1
BMIPS3300 processors do not have the hardware to support SMP, but with a small tweak, the SMP ebase relocation code allows BMIPS3300-based platforms to reuse the S2/S3 power management code from BMIPS4380-based chips. Normally this is as simple as adding one line to prom_init(): board_ebase_setup = &bmips_ebase_setup; Signed-off-by: Jon Fraser <[email protected]> Signed-off-by: Kevin Cernekee <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8159/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: BMIPS: Introduce helper function to change the reset vectorKevin Cernekee1-7/+58
This will need to be called from a few different places, and the logic is starting to get a bit hairy (with the need for IPIs, CPU bug workarounds, and hazards). Signed-off-by: Kevin Cernekee <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8158/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: BMIPS: Align secondary boot sequence with latest firmware releasesKevin Cernekee1-11/+1
On some older BMIPS5200 (dual core / quad thread) platforms, the PROM code set up CPU2/CPU3 so they would be started through an NMI instead of through the ACTION register. But this was incompatible with some power management features that were later added, so the scheme was changed so that Linux is fully responsible for booting CPU2/CPU3. Signed-off-by: Kevin Cernekee <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8157/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Kconfig option to better exercise/debug hybrid FPRsPaul Burton1-0/+18
The hybrid FPR scheme exists to allow for compatibility between existing FP32 code and newly compiled FP64A code. Such code should hopefully be rare in the real world, and for the moment is difficult to come across. All code except that built for the FP64 ABI can correctly execute using the hybrid FPR scheme, so debugging the hybrid FPR implementation can be eased by forcing all such code to use it. This is undesirable in general due to the trap & emulate overhead of the hybrid FPR implementation, but is a very useful option to have for debugging. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Alexander Viro <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7680/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: ELF: Set FP mode according to .MIPS.abiflagsPaul Burton2-3/+177
This patch reads the .MIPS.abiflags section when it is present, and sets the FP mode of the task accordingly. Any loaded ELF files which do not contain a .MIPS.abiflags section will continue to observe the previous behaviour, that is FR=1 if EF_MIPS_FP64 is set else FR=0. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Alexander Viro <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7681/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Support for hybrid FPRsPaul Burton1-0/+47
Hybrid FPRs is a scheme where scalar FP registers are 64b wide, but accesses to odd indexed single registers use bits 63:32 of the preceeding even indexed 64b register. In this mode all FP code except that built for the plain FP64 ABI can execute correctly. Most notably a combination of FP64A & FP32 code can execute correctly, allowing for existing FP32 binaries to be linked with new FP64A binaries that can make use of 64 bit FP & MSA. Hybrid FPRs are implemented by setting both the FR & FRE bits, trapping & emulating single precision FP instructions (via Reserved Instruction exceptions) whilst allowing others to execute natively. It therefore has a penalty in terms of execution speed, and should only be used when no fully native mode can be. As more binaries are recompiled to use either the FPXX or FP64(A) ABIs, the need for hybrid FPRs should diminish. However in the short to mid term it allows for a gradual transition towards that world, rather than a complete ABI break which is not feasible for some users & not desirable for many. A task will be executed using the hybrid FPR scheme when its TIF_HYBRID_FPREGS flag is set & TIF_32BIT_FPREGS is clear. A further patch will set the flags as necessary, this patch simply adds the infrastructure necessary for the hybrid FPR mode to work. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Alexander Viro <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7683/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Ensure Config5.UFE is clear on bootPaul Burton1-1/+1
As is done for UFR, ensure that userland cannot directly manipulate the mode by clearing the UFE bit during boot. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Alexander Viro <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7677/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: detect presence of the FRE & UFR bitsPaul Burton1-0/+2
Detect the presence of the Config5 FRE & UFE bits, as indicated by the FREP bit in FPIR. Record this as a CPU option bit, and provide a cpu_has_fre macro to ease checking of that option bit. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Alexander Viro <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7678/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Remove __strlen_user().Ralf Baechle1-4/+0
Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Move gic.h to include/linux/irqchip/mips-gic.hAndrew Bresticker7-8/+7
Now that the MIPS GIC irqchip lives in drivers/irqchip/, move its header over to include/linux/irqchip/. Signed-off-by: Andrew Bresticker <[email protected]> Cc: Daniel Lezcano <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Jason Cooper <[email protected]> Cc: Paul Burton <[email protected]> Cc: Qais Yousef <[email protected]> Cc: John Crispin <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8129/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24irqchip: mips-gic: Export function to read counter widthAndrew Bresticker1-8/+1
Export the function gic_get_count_width to read the width of the GIC global counter from GIC_SH_CONFIG. Update the GIC clocksource driver to use this new function. Signed-off-by: Andrew Bresticker <[email protected]> Cc: Daniel Lezcano <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Jason Cooper <[email protected]> Cc: Paul Burton <[email protected]> Cc: Qais Yousef <[email protected]> Cc: John Crispin <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8124/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24irqchip: mips-gic: Support local interruptsAndrew Bresticker2-10/+7
The MIPS GIC supports 7 local interrupts, 2 of which are the GIC local watchdog and count/compare timer. The remainder are CPU interrupts which may optionally be re-routed through the GIC. GIC hardware IRQs 0-6 are now used for local interrupts while hardware IRQs 7+ are used for external (shared) interrupts. Note that the 5 CPU interrupts may not be re-routable through the GIC. In that case mapping will fail and the vectors reported in C0_IntCtl should be used instead. gic_get_c0_compare_int() and gic_get_c0_perfcount_int() will return the correct IRQ number to use for the C0 timer and perfcounter interrupts based on the routability of those interrupts through the GIC. A separate irq_chip, with callbacks that mask/unmask the local interrupt on all CPUs, is used for the C0 timer and performance counter interrupts since all other platforms do not use the percpu IRQ API for those interrupts. Malta, SEAD-3, and the GIC clockevent driver have been updated to use local interrupts and the R4K clockevent driver has been updated to poll for C0 timer interrupts through the GIC when the GIC is present. Signed-off-by: Andrew Bresticker <[email protected]> Acked-by: Jason Cooper <[email protected]> Reviewed-by: Qais Yousef <[email protected]> Tested-by: Qais Yousef <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Jeffrey Deans <[email protected]> Cc: Markos Chandras <[email protected]> Cc: Paul Burton <[email protected]> Cc: Jonas Gorski <[email protected]> Cc: John Crispin <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7819/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24irqchip: mips-gic: Stop using per-platform mapping tablesAndrew Bresticker1-1/+2
Now that the GIC properly uses IRQ domains, kill off the per-platform routing tables that were used to make the GIC appear transparent. This includes: - removing the mapping tables and the support for applying them, - moving GIC IPI support to the GIC driver, - properly routing the i8259 through the GIC on Malta, and - updating IRQ assignments on SEAD-3 when the GIC is present. Platforms no longer will pass an interrupt mapping table to gic_init. Instead, they will pass the CPU interrupt vector (2 - 7) that they expect the GIC to route interrupts to. Note that in EIC mode this value is ignored and all GIC interrupts are routed to EIC vector 1. Signed-off-by: Andrew Bresticker <[email protected]> Acked-by: Jason Cooper <[email protected]> Reviewed-by: Qais Yousef <[email protected]> Tested-by: Qais Yousef <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Jeffrey Deans <[email protected]> Cc: Markos Chandras <[email protected]> Cc: Paul Burton <[email protected]> Cc: Jonas Gorski <[email protected]> Cc: John Crispin <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7816/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Move GIC to drivers/irqchip/Andrew Bresticker4-406/+3
Move GIC irqchip support to drivers/irqchip/ and rename the Kconfig option from IRQ_GIC to MIPS_GIC to avoid confusion with the ARM GIC. Signed-off-by: Andrew Bresticker <[email protected]> Acked-by: Jason Cooper <[email protected]> Reviewed-by: Qais Yousef <[email protected]> Tested-by: Qais Yousef <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Jeffrey Deans <[email protected]> Cc: Markos Chandras <[email protected]> Cc: Paul Burton <[email protected]> Cc: Jonas Gorski <[email protected]> Cc: John Crispin <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7812/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: smp-cps: Enable all hardware interrupts on secondary CPUsAndrew Bresticker1-2/+2
Currently interrupt vectors 2 and 5 are left disabled on secondary CPUs. Since systems using CPS must also have a GIC, which is responsible for routing all external interrupts and can map them to any hardware interrupt vector, enable the remaining vectors. The two software interrupt vectors are left disabled since they are not used with CPS. Signed-off-by: Andrew Bresticker <[email protected]> Reviewed-by: Qais Yousef <[email protected]> Tested-by: Qais Yousef <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Jason Cooper <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: Jeffrey Deans <[email protected]> Cc: Markos Chandras <[email protected]> Cc: Paul Burton <[email protected]> Cc: Qais Yousef <[email protected]> Cc: Jonas Gorski <[email protected]> Cc: John Crispin <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7803/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Add hook to get C0 performance counter interruptAndrew Bresticker1-16/+7
The hardware perf event driver and oprofile interpret the global cp0_perfcount_irq differently: in the hardware perf event driver it is an offset from MIPS_CPU_IRQ_BASE and in oprofile it is the actual IRQ number. This still works most of the time since MIPS_CPU_IRQ_BASE is usually 0, but is clearly wrong. Since the performance counter interrupt may vary from platform to platform like the C0 timer interrupt, add the optional get_c0_perfcount_int hook which returns the IRQ number of the performance counter. The hook should return < 0 if the performance counter interrupt is shared with the timer. If the hook is not present, the CPU vector reported in C0_IntCtl (cp0_perfcount_irq) is used. Signed-off-by: Andrew Bresticker <[email protected]> Reviewed-by: Qais Yousef <[email protected]> Tested-by: Qais Yousef <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Jason Cooper <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: Jeffrey Deans <[email protected]> Cc: Markos Chandras <[email protected]> Cc: Paul Burton <[email protected]> Cc: Qais Yousef <[email protected]> Cc: Jonas Gorski <[email protected]> Cc: John Crispin <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7805/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: i8259: Use IRQ domainsAndrew Bresticker1-5/+19
Create a legacy IRQ domain for the 16 i8259 interrupts. Signed-off-by: Andrew Bresticker <[email protected]> Reviewed-by: Qais Yousef <[email protected]> Tested-by: Qais Yousef <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Jason Cooper <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: Jeffrey Deans <[email protected]> Cc: Markos Chandras <[email protected]> Cc: Paul Burton <[email protected]> Cc: Qais Yousef <[email protected]> Cc: Jonas Gorski <[email protected]> Cc: John Crispin <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7804/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Set vint handler when mapping CPU interruptsAndrew Bresticker1-0/+4
When mapping an interrupt in the CPU IRQ domain, set the vint handler for that interrupt if the CPU uses vectored interrupt handling. Signed-off-by: Andrew Bresticker <[email protected]> Reviewed-by: Qais Yousef <[email protected]> Tested-by: Qais Yousef <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Jason Cooper <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: Jeffrey Deans <[email protected]> Cc: Markos Chandras <[email protected]> Cc: Paul Burton <[email protected]> Cc: Qais Yousef <[email protected]> Cc: Jonas Gorski <[email protected]> Cc: John Crispin <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7802/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Provide a generic plat_irq_dispatchAndrew Bresticker1-0/+18
For platforms which boot with device-tree or have correctly chained all external interrupt controllers, a generic plat_irq_dispatch() can be used. Implement a plat_irq_dispatch() which simply handles all the pending interrupts as reported by C0_Cause. Signed-off-by: Andrew Bresticker <[email protected]> Reviewed-by: Qais Yousef <[email protected]> Tested-by: Qais Yousef <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Jason Cooper <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: Jeffrey Deans <[email protected]> Cc: Markos Chandras <[email protected]> Cc: Paul Burton <[email protected]> Cc: Qais Yousef <[email protected]> Cc: Jonas Gorski <[email protected]> Cc: John Crispin <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7801/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Rename mips_cpu_intc_init() -> mips_cpu_irq_of_init()Andrew Bresticker1-2/+2
mips_cpu_intc_init() is used for DT-based initialization of the CPU IRQ domain. Give it a more appropriate name. Signed-off-by: Andrew Bresticker <[email protected]> Reviewed-by: Qais Yousef <[email protected]> Tested-by: Qais Yousef <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Jason Cooper <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: Jeffrey Deans <[email protected]> Cc: Markos Chandras <[email protected]> Cc: Paul Burton <[email protected]> Cc: Qais Yousef <[email protected]> Cc: Jonas Gorski <[email protected]> Cc: John Crispin <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7800/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Always use IRQ domains for CPU IRQsAndrew Bresticker1-25/+11
Use an IRQ domain for the 8 CPU IRQs in both the DT and non-DT cases. Signed-off-by: Andrew Bresticker <[email protected]> Reviewed-by: Qais Yousef <[email protected]> Tested-by: Qais Yousef <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Jason Cooper <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: Jeffrey Deans <[email protected]> Cc: Markos Chandras <[email protected]> Cc: Paul Burton <[email protected]> Cc: Qais Yousef <[email protected]> Cc: Jonas Gorski <[email protected]> Cc: John Crispin <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7799/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: cpu: Add 'noftlb' kernel command line option to disable the FTLBMarkos Chandras1-2/+62
Add new 'noftlb' kernel command line option to disable the FTLB. Since the kernel command line is not available when probing and enabling the CPU features in cpu_probe(), we let the kernel configure the FTLB during the config4 decode operation and we disable the FTLB later on, once the command line has become available to us. This should have no negative effects since FTLB isn't used so early in the boot process. FTLB increases the effective TLB size leading to less TLB misses. However, sometimes it's useful to be able to disable it when debugging memory related core features or other hardware components. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/7586/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24mips: Convert pr_warning to pr_warnJoe Perches3-7/+6
Use the much more common pr_warn instead of pr_warning with the goal of removing pr_warning eventually. Other miscellanea: o Coalesce formats o Realign arguments Signed-off-by: Joe Perches <[email protected]> Cc: linux-mips <[email protected]> Cc: LKML <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/7935/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Add arch_trigger_all_cpu_backtrace() functionEunbong Song1-0/+18
Currently, arch_trigger_all_cpu_backtrace() is defined in only x86 and sparc which have an NMI. But in case of softlockup, it could be possible to dump backtrace of all cpus. and this could be helpful for debugging. for example, if system has 2 cpus. CPU 0 CPU 1 acquire read_lock() try to do write_lock() ,,, missing read_unlock() In this case, softlockup will occur becasuse CPU 0 does not call read_unlock(). And dump_stack() print only backtrace for "CPU 0". If CPU1's backtrace is printed it's very helpful. [[email protected]: Fixed whitespace and formatting issues.] Signed-off-by: Ralf Baechle <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8200/
2014-11-24MIPS: Remove useless parenthesesRalf Baechle3-20/+20
Based on the spatch @@ expression e; @@ - return (e); + return e; with heavy hand editing because some of the changes are either whitespace or identation only or result in excessivly long lines. Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Fix address type used for early memory detection.Steven J. Hill1-1/+1
In 'early_parse_mem' the data type used for the start and size of a memory region specified on the command line is incorrect. If 64-bit addressing is used, the value gets truncated. Signed-off-by: Steven J. Hill <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8456/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: kernel: cps-vec: Set ISA level to mips32r2 for the MIPS MT ASEMarkos Chandras1-0/+2
Fixes the following build warnings: arch/mips/kernel/cps-vec.S: Assembler messages: arch/mips/kernel/cps-vec.S:228: Warning: the `mt' extension requires MIPS32 revision 2 or greater [...] arch/mips/kernel/cps-vec.S: Assembler messages: arch/mips/kernel/cps-vec.S:345: Warning: the `mt' extension requires MIPS32 revision 2 or greater Signed-off-by: Markos Chandras <[email protected]> Cc: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7355/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: fix EVA & non-SMP non-FPU FP context signal handlingPaul Burton1-4/+4
The save_fp_context & restore_fp_context pointers were being assigned to the wrong variables if either: - The kernel is configured for UP & runs on a system without an FPU, since b2ead5282885 "MIPS: Move & rename fpu_emulator_{save,restore}_context". - The kernel is configured for EVA, since ca750649e08c "MIPS: kernel: signal: Prevent save/restore FPU context in user memory". This would lead to FP context being clobbered incorrectly when setting up a sigcontext, then the garbage values being saved uselessly when returning from the signal. Fix by swapping the pointer assignments appropriately. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] # v3.15+ Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8230/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: cpu-probe: Set the FTLB probability bit on supported coresMarkos Chandras1-1/+32
Make use of the Config6/FLTBP bit to set the probability of a TLBWR instruction to hit the FTLB or the VTLB. A value of 0 (which may be the default value on certain cores, such as proAptiv or P5600) means that a TLBWR instruction will never hit the VTLB which leads to performance limitations since it effectively decreases the number of available TLB slots. Signed-off-by: Markos Chandras <[email protected]> Reviewed-by: James Hogan <[email protected]> Cc: <[email protected]> # v3.15+ Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8368/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: BMIPS: Fix ".previous without corresponding .section" warningsKevin Cernekee1-3/+0
Commit 078a55fc824c1 ("Delete __cpuinit/__CPUINIT usage from MIPS code") removed our __CPUINIT directives, so now the ".previous" directives are superfluous. Remove them. Signed-off-by: Kevin Cernekee <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8156/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-24MIPS: Fix info about plat_setup in arch_mem_init commentRafał Miłecki1-1/+1
Signed-off-by: Rafał Miłecki <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7607/ Signed-off-by: Ralf Baechle <[email protected]>
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