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2017-07-11MIPS: Fix MIPS I ISA /proc/cpuinfo reportingMaciej W. Rozycki1-1/+1
Correct a commit 515a6393dbac ("MIPS: kernel: proc: Add MIPS R6 support to /proc/cpuinfo") regression that caused MIPS I systems to show no ISA levels supported in /proc/cpuinfo, e.g.: system type : Digital DECstation 2100/3100 machine : Unknown processor : 0 cpu model : R3000 V2.0 FPU V2.0 BogoMIPS : 10.69 wait instruction : no microsecond timers : no tlb_entries : 64 extra interrupt vector : no hardware watchpoint : no isa : ASEs implemented : shadow register sets : 1 kscratch registers : 0 package : 0 core : 0 VCED exceptions : not available VCEI exceptions : not available and similarly exclude `mips1' from the ISA list for any processors below MIPSr1. This is because the condition to show `mips1' on has been made `cpu_has_mips_r1' rather than newly-introduced `cpu_has_mips_1'. Use the correct condition then. Fixes: 515a6393dbac ("MIPS: kernel: proc: Add MIPS R6 support to /proc/cpuinfo") Signed-off-by: Maciej W. Rozycki <[email protected]> Reviewed-by: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected] # 3.19+ Patchwork: https://patchwork.linux-mips.org/patch/16758/ Signed-off-by: Ralf Baechle <[email protected]>
2017-07-11MIPS: MIPS16e2: Report ASE presence in /proc/cpuinfoMaciej W. Rozycki1-0/+1
Only now that both feature determination and unaligned emulation is in place add reporting to /proc/cpuinfo, so that the presence of "mips16e2" there not only indicates our recognition of the hardware feature, but correct unaligned emulation as well. Signed-off-by: Maciej W. Rozycki <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/16757/ Signed-off-by: Ralf Baechle <[email protected]>
2016-10-04MIPS: Move identification of VP(E) into proc.c from smp-mt.cMatt Redfearn1-0/+7
The addition of VPE information to /proc/cpuinfo used to be in smp-mt.c. This file is not used by MIPS r6 kernels, so the Virtual Processor information was not present for these CPU types. Move the code to print VPE information into proc.c, add a case for MIPS r6 CPUS, and remove the block from smp-mt.c. Signed-off-by: Matt Redfearn <[email protected]> Reviewed-by: Paul Burton <[email protected]> Cc: Qais Yousef <[email protected]> Cc: Zubair Lutfullah Kakakhel <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/13847/ Signed-off-by: Ralf Baechle <[email protected]>
2016-05-13MIPS: Detect DSP v3 supportZubair Lutfullah Kakakhel1-0/+1
DSPv3 is supported on all MIPSr6 systems which indicate support for DSPv2. This doesn't require any changes to the kernel's handling of DSP resources. The patch is to detect support and indicate it in /proc/cpuinfo DSP v3 introduces a new instruction BPOSGE32C Signed-off-by: Zubair Lutfullah Kakakhel <[email protected]> Reviewed-by: Paul Burton <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12918/ Signed-off-by: Ralf Baechle <[email protected]>
2015-03-19MIPS: Add support for XPA.Steven J. Hill1-0/+1
Add support for extended physical addressing (XPA) so that 32-bit platforms can access equal to or greater than 40 bits of physical addresses. NOTE: 1) XPA and EVA are not the same and cannot be used simultaneously. 2) If you configure your kernel for XPA, the PTEs and all address sizes become 64-bit. 3) Your platform MUST have working HIGHMEM support. Signed-off-by: Steven J. Hill <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/9355/ Signed-off-by: Ralf Baechle <[email protected]>
2015-02-17MIPS: kernel: proc: Add MIPS R6 support to /proc/cpuinfoMarkos Chandras1-1/+7
Print 'mips64r6' and/or 'mips32r6' if the kernel is running on a MIPS R6 core. Signed-off-by: Markos Chandras <[email protected]>
2014-08-02MIPS: cpu: Add new cpu option for Hardware Table Walker.Markos Chandras1-0/+1
Moreover, report hardware page table walker support as 'htw' in the ASE list of /proc/cpuinfo, if the core implements this feature. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7334/ Signed-off-by: Ralf Baechle <[email protected]>
2014-07-30MIPS: Support CPU topology files in sysfsHuacai Chen1-0/+1
This patch is prepared for Loongson's NUMA support, it offer meaningful sysfs files such as physical_package_id, core_id, core_siblings and thread_siblings in /sys/devices/system/cpu/cpu?/topology. Signed-off-by: Huacai Chen <[email protected]> Reviewed-by: Andreas Herrmann <[email protected]> Cc: John Crispin <[email protected]> Cc: Steven J. Hill <[email protected]> Cc: Aurelien Jarno <[email protected]> Cc: [email protected] Cc: Fuxin Zhang <[email protected]> Cc: Zhangjin Wu <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/7184/ Signed-off-by: Ralf Baechle <[email protected]>
2014-05-13Revert "MIPS: MT: proc: Add support for printing VPE and TC ids"Ralf Baechle1-8/+1
Reverts commit 795038a6910937fa167d47f6f6183db0eb8fb706 because d6d3c9afaab47418ab2d7f874fb8aeac1f067104 provides the same functionality in a more generic way. Both patches applied however means that the VPE and TC IDs get printed twice currently.
2014-03-31MIPS: MT: proc: Add support for printing VPE and TC idsRalf Baechle1-0/+23
And there are more CPUs or configurations that want to provide special per-CPU information in /proc/cpuinfo. So I think there needs to be a hook mechanism, such as a notifier. This is a first cut only; I need to think about what sort of looking the notifier needs to have. But I'd appreciate testing on MT hardware! Signed-off-by: Ralf Baechle <[email protected]> Cc: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6066/
2014-03-26MIPS: kernel: proc: Add EVA to the list of CPU featuresMarkos Chandras1-0/+1
Signed-off-by: Markos Chandras <[email protected]>
2014-03-26MIPS: Detect the MSA ASEPaul Burton1-0/+1
This patch adds support for probing the MSAP bit within the Config3 register in order to detect the presence of the MSA ASE. Presence of the ASE will be indicated in /proc/cpuinfo. The value of the MSA implementation register will be displayed at boot to aid debugging and verification of a correct setup, as is done for the FPU. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6430/ Signed-off-by: Ralf Baechle <[email protected]>
2014-01-24MIPS: /proc/cpuinfo: always print the supported ISAAaro Koskinen1-20/+19
Currently the supported ISA is only printed on the latest architectures. Print it also on legacy platforms. Signed-off-by: Aaro Koskinen <[email protected]> Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/6295/
2014-01-22MIPS: MT: proc: Add support for printing VPE and TC idsMarkos Chandras1-1/+8
Add support for including VPE and TC ids in /proc/cpuinfo output as appropriate when MT/SMTC is enabled. Reviewed-by: James Hogan <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/6065/
2013-07-01MIPS: Get rid of MIPS I flag and test macros.Ralf Baechle1-3/+1
MIPS I is the ancestor of all MIPS ISA and architecture variants. Anything ever build in the MIPS empire is either MIPS I or at least contains MIPS I. If it's running Linux, that is. So there is little point in having cpu_has_mips_1 because it will always evaluate as true - though usually only at runtime. Thus there is no point in having the MIPS_CPU_ISA_I ISA flag, so get rid of it. Little complication: traps.c was using a test for a pure MIPS I ISA as a test for an R3000-style cp0. To deal with that, use a check for cpu_has_3kex or cpu_has_4kex instead. cpu_has_3kex is a new macro. At the moment its default implementation is !cpu_has_4kex but this may eventually change if Linux is ever going to support the oddball MIPS processors R6000 and R8000 so users of either of these macros should not make any assumptions. Signed-off-by: Ralf Baechle <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/5551/
2013-05-22MIPS: Idle: Consolidate all declarations in <asm/idle.h>.Ralf Baechle1-0/+1
Signed-off-by: Ralf Baechle <[email protected]>
2013-05-09Merge branch 'mti-next' of ↵Ralf Baechle1-0/+4
git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
2013-05-09MIPS: microMIPS: Add configuration option for microMIPS kernel.Steven J. Hill1-0/+4
This adds the option to build the Linux kernel using only the microMIPS ISA. The resulting kernel binary is, at a minimum, 20% smaller than using the MIPS32R2 ISA. Signed-off-by: Steven J. Hill <[email protected]>
2013-05-08MIPS: move mips_{set,get}_machine_name() to a more generic placeJohn Crispin1-1/+1
Previously this functionality was only available to users of the mips_machine api. Moving the code to prom.c allows us to also add a OF wrapper. Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/5164/
2013-03-13MIPS: Fix inconsistent formatting inside /proc/cpuinfoJohn Crispin1-1/+1
There is a missing " " inside /proc/cpuinfo. The bad commit was: commit a96102be700f87283f168942cd09a2b30f86f324 Author: Steven J. Hill <[email protected]> Date: Fri Dec 7 04:31:36 2012 +0000 MIPS: Add printing of ISA version in cpuinfo. Signed-off-by: John Crispin <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/4988/ Signed-off-by: Ralf Baechle <[email protected]>
2013-02-21Merge branch 'mips-next-3.9' of ↵Ralf Baechle1-0/+2
git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
2013-02-19MIPS: Probe for and report hardware virtualization support.David Daney1-0/+1
The presence of the MIPS Virtualization Application-Specific Extension is indicated by CP0_Config3[23]. Probe for this and report it in /proc/cpuinfo. Signed-off-by: David Daney <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4904/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: Add support for the M14KEc core.Steven J. Hill1-0/+1
Signed-off-by: Steven J. Hill <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4682/ Signed-off-by: John Crispin <[email protected]>
2013-02-15MIPS: Add printing of ISA version in cpuinfo.Steven J. Hill1-0/+22
Display the MIPS ISA version release in the /proc/cpuinfo file. [[email protected]: Add support for MIPS I ... IV legacy architecture revisions. Also differenciate between MIPS32 and MIPS64 versions instead of lumping them together as just r1 and r2. Note to application programmers: this indicates the CPU's ISA level It does not imply the current execution environment does support it. For example an O32 application seeing "mips64r2" would still be restricted by by the execution environment to 32-bit - but the kernel could run mips64r2 code. The same for a 32-bit kernel running on a 64-bit processor. This field doesn't include ASEs or optional architecture modules nor other detailed flags such as the availability of an FPU.] Signed-off-by: Steven J. Hill <[email protected]> Cc: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/4714/ Signed-off-by: Ralf Baechle <[email protected]>
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle1-1/+1
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <[email protected]>
2012-10-11MIPS: proc: Cleanup printing of ASEs.Ralf Baechle1-9/+11
The number of %s was just getting ridiculous. Signed-off-by: Ralf Baechle <[email protected]>
2012-10-11MIPS: Add detection of DSP ASE Revision 2.Steven J. Hill1-0/+1
[[email protected]: This patch really only detects the ASE and passes its existence on to userland via /proc/cpuinfo. The DSP ASE Rev 2. adds new resources but no resources that would need management by the kernel.] Signed-off-by: Steven J. Hill <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/4165/ Signed-off-by: Ralf Baechle <[email protected]>
2012-05-15MIPS: Code formatting fixes.Steven J. Hill1-13/+13
Signed-off-by: Steven J. Hill <[email protected]> Cc: [email protected] Signed-off-by: Ralf Baechle <[email protected]>
2012-03-29remove references to cpu_*_map in arch/Rusty Russell1-1/+1
This has been obsolescent for a while; time for the final push. In adjacent context, replaced old cpus_* with cpumask_*. Signed-off-by: Rusty Russell <[email protected]> Acked-by: David S. Miller <[email protected]> (arch/sparc) Acked-by: Chris Metcalf <[email protected]> (arch/tile) Cc: [email protected] Cc: Russell King <[email protected]> Cc: [email protected] Cc: Richard Kuo <[email protected]> Cc: [email protected] Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: Kyle McMartin <[email protected]> Cc: Helge Deller <[email protected]> Cc: [email protected]
2011-01-18MIPS: Probe for presence of KScratch registers.David Daney1-0/+2
Probe c0_config4 for KScratch registers and report them in /proc/cpuinfo. Signed-off-by: David Daney <[email protected]> To: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/1877/ Signed-off-by: Ralf Baechle <[email protected]>
2011-01-18MIPS: Add generic support for multiple machines within a single kernelGabor Juhos1-1/+6
This patch adds a generic solution to support multiple machines based on a given SoC within a single kernel image. It is implemented already for several other architectures but MIPS has no generic support for that yet. [Ralf: This competes with DT but DT is a much more complex solution and this code has been used by OpenWRT for a long time so for now DT is a bad reason to stop the merge but longer term this should be migrated to DT.] Signed-off-by: Gabor Juhos <[email protected]> Cc: [email protected] Cc: [email protected] Cc: Luis R. Rodriguez <[email protected]> Cc: Cliff Holden <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/1814/ Signed-off-by: Ralf Baechle <[email protected]>
2009-08-03MIPS: Eleminate filenames from commentsRalf Baechle1-2/+0
They tend to get not updated when files are moved around or copied and lack any obvious use. While at it zap some only too obvious comments and as per Shinya's suggestion, add a copyright header to extable.c. Signed-off-by: Ralf Baechle <[email protected]> Acked-by: Shinya Kuribayashi <[email protected]> Acked-by: Thadeu Lima de Souza Cascardo <[email protected]>
2009-06-08MIPS: Outline udelay and fix a few issues.Ralf Baechle1-1/+1
Outlining fixes the issue were on certain CPUs such as the R10000 family the delay loop would need an extra cycle if it overlaps a cacheline boundary. The rewrite also fixes build errors with GCC 4.4 which was changed in way incompatible with the kernel's inline assembly. Relying on pure C for computation of the delay value removes the need for explicit. The price we pay is a slight slowdown of the computation - to be fixed on another day. Signed-off-by: Ralf Baechle <[email protected]>
2008-10-15MIPS: show_cpuinfo prints the type of the calling CPUJohannes Dickgreber1-1/+1
It should print the type of the Nth processor. Signed-off-by: Johannes Dickgreber <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2008-10-11MIPS: Probe watch registers and report configuration.David Daney1-2/+11
Probe for watch register characteristics, and report them in /proc/cpuinfo. Signed-off-by: David Daney <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2008-01-29[MIPS]: constify function pointer tablesJan Engelhardt1-1/+1
Signed-off-by: Jan Engelhardt <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2008-01-29[MIPS] MT: Scheduler support for SMTRalf Baechle1-0/+1
Signed-off-by: Ralf Baechle <[email protected]>
2007-11-15[MIPS] Fix shadow register support.Ralf Baechle1-0/+2
Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <[email protected]>
2007-10-11[MIPS] Make facility to convert CPU types to strings generally available.Ralf Baechle1-74/+1
So far /proc/cpuinfo has been the only user but human readable processor name are more useful than that for proc. Signed-off-by: Ralf Baechle <[email protected]>
2007-10-11[MIPS] Add support for BCM47XX CPUs.Aurelien Jarno1-0/+2
Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch <[email protected]> Cc: Felix Fietkau <[email protected]> Cc: Florian Schirmer <[email protected]> Signed-off-by: Aurelien Jarno <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2007-07-10[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang1-0/+1
Signed-off-by: Fuxin Zhang <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2007-07-10[MIPS] Remove unused watchpoint support and arch/mips/lib-{32,64}Atsushi Nemoto1-1/+0
Signed-off-by: Atsushi Nemoto <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2007-02-06[MIPS] Whitespace cleanups.Ralf Baechle1-4/+4
Signed-off-by: Ralf Baechle <[email protected]>
2006-10-09[MIPS] Make sure cpu_has_fpu is used only in atomic contextAtsushi Nemoto1-1/+1
Make sure cpu_has_fpu (which uses smp_processor_id()) is used only in atomic context. Signed-off-by: Atsushi Nemoto <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2006-10-08[MIPS] Show actual CPU information in /proc/cpuinfoKarl-Johan Karlsson1-5/+5
Currently, /proc/cpuinfo contains several copies of the information for whatever processor we happen to be scheduled on. This patch makes it contain the proper information for each CPU, which is particularly useful on mixed R12k/R10k IP27 machines. Signed-off-by: Karl-Johan Karlsson <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2006-06-30Remove obsolete #include <linux/config.h>Jörn Engel1-1/+0
Signed-off-by: Jörn Engel <[email protected]> Signed-off-by: Adrian Bunk <[email protected]>
2006-06-01[MIPS] Treat R14000 like R10000.Kumba1-0/+1
Signed-off-by: Joshua Kinard <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2006-06-01[MIPS] Fix detection and handling of the 74K processor.Chris Dearman1-0/+1
Nothing exciting; Linux just didn't know it yet so this is most adding a value to a case statement. Signed-off-by: Chris Dearman <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2006-03-21[MIPS] Separate CPU entries in /proc/cpuinfo with a blank line.Martin Michlmayr1-0/+1
Put in a blank line between CPU entries in /proc/cpuinfo, just like most other architectures (i386, ia64, x86_64) do. Signed-off-by: Martin Michlmayr <[email protected]> Signed-off-by: Ralf Baechle <[email protected]> ---
2005-10-29Add support for SB1A CPU.Andrew Isaacson1-0/+1
Signed-Off-By: Andy Isaacson <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
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