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This modifies the IP32 (SGI O2) platform and reset code to utilize the new
rtc-ds1685 driver. The old mc146818rtc.h header is removed and ip32_defconfig
is updated as well.
Signed-off-by: Joshua Kinard <[email protected]>
Acked-by: Ralf Baechle <[email protected]>
Cc: Alessandro Zummo <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
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Switch to using the newly created asm-generic/seccomp.h for the seccomp
strict mode syscall definitions. COMPAT definitions retain their
overrides and the remaining definitions were identical.
Signed-off-by: Kees Cook <[email protected]>
Cc: Ralf Baechle <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/rw/misc
Pull exec domain removal from Richard Weinberger:
"This series removes execution domain support from Linux.
The idea behind exec domains was to support different ABIs. The
feature was never complete nor stable. Let's rip it out and make the
kernel signal handling code less complicated"
* 'exec_domain_rip_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/misc: (27 commits)
arm64: Removed unused variable
sparc: Fix execution domain removal
Remove rest of exec domains.
arch: Remove exec_domain from remaining archs
arc: Remove signal translation and exec_domain
xtensa: Remove signal translation and exec_domain
xtensa: Autogenerate offsets in struct thread_info
x86: Remove signal translation and exec_domain
unicore32: Remove signal translation and exec_domain
um: Remove signal translation and exec_domain
tile: Remove signal translation and exec_domain
sparc: Remove signal translation and exec_domain
sh: Remove signal translation and exec_domain
s390: Remove signal translation and exec_domain
mn10300: Remove signal translation and exec_domain
microblaze: Remove signal translation and exec_domain
m68k: Remove signal translation and exec_domain
m32r: Remove signal translation and exec_domain
m32r: Autogenerate offsets in struct thread_info
frv: Remove signal translation and exec_domain
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Pull crypto update from Herbert Xu:
"Here is the crypto update for 4.1:
New interfaces:
- user-space interface for AEAD
- user-space interface for RNG (i.e., pseudo RNG)
New hashes:
- ARMv8 SHA1/256
- ARMv8 AES
- ARMv8 GHASH
- ARM assembler and NEON SHA256
- MIPS OCTEON SHA1/256/512
- MIPS img-hash SHA1/256 and MD5
- Power 8 VMX AES/CBC/CTR/GHASH
- PPC assembler AES, SHA1/256 and MD5
- Broadcom IPROC RNG driver
Cleanups/fixes:
- prevent internal helper algos from being exposed to user-space
- merge common code from assembly/C SHA implementations
- misc fixes"
* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (169 commits)
crypto: arm - workaround for building with old binutils
crypto: arm/sha256 - avoid sha256 code on ARMv7-M
crypto: x86/sha512_ssse3 - move SHA-384/512 SSSE3 implementation to base layer
crypto: x86/sha256_ssse3 - move SHA-224/256 SSSE3 implementation to base layer
crypto: x86/sha1_ssse3 - move SHA-1 SSSE3 implementation to base layer
crypto: arm64/sha2-ce - move SHA-224/256 ARMv8 implementation to base layer
crypto: arm64/sha1-ce - move SHA-1 ARMv8 implementation to base layer
crypto: arm/sha2-ce - move SHA-224/256 ARMv8 implementation to base layer
crypto: arm/sha256 - move SHA-224/256 ASM/NEON implementation to base layer
crypto: arm/sha1-ce - move SHA-1 ARMv8 implementation to base layer
crypto: arm/sha1_neon - move SHA-1 NEON implementation to base layer
crypto: arm/sha1 - move SHA-1 ARM asm implementation to base layer
crypto: sha512-generic - move to generic glue implementation
crypto: sha256-generic - move to generic glue implementation
crypto: sha1-generic - move to generic glue implementation
crypto: sha512 - implement base layer for SHA-512
crypto: sha256 - implement base layer for SHA-256
crypto: sha1 - implement base layer for SHA-1
crypto: api - remove instance when test failed
crypto: api - Move alg ref count init to crypto_check_alg
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The arch_randomize_brk() function is used on several architectures,
even those that don't support ET_DYN ASLR. To avoid bulky extern/#define
tricks, consolidate the support under CONFIG_ARCH_HAS_ELF_RANDOMIZE for
the architectures that support it, while still handling CONFIG_COMPAT_BRK.
Signed-off-by: Kees Cook <[email protected]>
Cc: Hector Marco-Gisbert <[email protected]>
Cc: Russell King <[email protected]>
Reviewed-by: Ingo Molnar <[email protected]>
Cc: Catalin Marinas <[email protected]>
Cc: Will Deacon <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: Benjamin Herrenschmidt <[email protected]>
Cc: Paul Mackerras <[email protected]>
Cc: Michael Ellerman <[email protected]>
Cc: Martin Schwidefsky <[email protected]>
Cc: Heiko Carstens <[email protected]>
Cc: Alexander Viro <[email protected]>
Cc: Oleg Nesterov <[email protected]>
Cc: Andy Lutomirski <[email protected]>
Cc: "David A. Long" <[email protected]>
Cc: Andrey Ryabinin <[email protected]>
Cc: Arun Chandran <[email protected]>
Cc: Yann Droneaud <[email protected]>
Cc: Min-Hua Chen <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: Alex Smith <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: Vineeth Vijayan <[email protected]>
Cc: Jeff Bailey <[email protected]>
Cc: Michael Holzheu <[email protected]>
Cc: Ben Hutchings <[email protected]>
Cc: Behan Webster <[email protected]>
Cc: Ismael Ripoll <[email protected]>
Cc: Jan-Simon Mller <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull core locking changes from Ingo Molnar:
"Main changes:
- jump label asm preparatory work for PowerPC (Anton Blanchard)
- rwsem optimizations and cleanups (Davidlohr Bueso)
- mutex optimizations and cleanups (Jason Low)
- futex fix (Oleg Nesterov)
- remove broken atomicity checks from {READ,WRITE}_ONCE() (Peter
Zijlstra)"
* 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
powerpc, jump_label: Include linux/jump_label.h to get HAVE_JUMP_LABEL define
jump_label: Allow jump labels to be used in assembly
jump_label: Allow asm/jump_label.h to be included in assembly
locking/mutex: Further simplify mutex_spin_on_owner()
locking: Remove atomicy checks from {READ,WRITE}_ONCE
locking/rtmutex: Rename argument in the rt_mutex_adjust_prio_chain() documentation as well
locking/rwsem: Fix lock optimistic spinning when owner is not running
locking: Remove ACCESS_ONCE() usage
locking/rwsem: Check for active lock before bailing on spinning
locking/rwsem: Avoid deceiving lock spinners
locking/rwsem: Set lock ownership ASAP
locking/rwsem: Document barrier need when waking tasks
locking/futex: Check PF_KTHREAD rather than !p->mm to filter out kthreads
locking/mutex: Refactor mutex_spin_on_owner()
locking/mutex: In mutex_spin_on_owner(), return true when owner changes
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Signed-off-by: Richard Weinberger <[email protected]>
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Set good default FPU flags (FR0) for O32 binaries similar to what the
kernel does for the N64/N32 ones. This also fixes a regression
introduced in commit 46490b572544 ("MIPS: kernel: elf: Improve the
overall ABI and FPU mode checks") when MIPS_O32_FP64_SUPPORT is
disabled. In that case, the mips_set_personality_fp() did not set the
FPU mode at all because it assumed that the FPU mode was already set
properly. That led to O32 userland problems.
Signed-off-by: Markos Chandras <[email protected]>
Reported-by: Mans Rullgard <[email protected]>
Fixes: 46490b572544 ("MIPS: kernel: elf: Improve the overall ABI and FPU mode checks")
Tested-by: Mans Rullgard <[email protected]>
Tested-by: Aaro Koskinen <[email protected]>
Cc: Matthew Fortune <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/9344/
Signed-off-by: Ralf Baechle <[email protected]>
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The lose_fpu() function only disables the FPU in CP0_Status.CU1 if the
FPU is in use and MSA isn't enabled.
This isn't necessarily a problem because KSTK_STATUS(current), the
version of CP0_Status stored on the kernel stack on entry from user
mode, does always get updated and gets restored when returning to user
mode, but I don't think it was intended, and it is inconsistent with the
case of only the FPU being in use. Sometimes leaving the FPU enabled may
also mask kernel bugs where FPU operations are executed when the FPU
might not be enabled.
So lets disable the FPU in the MSA case too.
Fixes: 33c771ba5c5d ("MIPS: save/disable MSA in lose_fpu")
Signed-off-by: James Hogan <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9323/
Signed-off-by: Ralf Baechle <[email protected]>
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This is no longer needed with the fixed, new and improved definition
of cpu_has_mips_r2_exec_hazard in <asm/cpu-features.h>.
For a discussion, see http://patchwork.linux-mips.org/patch/9539/.
Signed-off-by: Ralf Baechle <[email protected]>
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Returns a non-zero value if the current processor implementation requires
an IHB instruction to deal with an instruction hazard as per MIPS R2
architecture specification, zero otherwise.
For a discussion, see http://patchwork.linux-mips.org/patch/9539/.
Signed-off-by: Ralf Baechle <[email protected]>
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Commit 5753762cbd1c("MIPS: asm: spinlock: Replace "sub" instruction
with "addiu") replaced the "sub" instruction with addiu but it did
not update the immediate value in the R10000_LLSC_WAR case.
Signed-off-by: Markos Chandras <[email protected]>
Fixes: 5753762cbd1c("MIPS: asm: spinlock: Replace "sub" instruction with "addiu"")
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9385/
Signed-off-by: Ralf Baechle <[email protected]>
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Commit 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll
functions") added support for MIPS R6 cache flushes but it used the
wrong base address register to perform the flushes so the same lines
were flushed over and over. Moreover, replace the "addiu" instructions
with LONG_ADDIU so the correct base address is calculated for 64-bit
cores.
Signed-off-by: Markos Chandras <[email protected]>
Fixes: 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions")
Cc: [email protected]
Reviewed-by: Maciej W. Rozycki <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9384/
Signed-off-by: Ralf Baechle <[email protected]>
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Introduce new macros for kernel load/store variants which will be
used to perform regular kernel space load/store operations in EVA
mode.
Signed-off-by: Markos Chandras <[email protected]>
Cc: <[email protected]> # v3.15+
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9500/
Signed-off-by: Ralf Baechle <[email protected]>
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udelay() in PCI/PCIe read/write callbacks cause 30ms IRQ latency on Octeon
platforms because these operations are called from PCI_OP_READ() and
PCI_OP_WRITE() under raw_spin_lock_irqsave().
Signed-off-by: Alexander Sverdlin <[email protected]>
Cc: [email protected]
Cc: David Daney <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Jiri Kosina <[email protected]>
Cc: Randy Dunlap <[email protected]>
Cc: Masanari Iida <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Mathias <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9576/
Signed-off-by: Ralf Baechle <[email protected]>
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Wrap asm/jump_label.h for all archs with #ifndef __ASSEMBLY__.
Since these are kernel only headers, we don't need #ifdef
__KERNEL__ so can simplify things a bit.
If an architecture wants to use jump labels in assembly, it
will still need to define a macro to create the __jump_table
entries (see ARCH_STATIC_BRANCH in the powerpc asm/jump_label.h
for an example).
Signed-off-by: Anton Blanchard <[email protected]>
Acked-by: Peter Zijlstra (Intel) <[email protected]>
Cc: Andrew Morton <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Paul E. McKenney <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
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Broadcom BCM63xx DSL SoCs utilize BMIPS CPUs, and as such are required
to perform a read-ahead cache flush after a DMA transfer. Utilize
asm/bmips.h to provide a plat_post_dma_flush_hook, and
mach-generic/dma-coherence.h for everything else.
Signed-off-by: Florian Fainelli <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9726/
Signed-off-by: Ralf Baechle <[email protected]>
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Instead of having platforms to copy the entirety of
mach-generic/dma-coherence.h, check whether these platforms have already
defined a plat_post_dma_flush hook, and if not, provide an inline stub.
Signed-off-by: Florian Fainelli <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9725/
Signed-off-by: Ralf Baechle <[email protected]>
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arch/mips/include/asm/mach-bmips/dma-coherence.h contains the
plat_post_dma_flush implementation which is not specific to mach-bmips,
but required for all BMIPS-based systems.
Move plat_post_dma_flush to arch/mips/include/asm/bmips.h, rename it to
bmips_post_dma_flush such that other platforms like bcm63xx can utilize
it.
Signed-off-by: Florian Fainelli <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9724/
Signed-off-by: Ralf Baechle <[email protected]>
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Define the central place the default FCSR value is set from, initialised
in `cpu_probe'. Determine the FCSR mask applied to values written to
the register with CTC1 in the full emulation mode and via ptrace(2),
according to the ISA level of processor hardware or the writability of
bits 31:18 if actual FPU hardware is used.
Software may rely on FCSR bits whose functions our emulator does not
implement, so it should not allow them to be set or software may get
confused. For ptrace(2) it's just sanity.
[[email protected]: Fixed double inclusion of <asm/current.h>.]
Signed-off-by: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9711/
Signed-off-by: Ralf Baechle <[email protected]>
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Define IEEE 754-2008 feature control bits: FIR.HAS2008, FCSR.ABS2008 and
FCSR.NAN2008, and update the `_ieee754_csr' structure accordingly.
For completeness define FIR.UFRP too.
Signed-off-by: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9709/
Signed-off-by: Ralf Baechle <[email protected]>
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Implement the FCCR, FEXR and FENR "shadow" FPU registers for the
architecture levels that include them, for the CFC1 and CTC1
instructions in the full emulation mode.
For completeness add macros for the CP1 UFR and UNFR registers too, no
actual implementation though.
Signed-off-by: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9708/
Signed-off-by: Ralf Baechle <[email protected]>
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Rework `process_fpemu_return' and move IEEE 754 exception interpretation
there, from `do_fpe'. Record the cause bits set in FCSR before they are
cleared and pass them through to `process_fpemu_return' so as to set
`si_code' correctly too for SIGFPE signals sent from emulation rather
than those issued by hardware with the FPE processor exception only.
For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised
and only sets it to anything if an FPU instruction has been emulated,
which in turn is the only case SIGFPE can be issued for here.
Signed-off-by: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9705/
Signed-off-by: Ralf Baechle <[email protected]>
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Correct ISA requirements for floating-point instructions:
* the CU3 exception signifies a real COP3 instruction in MIPS I & II,
* the BC1FL and BC1TL instructions are not supported in MIPS I,
* the SQRT.fmt instructions are indeed supported in MIPS II,
* the LDC1 and SDC1 instructions are indeed supported in MIPS32r1,
* the CEIL.W.fmt, FLOOR.W.fmt, ROUND.W.fmt and TRUNC.W.fmt instructions
are indeed supported in MIPS32,
* the CVT.L.fmt and CVT.fmt.L instructions are indeed supported in
MIPS32r2 and MIPS32r6,
* the CEIL.L.fmt, FLOOR.L.fmt, ROUND.L.fmt and TRUNC.L.fmt instructions
are indeed supported in MIPS32r2 and MIPS32r6,
* the RSQRT.fmt and RECIP.fmt instructions are indeed supported in
MIPS64r1,
Also simplify conditionals for MIPS III and MIPS IV FPU instructions and
the handling of the MOVCI minor opcode.
Signed-off-by: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9700/
Signed-off-by: Ralf Baechle <[email protected]>
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Implement the correct ordering of individual floating-point registers
within double-precision register pairs for the MIPS I FP context, as
required by our FP emulation code and expected by userland talking via
ptrace(2). Use L.D and S.D assembly macros that do the right thing like
LDC1 and SDC1 from MIPS II up, avoiding the need to mess up with
endianness conditionals.
This in particular fixes the handling of denormals and NaN generation in
Unimplemented Operation emulation traps.
Signed-off-by: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9699/
Signed-off-by: Ralf Baechle <[email protected]>
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The `cpu_has_fpu' feature flag must not be hardcoded to 1 or the `nofpu'
kernel option will be ignored. Remove any such overrides and add a
cautionary note. Hardcoding to 0 is fine for FPU-less platforms.
Signed-off-by: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9694/
Signed-off-by: Ralf Baechle <[email protected]>
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GCC is smart enough to substitute the final result for FLS calculations
as implemented in the fallback C code we have in `__fls' and `fls'
applied to constant values. The presence of inline asm defeats the
compiler though, forcing it to emit extraneous CLZ/DCLZ calculation for
processors that support these instructions.
Use `__builtin_constant_p' then to avoid inline asm altogether for
constants.
Signed-off-by: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9681/
Signed-off-by: Ralf Baechle <[email protected]>
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Use `static inline' rather than `static __maybe_unused' for
`mipsr2_decoder' in the empty case, making inlining explicit where it
will happen anyway.
Signed-off-by: Maciej W. Rozycki <[email protected]>
Cc: Leonid Yegoshin <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9678/
Signed-off-by: Ralf Baechle <[email protected]>
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Reindent CP0 Cause macros for a single space after #define, leaving
extra indentation for individual Interrupt Pending bits as with CP0
Status register's Interrupt Mask bits.
[[email protected]: Fix conflict.]
[[email protected]: Fix indentation of the CAUSEB_FDCI and CAUSEF_FDCI
definitions.]
Signed-off-by: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9669/
Signed-off-by: Ralf Baechle <[email protected]>
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TX39 CP0 Configuration Register 3 macro definitions have been randomly
thrown in the middle of a block of CP0 Status register value macros.
Move them to the end of the whole CP0 register value macro block,
complementing the location of the TX39 Cache register name macro at the
end of the CP0 register name macro block.
[[email protected]: Fix conflict.]
Signed-off-by: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9668/
Signed-off-by: Ralf Baechle <[email protected]>
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Originally CP1 macros were placed between CP0 register name macros and
CP0 register value macros. As changes were applied to the header the
position of CP1 macros gradually has become more and more arbitrary and
two separate blocks were created. This may only cause confusion.
Move them out of the way then and place together after all the CP0
macros. No semantic change.
[[email protected]: Fix conflict.]
Signed-off-by: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9667/
Signed-off-by: Ralf Baechle <[email protected]>
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Remove a duplicate FPU Status Register reference that has been there
since forever and a mistakenly copied and pasted R4xx0 manual reference.
[[email protected]: Fix conflict.]
Signed-off-by: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9666/
Signed-off-by: Ralf Baechle <[email protected]>
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This cleanup is prepare to move the driver to drivers/gpio. Custom
definitions of gpio_get_value()/gpio_set_value() are dropped.
Acked-by: Ralf Baechle <[email protected]>
Signed-off-by: Huacai Chen <[email protected]>
Reviewed-by: Alexandre Courbot <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
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Signed-off-by: Rafał Miłecki <[email protected]>
Cc: [email protected]
Cc: Hauke Mehrtens <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9656/
Signed-off-by: Ralf Baechle <[email protected]>
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MIPS architecture code does not provide copy_user_page,
so it should not provide a prototype for it either.
Signed-off-by: Guenter Roeck <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9266/
Signed-off-by: Ralf Baechle <[email protected]>
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This add CPU Hwmon (temperature sensor) platform driver for Loongson-3.
Signed-off-by: Huacai Chen <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9617/
Signed-off-by: Ralf Baechle <[email protected]>
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On SGI Origin 2k/Onyx2 and SGI Octane systems, there can exist multiple PCI
buses attached to the Xtalk bus. The current code will stop counting PCI buses
after it finds the first one. If one installs the optional PCI cardcage
("shoebox") into these systems, because of the order of the Xtalk widgets, the
current PCI code will find the cardcage first, and fail to detect the BaseIO
PCI devices, which are on a higher Xtalk widget ID.
This patch adds the hooks needed for resolving this issue in the IP27 PCI code
(in a later patch).
Verified on both an SGI Onyx2 and an SGI Octane.
Signed-off-by: Joshua Kinard <[email protected]>
Cc: Linux MIPS List <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9074/
Signed-off-by: Ralf Baechle <[email protected]>
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Use the normal return values for bool functions
Signed-off-by: Joe Perches <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9640/
Signed-off-by: Ralf Baechle <[email protected]>
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64 bit access is unaffected but for 32 bit access, swap high and
low words. Similarly for 16 bit access, reverse the order of the
four possible words, and for 8 bit access reverse the order of byte
accesses.
Signed-off-by: Paul Martin <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9630/
Signed-off-by: Ralf Baechle <[email protected]>
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Although the proper way to do this for bitfields would be to use
the macro that Ralf has provided, this is a little easier to
understand as a diff.
Signed-off-by: Paul Martin <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9628/
Signed-off-by: Ralf Baechle <[email protected]>
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This allows the kernel to correctly detect an R16000 MIPS CPU on systems that
have those. Otherwise, such systems will detect the CPU as an R14000, due to
similarities in the CPU PRId value.
Signed-off-by: Joshua Kinard <[email protected]>
Cc: Linux MIPS List <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9092/
Signed-off-by: Ralf Baechle <[email protected]>
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Signed-off-by: Ralf Baechle <[email protected]>
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BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer
may cause parts of the DMA buffer to be prefetched into the RAC. To
avoid possible coherency problems, flush the RAC upon DMA completion.
Derived from Kevin Cernekee's https://patchwork.linux-mips.org/patch/9602/.
Signed-off-by: Ralf Baechle <[email protected]>
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Signed-off-by: Ralf Baechle <[email protected]>
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These got merged with the ath25 support after 4e7f72660c39 (MIPS: Remove
unnecessary platform dma helper functions) had already removed them for
all other platforms.
Signed-off-by: Ralf Baechle <[email protected]>
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There are two reasons for having this header in the common place:
1) Simplifying drivers that read NVRAM entries. We will be able to
safely call bcm47xx_nvram_* functions without #ifdef-s.
2) Getting NVRAM driver out of MIPS arch code. This is needed to support
BCM5301X arch which also requires this NVRAM driver. Patch for that
will follow once we get is reviewed.
Signed-off-by: Rafał Miłecki <[email protected]>
Acked-by: Hauke Mehrtens <[email protected]>
Cc: [email protected]
Cc: Arnd Bergmann <[email protected]>
Cc: Paul Walmsley <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/8619/
Signed-off-by: Ralf Baechle <[email protected]>
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With CONFIG_MIGRATION, the PFN of the migrating pages is stored in
__swp_offset(), so we must have enough bits to store the largest
possible PFN. OCTEON NUMA systems have 41 bits of physical address
space, so with 4K pages (12-bits), we need at least 29 bits to store
the PFN.
The current width of 24-bits is too narrow, so expand it all the way
out to 40-bits. This leaves the low order 16 bits as zero which does
not interfere with any of the PTE bits.
Signed-off-by: David Daney <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9315/
Signed-off-by: Ralf Baechle <[email protected]>
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Delay slot emulation in the FPU emulator is the only kernel user of an
executable stack, it is also very slow. Add a counter so we can see
how many of these emulations are done.
Signed-off-by: David Daney <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/8634/
Signed-off-by: Ralf Baechle <[email protected]>
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