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Support probing the i8259 programmable interrupt controller, as found on
the Malta board, and using its interrupts via device tree.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Rob Herring <[email protected]>
Cc: Pawel Moll <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Ian Campbell <[email protected]>
Cc: Kumar Gala <[email protected]>
Cc: Qais Yousef <[email protected]>
Cc: Andrew Bresticker <[email protected]>
Cc: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/10114/
Signed-off-by: Ralf Baechle <[email protected]>
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A later patch in this series will include mips-cm.h but does not require
errno.h. This leads to a build failure with ENODEV undeclared. Include
errno.h from mips-cm.h to pull in the appropriate definition and avoid
the build failure.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Rob Herring <[email protected]>
Cc: Pawel Moll <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Ian Campbell <[email protected]>
Cc: Kumar Gala <[email protected]>
Cc: James Hogan <[email protected]>
Cc: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/10113/
Signed-off-by: Ralf Baechle <[email protected]>
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Add definitions for the GICEX field in the GCR_GIC_STATUS register to
mips-cm.h for use in a later patch.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Rob Herring <[email protected]>
Cc: Pawel Moll <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Ian Campbell <[email protected]>
Cc: Kumar Gala <[email protected]>
Cc: James Hogan <[email protected]>
Cc: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/10112/
Signed-off-by: Ralf Baechle <[email protected]>
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This is the first patch of two to clean up/update the Xtalk detection
code used by IP27 with some of the code used in the IP30 port.
This specific patch adds Xtalk widget manufacturer and widget device
numbers to arch/mips/include/asm/xtalk/widget.h
Signed-off-by: Joshua Kinard <[email protected]>
Cc: Linux MIPS List <[email protected]>
Patchwork: http://patchwork.linux-mips.org/patch/10174/
Signed-off-by: Ralf Baechle <[email protected]>
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Commits ac1d8590d3ae (MIPS: asm: uaccess: Use EVA instructions
wrappers), 05c6516005c4 (MIPS: asm: uaccess: Add EVA support to
copy_{in, to,from}_user) & e3a9b07a9caf (MIPS: asm: uaccess: Add EVA
support for str*_user operations) added checks to various user memory
access functions & macros in order to determine whether to perform
standard memory accesses or their EVA userspace equivalents. In kernels
built without support for EVA these checks are entirely redundant. Avoid
emitting them & allow the compiler to optimise out the EVA userspace
code in such kernels by checking config_enabled(CONFIG_EVA).
This reduces the size of a malta_defconfig kernel built using GCC 4.9.2
by approximately 33KB (from 5995072 to 5962304 bytes).
Signed-off-by: Paul Burton <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/10165/
Signed-off-by: Ralf Baechle <[email protected]>
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In preparation to allow users to enable DeviceTree without arch or
machine selecting it, we need to fix build errors on MIPS. When
CONFIG_OF is enabled, device_tree_init cannot be resolved. This is
trivially fixed by using CONFIG_USE_OF instead of CONFIG_OF for prom.h.
Signed-off-by: Rob Herring <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: [email protected]
Signed-off-by: Ralf Baechle <[email protected]>
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The R12000 added a new feature to enhance branch prediction called
"global history". Per the Vr10000 Series User Manual (U10278EJ4V0UM),
Coprocessor 0, Diagnostic Register (22):
"""
If bit 26 is set, branch prediction uses all eight bits of the global
history register. If bit 26 is not set, then bits 25:23 specify a count
of the number of bits of global history to be used. Thus if bits 26:23
are all zero, global history is disabled.
The global history contains a record of the taken/not-taken status of
recently executed branches, and when used is XOR'ed with the PC of a
branch being predicted to produce a hashed value for indexing the BPT.
Some programs with small "working set of conditional branches" benefit
significantly from the use of such hashing, some see slight performance
degradation.
"""
This patch enables global history on R12000 CPUs and up by setting bit
26 in the branch prediction diagnostic register (CP0 $22) to '1'. Bits
25:23 are left alone so that all eight bits of the global history
register are available for branch prediction.
Signed-off-by: Joshua Kinard <[email protected]>
Signed-off-by: Ralf Baechle <[email protected]>
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Inspired by Maciej's recent patch to update DEC cpu-feature-overrides.h,
I updated IP27's as well to disable features known to not apply to the
IP27 platform or the R10K-series of CPUs.
Before:
text data bss dec hex filename
8616648 463200 472240 9552088 91c0d8 vmlinux
After:
text data bss dec hex filename
8592256 471392 472240 9535888 918190 vmlinux
I believe the increase in the size of the data section is for the same
reasons as in the DEC patch.
Signed-off-by: Joshua Kinard <[email protected]>
Cc: [email protected]
Signed-off-by: Ralf Baechle <[email protected]>
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Commit 854700115ecf ([MIPS] kgdb: add arch support for the kernel's kgdb core)
added the 'kgdb_early_setup' flag to avoid calling trap_init() and init_IRQ()
the second time, however the code that called these functions earlier, from
kgdb_arch_init(), had been already removed by that time, so the flag never
served any useful purpose. Remove the related code along with ugly #ifdef'ery
at last.
[[email protected]: Folded in Guenter Roeck's fix.]
Signed-off-by: Sergei Shtylyov <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10501/
Signed-off-by: Guenter Roeck <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10533/
Signed-off-by: Ralf Baechle <[email protected]>
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Currently, code of Loongson-2/3 is under loongson directory and code of
Loongson-1 is under loongson1 directory. Besides, there are Kconfig
options such as MACH_LOONGSON and MACH_LOONGSON1. This naming style is
very ugly and confusing. Since Loongson-2/3 are both 64-bit general-
purpose CPU while Loongson-1 is 32-bit SoC, we rename both file names
and Kconfig symbols from loongson/loongson1 to loongson64/loongson32.
[[email protected]: Resolve a number of simple conflicts.]
Signed-off-by: Huacai Chen <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Cc: Kelvin Cheung <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9790/
Signed-off-by: Ralf Baechle <[email protected]>
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KVM guest kernels for trap & emulate run in user mode, with a modified
set of kernel memory segments. However the fixmap address is still in
the normal KSeg3 region at 0xfffe0000 regardless, causing problems when
cache alias handling makes use of them when handling copy on write.
Therefore define FIXADDR_TOP as 0x7ffe0000 in the guest kernel mapped
region when CONFIG_KVM_GUEST is defined.
Signed-off-by: James Hogan <[email protected]>
Cc: [email protected]
Cc: <[email protected]> # v3.10+
Patchwork: https://patchwork.linux-mips.org/patch/9887/
Signed-off-by: Ralf Baechle <[email protected]>
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Signed-off-by: Dan Haab <[email protected]>
Acked-by: Rafał Miłecki <[email protected]>
Cc: [email protected]
Cc: Hauke Mehrtens <[email protected]>
Cc: Dan Haab <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9831/
Signed-off-by: Ralf Baechle <[email protected]>
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The DDR controller need to be used by the IRQ controller to flush
the write buffer of some devices before running the IRQ handler.
It is also used by the PCI controller to setup the PCI memory windows.
The current interface used to access the DDR controller doesn't
provides any useful abstraction and simply rely on a shared global
pointer.
Replace this by a simple API to setup the PCI memory windows and use
the write buffer flush independently of the SoC type. That remove the
need for the shared global pointer, simplify the IRQ handler code.
[[email protected]: Folded in Alban Bedel's follup fix.]
Signed-off-by: Alban Bedel <[email protected]>
Cc: [email protected]
Cc: Andrew Bresticker <[email protected]>
Cc: Qais Yousef <[email protected]>
Cc: Wolfram Sang <[email protected]>
Cc: Sergey Ryazanov <[email protected]>
Cc: Gabor Juhos <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9773/
Patchwork: http://patchwork.linux-mips.org/patch/10543/
Signed-off-by: Ralf Baechle <[email protected]>
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This register is named PLL_FB and is not a divider but a multiplier.
To make things less confusing rename the ARxxxx_PLL_DIV_SHIFT and
ARxxxx_PLL_DIV_MASK macros to ARxxxx_PLL_FB_SHIFT and
ARxxxx_PLL_FB_MASK.
Signed-off-by: Alban Bedel <[email protected]>
Cc: [email protected]
Cc: Andrew Bresticker <[email protected]>
Cc: Qais Yousef <[email protected]>
Cc: Wolfram Sang <[email protected]>
Cc: Sergey Ryazanov <[email protected]>
Cc: Gabor Juhos <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9772/
Signed-off-by: Ralf Baechle <[email protected]>
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We removed __cpuinit support (leaving no-op stubs) quite some time ago.
However a few more crept in as of commit 6ee1d93455384cef8a0426effe85da2
("MIPS: BCM47XX: Detect more then 128 MiB of RAM (HIGHMEM)")
Since we want to clobber the stubs soon, get this removed now.
Signed-off-by: Paul Gortmaker <[email protected]>
Cc: Rafał Miłecki <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9892/
Signed-off-by: Ralf Baechle <[email protected]>
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Since BCM63xx runs on BMIPS3300 which requires the use of a FIXADDR_TOP
to avoid collisions with the SBR, utilize asm/bmips-spaces.h which
defines FIXADDR_TOP for us now.
Signed-off-by: Florian Fainelli <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9969/
Signed-off-by: Ralf Baechle <[email protected]>
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The FIXADDR_TOP value used by mach-bmips is in fact required whenever we
run on BMIPS3300 BMIPS CPUs, and is not machine, but CPU-specific, move
this constant to asm/bmips-spaces.h and use it in mach-bmips/spaces.h.
Signed-off-by: Florian Fainelli <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9968/
Signed-off-by: Ralf Baechle <[email protected]>
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Support the Ingenic JZ4780 SoC using the existing code under
arch/mips/jz4740 now that it has been generalised sufficiently.
Signed-off-by: Paul Burton <[email protected]>
Cc: Ian Campbell <[email protected]>
Cc: Kumar Gala <[email protected]>
Cc: Lars-Peter Clausen <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Pawel Moll <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Joshua Kinard <[email protected]>
Cc: Leonid Yegoshin <[email protected]>
Cc: Deng-Cheng Zhu <[email protected]>
Cc: [email protected]
Cc: Markos Chandras <[email protected]>
Cc: Andreas Herrmann <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10164/
Signed-off-by: Ralf Baechle <[email protected]>
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Remove the serial support from arch/mips/jz4740 & make use of the new
Ingenic SoC UART driver. This is done for both regular & early console
output.
Signed-off-by: Paul Burton <[email protected]>
Cc: Ian Campbell <[email protected]>
Cc: Kumar Gala <[email protected]>
Cc: Lars-Peter Clausen <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Pawel Moll <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Linus Walleij <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: [email protected]
Cc: Brian Norris <[email protected]>
Cc: Apelete Seketeli <[email protected]>
Cc: Alexandre Courbot <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10160/
Signed-off-by: Ralf Baechle <[email protected]>
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The only thing remaining in arch/mips/jz4740/clock.h is declarations of
the jz4740_clock_{suspend,resume} functions. Move these to
arch/mips/include/asm/mach-jz4740/clock.h for consistency with similar
functions, and remove the redundant arch/mips/jz4740/clock.h header.
Signed-off-by: Paul Burton <[email protected]>
Cc: Lars-Peter Clausen <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10156/
Signed-off-by: Ralf Baechle <[email protected]>
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The jz4740-cgu driver already has access to the CGU, so it makes sense
to move the few remaining accesses to the CGU from arch/mips/jz4740
there too. Move the jz4740_clock_{suspend,resume} functions there for
such consistency. The arch/mips/jz4740/clock.c file now contains nothing
more of use & so is removed.
Signed-off-by: Paul Burton <[email protected]>
Cc: Lars-Peter Clausen <[email protected]>
Cc: Mike Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Deng-Cheng Zhu <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10158/
Signed-off-by: Ralf Baechle <[email protected]>
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Call jz4740_clock_init before any uses of jz4740_clock_bdata occur. This
is in preparation for replacing uses of that struct with calls to
clk_get_rate, which will allow the clocks to be migrated towards common
clock framework & devicetree.
Signed-off-by: Paul Burton <[email protected]>
Cc: Lars-Peter Clausen <[email protected]>
Cc: [email protected]
Cc: Deng-Cheng Zhu <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10148/
Signed-off-by: Ralf Baechle <[email protected]>
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For interrupts numbered after those of the interrupt controller, define
their numbers based upon the number of interrupts provided by the SoC
interrupt controller. This is in preparation for supporting newer
Ingenic SoCs which provide more interrupts.
Signed-off-by: Paul Burton <[email protected]>
Cc: Lars-Peter Clausen <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10143/
Signed-off-by: Ralf Baechle <[email protected]>
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Declare the JZ4740 interrupt controller for probe via DT using the
standard irqchip_init function, and make use of that function to probe
the controller by adding the appropriate node to the JZ4740 dtsi.
Signed-off-by: Paul Burton <[email protected]>
Cc: Ian Campbell <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Kumar Gala <[email protected]>
Cc: Lars-Peter Clausen <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Pawel Moll <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Brian Norris <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10135/
Signed-off-by: Ralf Baechle <[email protected]>
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In preparation for moving the JZ4740 interrupt controller driver to
drivers/irqchip, move arch_init_irq into setup.c such that everything
remaining in irq.c is related to said JZ4740 interrupt controller.
Signed-off-by: Paul Burton <[email protected]>
Cc: Lars-Peter Clausen <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Brian Norris <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10136/
Signed-off-by: Ralf Baechle <[email protected]>
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While at it, rename it because in drivers/irqchip no longer every CPU is
a MIPS.
Signed-off-by: Ralf Baechle <[email protected]>
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Ingenic have actually varied the vendor/company ID of the XBurst cores
across their range of SoCs, whilst keeping the product ID & revision
constant... Add definitions for vendor IDs known to be used in some of
Ingenic's newer SoCs, and handle them in the same way as the existing
Ingenic vendor ID from the JZ4740.
Signed-off-by: Paul Burton <[email protected]>
Co-authored-by: Paul Cercueil <[email protected]>
Cc: Lars-Peter Clausen <[email protected]>
Cc: [email protected]
Cc: Steven J. Hill <[email protected]>
Cc: Joshua Kinard <[email protected]>
Cc: Leonid Yegoshin <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Cc: Huacai Chen <[email protected]>
Cc: Markos Chandras <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10128/
Signed-off-by: Ralf Baechle <[email protected]>
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Update CPU overrides for the DEC port with the recent additions, shaving
off some effectively dead code:
text data bss dec hex filename
5586952 233132 5990368 11810452 b43694 vmlinux.32-old
5581248 233140 5990368 11804756 b42054 vmlinux.32-new
text data bss dec hex filename
6036936 356648 10756544 17150128 105b0b0 vmlinux.64-old
6029896 360752 10756544 17147192 105a538 vmlinux.64-new
The data size increase is due to the special alignment requirement of
`init_thread_union' aka `.data..init_task' moving it up to the nearest
page boundary and making the amount of padding at its front rely on how
far within a page text ends.
Signed-off-by: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10197/
Signed-off-by: Ralf Baechle <[email protected]>
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Add definitions for EntryLo register bits in mipsregs.h. The R4000
compatible ones are prefixed MIPS_ENTRYLO_ and the R3000 compatible ones
are prefixed R3K_ENTRYLO_.
These will be used in later patches.
Signed-off-by: James Hogan <[email protected]>
Cc: [email protected]
Cc: Maciej W. Rozycki <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10073/
Signed-off-by: Ralf Baechle <[email protected]>
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Add hazard macros to <asm/hazards.h> for the following hazards around
tlbr (TLB read) instructions, which are used in TLB dumping code and
some KVM TLB management code:
- mtc0_tlbr_hazard
Between mtc0 (Index) and tlbr. This is copied from mtc0_tlbw_hazard in
all cases on the assumption that tlbr always has similar data user
timings to tlbw.
- tlb_read_hazard
Between tlbr and mfc0 (various TLB registers). This is copied from
tlbw_use_hazard in all cases on the assumption that tlbr has similar
data writer characteristics to tlbw, and mfc0 has similar data user
characteristics to loads and stores.
Signed-off-by: James Hogan <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10078/
Signed-off-by: Ralf Baechle <[email protected]>
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Extra bcma buses may be totally different models, see following dump:
boardtype=0x0646
pci/1/1/boardtype=0x0545
pci/2/1/boardtype=0x62b
We need to detect them properly to allow drivers apply some board
specific hacks.
[[email protected]: folded in Rafal's fix.]
Signed-off-by: Rafał Miłecki <[email protected]>
Cc: [email protected]
Cc: Hauke Mehrtens <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10028/
Patchwork: https://patchwork.linux-mips.org/patch/10048/
Signed-off-by: Ralf Baechle <[email protected]>
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'spi/topic/davinci' into spi-next
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Due to the slightly odd way that new threads and processes start execution
when scheduled for the very first time they were bypassing the required
disable_msa call.
Signed-off-by: Ralf Baechle <[email protected]>
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Commit be0c37c985ed ("MIPS: Rearrange PTE bits into fixed positions.")
rearranged the PTE bits into fixed positions in preparation for the XPA
support. However, this patch broke R6 since it only took R2 cores
into consideration for the RI/XI bits leading to boot failures. We fix
this by adding the missing CONFIG_CPU_MIPSR6 definitions
Fixes: be0c37c985ed ("MIPS: Rearrange PTE bits into fixed positions.")
Cc: Steven J. Hill <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10208/
Signed-off-by: Markos Chandras <[email protected]>
Signed-off-by: Ralf Baechle <[email protected]>
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pci_dma_burst_advice() was added by e24c2d963a60 ("[PATCH] PCI: DMA
bursting advice") but apparently never used. Remove it.
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Michal Simek <[email protected]> # microblaze
CC: David S. Miller <[email protected]>
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So first of all, this atomic_scrub() function's naming is bad. It looks
like an atomic_t helper. Change it to edac_atomic_scrub().
The bigger problem is that this function is arch-specific and every new
arch which doesn't necessarily need that functionality still needs to
define it, otherwise EDAC doesn't compile.
So instead of doing that and including arch-specific headers, have each
arch define an EDAC_ATOMIC_SCRUB symbol which can be used in edac_mc.c
for ifdeffery. Much cleaner.
And we already are doing this with another symbol - EDAC_SUPPORT. This
is also much cleaner than having CONFIG_EDAC enumerate all the arches
which need/have EDAC support and drivers.
This way I can kill the useless edac.h header in tile too.
Acked-by: Ralf Baechle <[email protected]>
Acked-by: Michael Ellerman <[email protected]>
Acked-by: Chris Metcalf <[email protected]>
Acked-by: Ingo Molnar <[email protected]>
Acked-by: Russell King <[email protected]>
Cc: Benjamin Herrenschmidt <[email protected]>
Cc: Doug Thompson <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: "Maciej W. Rozycki" <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: Mauro Carvalho Chehab <[email protected]>
Cc: Paul Mackerras <[email protected]>
Cc: "Steven J. Hill" <[email protected]>
Cc: [email protected]
Signed-off-by: Borislav Petkov <[email protected]>
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Rename topology_thread_cpumask() to topology_sibling_cpumask()
for more consistency with scheduler code.
Signed-off-by: Bartosz Golaszewski <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
Acked-by: Russell King <[email protected]>
Acked-by: Catalin Marinas <[email protected]>
Cc: Benoit Cousson <[email protected]>
Cc: Fenghua Yu <[email protected]>
Cc: Guenter Roeck <[email protected]>
Cc: Jean Delvare <[email protected]>
Cc: Jonathan Corbet <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Oleg Drokin <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Rafael J. Wysocki <[email protected]>
Cc: Russell King <[email protected]>
Cc: Viresh Kumar <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
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Prepare for the case of multiple address spaces.
Reviewed-by: Radim Krcmar <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
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Signed-off-by: Christoph Hellwig <[email protected]>
Reported-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Jens Axboe <[email protected]>
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enabled
In general, non-atomic variants of user access functions must not sleep
if pagefaults are disabled.
Let's update all relevant comments in uaccess code. This also reflects
the might_sleep() checks in might_fault().
Reviewed-and-tested-by: Thomas Gleixner <[email protected]>
Signed-off-by: David Hildenbrand <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Cc: [email protected]
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
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Since set_mb() is really about an smp_mb() -- not a IO/DMA barrier
like mb() rename it to match the recent smp_load_acquire() and
smp_store_release().
Suggested-by: Linus Torvalds <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Signed-off-by: Ingo Molnar <[email protected]>
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Since we assume set_mb() to result in a single store followed by a
full memory barrier, employ WRITE_ONCE().
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Signed-off-by: Ingo Molnar <[email protected]>
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We removed the only user of this define in the rtmutex code. Get rid
of it.
Signed-off-by: Thomas Gleixner <[email protected]>
Cc: Sebastian Andrzej Siewior <[email protected]>
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Fix "BUG: using smp_processor_id() in preemptible" reported in accesses
to thread's FPU defaults: the value to initialise FSCR to at program
startup, the FCSR r/w mask and the contents of FIR in full FPU
emulation, removing a regression introduced with 9b26616c [MIPS: Respect
the ISA level in FCSR handling] and f6843626 [MIPS: math-emu: Set FIR
feature flags for full emulation].
Use `boot_cpu_data' to obtain the data from, following the approach that
`cpu_has_*' macros take and avoiding the call to `smp_processor_id' made
in the reference to `current_cpu_data'. The contents of FSCR have to be
consistent across processors in an SMP system, the settings there must
not change as a thread is migrated across processors. And the contents
of FIR are guaranteed to be consistent in FPU emulation, by definition.
Signed-off-by: Maciej W. Rozycki <[email protected]>
Tested-by: Ezequiel Garcia <[email protected]>
Tested-by: Paul Martin <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: James Hogan <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10030/
Signed-off-by: Ralf Baechle <[email protected]>
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CC arch/mips/kernel/smp.o
arch/mips/kernel/smp.c: In function ‘start_secondary’:
arch/mips/kernel/smp.c:149:2: error: passing argument 2 of ‘cpumask_set_cpu’ discards ‘volatile’ qualifier from pointer target type [-Werror]
cpumask_set_cpu(cpu, &cpu_callin_map);
^
In file included from ./arch/mips/include/asm/processor.h:14:0,
from ./arch/mips/include/asm/thread_info.h:15,
from include/linux/thread_info.h:54,
from include/asm-generic/preempt.h:4,
from arch/mips/include/generated/asm/preempt.h:1,
from include/linux/preempt.h:18,
from include/linux/interrupt.h:8,
from arch/mips/kernel/smp.c:24:
include/linux/cpumask.h:272:91: note: expected ‘struct cpumask *’ but argument is of type ‘volatile struct cpumask_t *’
static inline void cpumask_set_cpu(unsigned int cpu, struct cpumask *dstp)
^
arch/mips/kernel/smp.c: In function ‘smp_prepare_boot_cpu’:
arch/mips/kernel/smp.c:211:2: error: passing argument 2 of ‘cpumask_set_cpu’ discards ‘volatile’ qualifier from pointer target type [-Werror]
cpumask_set_cpu(0, &cpu_callin_map);
^
In file included from ./arch/mips/include/asm/processor.h:14:0,
from ./arch/mips/include/asm/thread_info.h:15,
from include/linux/thread_info.h:54,
from include/asm-generic/preempt.h:4,
from arch/mips/include/generated/asm/preempt.h:1,
from include/linux/preempt.h:18,
from include/linux/interrupt.h:8,
from arch/mips/kernel/smp.c:24:
include/linux/cpumask.h:272:91: note: expected ‘struct cpumask *’ but argument is of type ‘volatile struct cpumask_t *’
static inline void cpumask_set_cpu(unsigned int cpu, struct cpumask *dstp)
^
arch/mips/kernel/smp.c: In function ‘__cpu_up’:
arch/mips/kernel/smp.c:221:10: error: passing argument 2 of ‘cpumask_test_cpu’ discards ‘volatile’ qualifier from pointer target type [-Werror]
while (!cpumask_test_cpu(cpu, &cpu_callin_map))
^
In file included from ./arch/mips/include/asm/processor.h:14:0,
from ./arch/mips/include/asm/thread_info.h:15,
from include/linux/thread_info.h:54,
from include/asm-generic/preempt.h:4,
from arch/mips/include/generated/asm/preempt.h:1,
from include/linux/preempt.h:18,
from include/linux/interrupt.h:8,
from arch/mips/kernel/smp.c:24:
include/linux/cpumask.h:294:90: note: expected ‘const struct cpumask *’ but argument is of type ‘volatile struct cpumask_t *’
static inline int cpumask_test_cpu(int cpu, const struct cpumask *cpumask)
^
cc1: all warnings being treated as errors
make[2]: *** [arch/mips/kernel/smp.o] Error 1
make[1]: *** [arch/mips/kernel] Error 2
make: *** [arch/mips] Error 2
Signed-off-by: Ralf Baechle <[email protected]>
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We don't have any arch specific scatterlist now that parisc switched over
to the generic one.
Signed-off-by: Christoph Hellwig <[email protected]>
Signed-off-by: Jens Axboe <[email protected]>
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Set the OF node of the spi controller and use the generic GPIO based
chip select instead of the custom controller data. As the controller
data isn't used by any board just drop it.
Signed-off-by: Alban Bedel <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux
Pull final removal of deprecated cpus_* cpumask functions from Rusty Russell:
"This is the final removal (after several years!) of the obsolete
cpus_* functions, prompted by their mis-use in staging.
With these function removed, all cpu functions should only iterate to
nr_cpu_ids, so we finally only allocate that many bits when cpumasks
are allocated offstack"
* tag 'cpumask-next-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux: (25 commits)
cpumask: remove __first_cpu / __next_cpu
cpumask: resurrect CPU_MASK_CPU0
linux/cpumask.h: add typechecking to cpumask_test_cpu
cpumask: only allocate nr_cpumask_bits.
Fix weird uses of num_online_cpus().
cpumask: remove deprecated functions.
mips: fix obsolete cpumask_of_cpu usage.
x86: fix more deprecated cpu function usage.
ia64: remove deprecated cpus_ usage.
powerpc: fix deprecated CPU_MASK_CPU0 usage.
CPU_MASK_ALL/CPU_MASK_NONE: remove from deprecated region.
staging/lustre/o2iblnd: Don't use cpus_weight
staging/lustre/libcfs: replace deprecated cpus_ calls with cpumask_
staging/lustre/ptlrpc: Do not use deprecated cpus_* functions
blackfin: fix up obsolete cpu function usage.
parisc: fix up obsolete cpu function usage.
tile: fix up obsolete cpu function usage.
arm64: fix up obsolete cpu function usage.
mips: fix up obsolete cpu function usage.
x86: fix up obsolete cpu function usage.
...
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"This is the bulk of GPIO changes for the v4.1 development cycle:
- A new GPIO hogging mechanism has been added. This can be used on
boards that want to drive some GPIO line high, low, or set it as
input on boot and then never touch it again. For some embedded
systems this is bliss and simplifies things to a great extent.
- Some API cleanup and closure: gpiod_get_array() and
gpiod_put_array() has been added to get and put GPIOs in bulk as
was possible with the non-descriptor API.
- Encapsulate cross-calls to the pin control subsystem in
<linux/gpio/driver.h>. Now this should be the only header any GPIO
driver needs to include or something is wrong. Cleanups
restricting drivers to this include are welcomed if tested.
- Sort the GPIO Kconfig and split it into submenus, as it was
becoming and unstructured, illogical and unnavigatable mess. I
hope this is easier to follow. Menus that require a certain
subsystem like I2C can now be hidden nicely for example, still
working on others.
- New drivers:
- New driver for the Altera Soft GPIO.
- The F7188x driver now handles the F71869 and F71869A variants.
- The MIPS Loongson driver has been moved to drivers/gpio for
consolidation and cleanup.
- Cleanups:
- The MAX732x is converted to use the GPIOLIB_IRQCHIP
infrastructure.
- The PCF857x is converted to use the GPIOLIB_IRQCHIP
infrastructure.
- Radical cleanup of the OMAP driver.
- Misc:
- Enable the DWAPB GPIO for all architectures. This is a "hard
IP" block from Synopsys which has started to turn up in so
diverse architectures as X86 Quark, ARC and a slew of ARM
systems. So even though it's not an expander, it's generic
enough to be available for all.
- We add a mock GPIO on Crystalcove PMIC after a long discussion
with Daniel Vetter et al, tracing back to the shootout at the
kernel summit where DRM drivers and sub-componentization was
discussed. In this case a mock GPIO is assumed to be the best
compromise gaining some reuse of infrastructure without making
DRM drivers overly complex at the same time. Let's see"
* tag 'gpio-v4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (62 commits)
Revert "gpio: sch: use uapi/linux/pci_ids.h directly"
gpio: dwapb: remove dependencies
gpio: dwapb: enable for ARC
gpio: removing kfree remove functionality
gpio: mvebu: Fix mask/unmask managment per irq chip type
gpio: split GPIO drivers in submenus
gpio: move MFD GPIO drivers under their own comment
gpio: move BCM Kona Kconfig option
gpio: arrange SPI Kconfig symbols alphabetically
gpio: arrange PCI GPIO controllers alphabetically
gpio: arrange I2C Kconfig symbols alphabetically
gpio: arrange Kconfig symbols alphabetically
gpio: ich: Implement get_direction function
gpio: use (!foo) instead of (foo == NULL)
gpio: arizona: drop owner assignment from platform_drivers
gpio: max7300: remove 'ret' variable
gpio: use devm_kzalloc
gpio: sch: use uapi/linux/pci_ids.h directly
gpio: x-gene: fix devm_ioremap_resource() check
gpio: loongson: Add Loongson-3A/3B GPIO driver support
...
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Pull MIPS updates from Ralf Baechle:
"This is the main pull request for MIPS for Linux 4.1. Most
noteworthy:
- Add more Octeon-optimized crypto functions
- Octeon crypto preemption and locking fixes
- Little endian support for Octeon
- Use correct CSR to soft reset Octeons
- Support LEDs on the Octeon-based DSR-1000N
- Fix PCI interrupt mapping for the Octeon-based DSR-1000N
- Mark prom_free_prom_memory() as __init for a number of systems
- Support for Imagination's Pistachio SOC. This includes arch and
CLK bits. I'd like to merge pinctrl bits later
- Improve parallelism of csum_partial for certain pipelines
- Organize DTB files in subdirs like other architectures
- Implement read_sched_clock for all MIPS platforms other than
Octeon
- Massive series of 38 fixes and cleanups for the FPU emulator /
kernel
- Further FPU remulator work to support new features. This sits on a
separate branch which also has been pulled into the 4.1 KVM branch
- Clean up and fixes for the SEAD3 eval board; remove unused file
- Various updates for Netlogic platforms
- A number of small updates for Loongson 3 platforms
- Increase the memory limit for ATH79 platforms to 256MB
- A fair number of fixes and updates for BCM47xx platforms
- Finish the implementation of XPA support
- MIPS FDC support. No, not floppy controller but Fast Debug Channel :)
- Detect the R16000 used in SGI legacy platforms
- Fix Kconfig dependencies for the SSB bus support"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (265 commits)
MIPS: Makefile: Fix MIPS ASE detection code
MIPS: asm: elf: Set O32 default FPU flags
MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G
MIPS: Kconfig: Disable SMP/CPS for 64-bit
MIPS: Hibernate: flush TLB entries earlier
MIPS: smp-cps: cpu_set FPU mask if FPU present
MIPS: lose_fpu(): Disable FPU when MSA enabled
MIPS: ralink: add missing symbol for RALINK_ILL_ACC
MIPS: ralink: Fix bad config symbol in PCI makefile.
SSB: fix Kconfig dependencies
MIPS: Malta: Detect and fix bad memsize values
Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores."
MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard.
MIPS: Fix cpu_has_mips_r2_exec_hazard.
MIPS: kernel: entry.S: Set correct ISA level for mips_ihb
MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case
MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes
MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter
MIPS: unaligned: Fix regular load/store instruction emulation for EVA
MIPS: unaligned: Surround load/store macros in do {} while statements
...
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