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2018-07-17mips: unify prom_putchar() declarationsAlexander Sverdlin3-2/+2
prom_putchar() is used centrally in early printk infrastructure therefore at least MIPS should agree on the function return type. [[email protected]: - Include linux/types.h in asm/setup.h to gain the bool typedef before we start include asm/setup.h elsewhere. - Include asm/setup.h in all files that use or define prom_putchar(). - Also standardise on signed rather than unsigned char argument.] Signed-off-by: Alexander Sverdlin <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19842/ Cc: [email protected] Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: Jonas Gorski <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: Kate Stewart <[email protected]> Cc: Philippe Ombredanne <[email protected]>
2018-07-17Merge tag 'v4.18-rc5' into locking/core, to pick up fixesIngo Molnar3-6/+17
Signed-off-by: Ingo Molnar <[email protected]>
2018-07-12MIPS: Cleanup R10000_LLSC_WAR logic in atomic.hJoshua Kinard1-147/+32
This patch reduces down the conditionals in MIPS atomic code that deal with a silicon bug in early R10000 cpus that required a workaround of a branch-likely instruction following a store-conditional in order to to guarantee the whole ll/sc sequence is atomic. As the only real difference is a branch-likely instruction (beqzl) over a standard branch (beqz), the conditional is reduced down to a single preprocessor check at the top to pick the required instruction. This requires writing the uses in assembler, thus we discard the non-R10000 case that uses a mixture of a C do...while loop with embedded assembler that was added back in commit 7837314d141c ("MIPS: Get rid of branches to .subsections."). A note found in the git log for commit 5999eca25c1f ("[MIPS] Improve branch prediction in ll/sc atomic operations.") is also addressed. The macro definition for the branch instruction and the code comment derives from a patch sent in earlier by Paul Burton for various cmpxchg cleanups. [[email protected]: - Minor whitespace fix for checkpatch.] Signed-off-by: Joshua Kinard <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/17736/ Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: "Maciej W. Rozycki" <[email protected]> Cc: [email protected]
2018-07-12MIPS: Fix delay slot bug in `atomic*_sub_if_positive' for R10000_LLSC_WARJoshua Kinard1-20/+12
This patch fixes an old bug in MIPS ll/sc atomics, in the `atomic_sub_if_positive' and `atomic64_sub_if_positive' functions, for the R10000_LLSC_WAR case where the result of the subu/dsubu instruction would potentially not be made available to the sc/scd instruction due to being in the delay-slot of the branch-likely (beqzl) instruction. This also removes the need for the `noreorder' directive, allowing GAS to use delay slot scheduling as needed. The same fix is also applied to the standard branch (beqz) case in preparation for a follow-up patch that will cleanup/merge the R10000_LLSC_WAR and non-R10K sections together. Signed-off-by: Joshua Kinard <[email protected]> Signed-off-by: Paul Burton <[email protected]> Tested-by: Joshua Kinard <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/17735/ Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: "Maciej W. Rozycki" <[email protected]> Cc: [email protected]
2018-07-10mips: mm: Discard ioremap_uncached_accelerated() methodSerge Semin1-6/+2
Adaptive ioremap_wc() method is now available as of commit 9748e33e26c6 ("mips: mm: Create UCA-based ioremap_wc() method"). We can use it to obtain UnCached Accelerated (UCA) mappings safely on all MIPS systems, and so we don't need the MIPS-specific ioremap_uncached_accelerated() any longer. This macro hard-coded the UCA Cache Coherency Attribute (CCA) in a manner that isn't safe for kernels that may run on different CPUs, and it is also entirely unused so we can trivially remove it. [[email protected]: - Reword the commit message a little. - Remove CC stable.] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19790/ Cc: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2018-07-10mips: mm: Create UCA-based ioremap_wc() methodSerge Semin1-0/+23
Modern MIPS cores (like P5600/6600, M5150/6520, end so on) which got L2-cache on chip also can enable a special type Cache-Coherency attribute (CCA) named UnCached Accelerated attribute (UCA). In this way uncached accelerated accesses are treated the same way as non-accelerated uncached accesses, but uncached stores are gathered together for more efficient bus utilization. So to speak this CCA enables uncached transactions to better utilize bus bandwidth via burst transactions. This is exactly why ioremap_wc() method has been introduced in Linux. Alas MIPS-platform code hasn't implemented it so far, instead default one has been used which was an alias to ioremap_nocache. In order to fix this we added MIPS-specific ioremap_wc() macro substituted by generic __ioremap_mode() method call with writecombine CPU-info field passed. It shall create real ioremap_wc() method if CPU-cache supports UCA feature and fall-back to _CACHE_UNCACHED attribute if one doesn't. Additionally platform-specific io.h shall declare ARCH_HAS_IOREMAP_WC macro as indication of architectural definition of ioremap_wc() (similar to x86/powerpc). [[email protected]: - Remove CC stable, this is new functionality.] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19789/ Cc: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2018-07-04net: Add a new socket option for a future transmit time.Richard Cochran1-0/+3
This patch introduces SO_TXTIME. User space enables this option in order to pass a desired future transmit time in a CMSG when calling sendmsg(2). The argument to this socket option is a 8-bytes long struct provided by the uapi header net_tstamp.h defined as: struct sock_txtime { clockid_t clockid; u32 flags; }; Note that new fields were added to struct sock by filling a 2-bytes hole found in the struct. For that reason, neither the struct size or number of cachelines were altered. Signed-off-by: Richard Cochran <[email protected]> Signed-off-by: Jesus Sanchez-Palencia <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2018-07-03MIPS: Octeon: Simplify CIU register functions.Steven J. Hill1-94/+22
Collapse and simplify switch statements in functions. Signed-off-by: Steven J. Hill <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19713/ Cc: [email protected] Cc: Chandrakala Chavva <[email protected]>
2018-07-03MIPS: Octeon: Create simple macro for CIU registers.Steven J. Hill1-28/+32
Create new CVMX_CIU_ADDR macro to improve readability. Signed-off-by: Steven J. Hill <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19712/ Cc: [email protected] Cc: Chandrakala Chavva <[email protected]>
2018-07-03MIPS: Octeon: Remove all unused CIU macros.Steven J. Hill1-52/+18
Get rid of all unused CIU macros and sort them. Verified with 'make allyesconfig' build test. [[email protected]: - Also checked via convoluted grep invocation for use of all removed macros within arch/mips/ & drivers/.] Signed-off-by: Steven J. Hill <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19710/ Cc: [email protected] Cc: Chandrakala Chavva <[email protected]>
2018-07-03MIPS: Octeon: Convert CIU types to use bitfields.Steven J. Hill1-128/+56
Convert remaining structures to use __BITFIELD_FIELD macro. Also straighten up the description text and whitespace. Signed-off-by: Steven J. Hill <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19709/ Cc: [email protected] Cc: Chandrakala Chavva <[email protected]>
2018-07-03MIPS: Octeon: Unify QLM data types in CIU header.Steven J. Hill1-37/+2
Data types 'cvmx_ciu_qlm0' and 'cvmx_ciu_qlm1' are identical in their usage and structure. Combine them and update the PCIe code. Signed-off-by: Steven J. Hill <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19708/ Cc: [email protected] Cc: Chandrakala Chavva <[email protected]>
2018-07-03MIPS: Octeon: Remove unused CIU types.Steven J. Hill1-9629/+0
Remove all unused data types. Verified with a 'make allyesconfig' and Cavium platform. [[email protected]: - Also checked via convoluted grep invocation for use of all removed structs & unions within arch/mips/ & drivers/.] Signed-off-by: Steven J. Hill <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19711/ Cc: [email protected] Cc: Chandrakala Chavva <[email protected]>
2018-06-26Merge branch 'linus' into perf/core, to pick up fixesIngo Molnar3-6/+17
Signed-off-by: Ingo Molnar <[email protected]>
2018-06-24MIPS: Schedule on CPUs we need to lose FPU for a mode switchPaul Burton1-2/+0
Commit 6b8322576e9d ("MIPS: Force CPUs to lose FP context during mode switches") ensures that we react to PR_SET_FP_MODE prctl syscalls quickly by broadcasting an IPI in order to cause CPUs to lose FPU access when necessary. Whilst it achieves that, unfortunately it causes all sorts of strange race conditions because: 1) The IPI may arrive at a point where the FPU is in the process of being enabled, but that process is not yet complete leading to a state we aren't prepared to handle. For example: [ 370.215903] do_cpu invoked from kernel context![#1]: [ 370.221064] CPU: 0 PID: 963 Comm: fp-prctl Not tainted 4.9.0-rc5-00323-g210db32-dirty #226 [ 370.229420] task: a8000000fd672e00 task.stack: a8000000fd630000 [ 370.235399] $ 0 : 0000000000000000 0000000000000001 0000000000000001 a8000000fd630000 [ 370.243882] $ 4 : a8000000fd672e00 0000000000000000 0000000000000453 0000000000000000 [ 370.252317] $ 8 : 0000000000000000 a8000000fd637c28 1000000000000000 0000000000000010 [ 370.260753] $12 : 00000000140084e0 ffffffff80109c00 0000000000000000 0000000000000002 [ 370.269179] $16 : ffffffff8092f080 a8000000fd672e00 ffffffff80107fe8 a8000000fd485000 [ 370.277612] $20 : ffffffff8084d328 ffffffff80940000 0000000000000009 ffffffff80930000 [ 370.286038] $24 : 0000000000000000 900000001612048c [ 370.294476] $28 : a8000000fd630000 a8000000fd637ac0 ffffffff80937300 ffffffff8010807c [ 370.302909] Hi : 0000000000000000 [ 370.306595] Lo : 0000000000000200 [ 370.310376] epc : ffffffff80115d38 _save_fp+0x10/0xa0 [ 370.315784] ra : ffffffff8010807c prepare_for_fp_mode_switch+0x94/0x1b0 [ 370.322707] Status: 140084e2 KX SX UX KERNEL EXL [ 370.327980] Cause : 1080002c (ExcCode 0b) [ 370.332091] PrId : 0001a428 (MIPS P6600) [ 370.336179] Modules linked in: [ 370.339486] Process fp-prctl (pid: 963, threadinfo=a8000000fd630000, task=a8000000fd672e00, tls=00000000756e67d0) [ 370.349724] Stack : 0000000000000000 a8000000fd557dc0 0000000000000000 ffffffff801ca8e0 [ 370.358161] 0000000000000000 a8000000fd637b9c 0000000000000009 ffffffff80923780 [ 370.366575] ffffffff80850000 ffffffff8011610c 00000000000000b8 ffffffff801a5084 [ 370.374989] ffffffff8084a370 ffffffff8084a388 ffffffff80923780 ffffffff80923828 [ 370.383395] 0000000000010000 ffffffff809237a8 0000000000020000 ffffffff80a40000 [ 370.391817] 000000000000007c 00000000004a0000 00000000756dedd0 ffffffff801a5188 [ 370.400230] a800000002014900 0000000000000001 ffffffff80923780 0000000080923828 [ 370.408644] ffffffff80923780 ffffffff80923780 ffffffff80923828 ffffffff801a521c [ 370.417066] ffffffff80923780 ffffffff80923828 0000000000010000 ffffffff801a8f84 [ 370.425472] ffffffff80a40000 a8000000fd637c20 ffffffff80a39240 0000000000000001 [ 370.433885] ... [ 370.436562] Call Trace: [ 370.439222] [<ffffffff80115d38>] _save_fp+0x10/0xa0 [ 370.444305] [<ffffffff8010807c>] prepare_for_fp_mode_switch+0x94/0x1b0 [ 370.451035] [<ffffffff801ca8e0>] flush_smp_call_function_queue+0xf8/0x230 [ 370.457991] [<ffffffff8011610c>] ipi_call_interrupt+0xc/0x20 [ 370.463814] [<ffffffff801a5084>] __handle_irq_event_percpu+0xc4/0x1a8 [ 370.470404] [<ffffffff801a5188>] handle_irq_event_percpu+0x20/0x68 [ 370.476734] [<ffffffff801a521c>] handle_irq_event+0x4c/0x88 [ 370.482486] [<ffffffff801a8f84>] handle_edge_irq+0x12c/0x210 [ 370.488316] [<ffffffff801a47a0>] generic_handle_irq+0x38/0x48 [ 370.494280] [<ffffffff804a2dbc>] gic_handle_shared_int+0x194/0x268 [ 370.500616] [<ffffffff801a47a0>] generic_handle_irq+0x38/0x48 [ 370.506529] [<ffffffff80107e60>] do_IRQ+0x18/0x28 [ 370.511445] [<ffffffff804a1524>] plat_irq_dispatch+0xc4/0x140 [ 370.517339] [<ffffffff80106230>] ret_from_irq+0x0/0x4 [ 370.522583] [<ffffffff8010fad4>] do_ri+0x4fc/0x7e8 [ 370.527546] [<ffffffff80106220>] ret_from_exception+0x0/0x10 2) The IPI may arrive during kernel use of the FPU, since we generally only disable preemption around use of the FPU & leave interrupts enabled. This can lead to us unexpectedly losing access to the FPU in places where it previously had not been possible. For example: do_cpu invoked from kernel context![#2]: CPU: 2 PID: 7338 Comm: fp-prctl Tainted: G D 4.7.0-00424-g49b0c82 #2 task: 838e4000 ti: 88d38000 task.ti: 88d38000 $ 0 : 00000000 00000001 ffffffff 88d3fef8 $ 4 : 838e4000 88d38004 00000000 00000001 $ 8 : 3400fc01 801f8020 808e9100 24000000 $12 : dbffffff 807b69d8 807b0000 00000000 $16 : 00000000 80786150 00400fc4 809c0398 $20 : 809c0338 0040273c 88d3ff28 808e9d30 $24 : 808e9d30 00400fb4 $28 : 88d38000 88d3fe88 00000000 8011a2ac Hi : 0040273c Lo : 88d3ff28 epc : 80114178 _restore_fp+0x10/0xa0 ra : 8011a2ac mipsr2_decoder+0xd5c/0x1660 Status: 1400fc03 KERNEL EXL IE Cause : 1080002c (ExcCode 0b) PrId : 0001a920 (MIPS I6400) Modules linked in: Process fp-prctl (pid: 7338, threadinfo=88d38000, task=838e4000, tls=766527d0) Stack : 00000000 00000000 00000000 88d3fe98 00000000 00000000 809c0398 809c0338 808e9100 00000000 88d3ff28 00400fc4 00400fc4 0040273c 7fb69e18 004a0000 004a0000 004a0000 7664add0 8010de18 00000000 00000000 88d3fef8 88d3ff28 808e9100 00000000 766527d0 8010e534 000c0000 85755000 8181d580 00000000 00000000 00000000 004a0000 00000000 766527d0 7fb69e18 004a0000 80105c20 ... Call Trace: [<80114178>] _restore_fp+0x10/0xa0 [<8011a2ac>] mipsr2_decoder+0xd5c/0x1660 [<8010de18>] do_ri+0x90/0x6b8 [<80105c20>] ret_from_exception+0x0/0x10 At first glance a simple fix may seem to be to disable interrupts around kernel use of the FPU rather than merely preemption, however this would introduce further overhead outside of the mode switch path & doesn't solve the third problem: 3) The IPI may arrive whilst the kernel is running code that will lead to a preempt_disable() call & FPU usage soon. If this happens then the IPI will be serviced & we'll proceed to enable an FPU whilst the mode switch is in progress, leading to strange & inconsistent behaviour. Further to all of this is a separate but related problem: 4) There are various paths through which we may enable the FPU without the user having triggered a coprocessor 1 disabled exception. These paths are those in which we emulate instructions & then enable the FPU with the expectation that the user might execute an FP instruction shortly afterwards. However these paths have not previously checked whether an FP mode switch is underway for the task, and therefore could enable the FPU whilst such a mode switch is in progress leading to strange & inconsistent behaviour for user code. This patch fixes all of the above by taking a step back & re-examining our approach to FP mode switches. Up until now we have taken these basic steps: a) Prevent any threads that are part of the affected process from being able to obtain ownership of the FPU. b) Cause any threads that are part of the affected process and already have ownership of an FPU to lose it. c) Set the thread flags for each thread that is part of the affected process to reflect the new FP mode. d) Allow threads to obtain ownership of the FPU again. This approach is however more complex than necessary. All that we really require is that the mode switch has occurred for all threads that are part of the affected process before mips_set_process_fp_mode(), and thus the PR_SET_FP_MODE prctl() syscall, returns. This doesn't require that we stop threads from owning or using an FPU whilst a mode switch occurs, only that we force them to relinquish it after the mode switch has occurred such that they next own an FPU with the correct mode configured. Our basic steps therefore simplify to: A) Set the thread flags for each thread that is part of the affected process to reflect the new FP mode. B) Cause any threads that are part of the affected process and already have ownership of an FPU to lose it. We implement B) by forcing each CPU which might be running a thread which is part of the affected process to schedule a no-op function, which causes the affected thread to lose its FPU ownership when it is descheduled. The end result is simpler FP mode switching with less overhead in the FPU enable path (ie. enable_restore_fp_context()) and fewer moving parts. Signed-off-by: Paul Burton <[email protected]> Fixes: 9791554b45a2 ("MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS") Fixes: 6b8322576e9d ("MIPS: Force CPUs to lose FP context during mode switches") Cc: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: stable <[email protected]> # v4.0+
2018-06-24MIPS: remove unneeded includes from dma-mapping.hChristoph Hellwig1-8/+0
Keep this file as light as possible as it gets pulled into every driver using dma mapping APIs. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19552/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: remove the old dma-default implementationChristoph Hellwig2-76/+0
Now unused. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19551/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: bmips: use generic dma noncoherent opsChristoph Hellwig2-70/+0
Provide phys_to_dma/dma_to_phys helpers, and the special arch_sync_dma_for_cpu_all hook, everything else is generic Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19550/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: jazz: split dma mapping operations from dma-defaultChristoph Hellwig2-61/+4
Jazz actually has a very basic IOMMU, so split the ops into a separate implementation from the generic default support (which is about to go away anyway). Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19548/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: ath25: use generic dma noncoherent opsChristoph Hellwig1-71/+0
Provide phys_to_dma/dma_to_phys helpers only if PCI support is enabled, everything else is generic. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19547/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: IP32: use generic dma noncoherent opsChristoph Hellwig1-92/+0
Provide phys_to_dma/dma_to_phys helpers, everything else is generic. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19546/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: loongson64: use generic dma noncoherent opsChristoph Hellwig1-69/+0
Provide phys_to_dma/dma_to_phys helpers, everything else is generic. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19545/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: use generic dma noncoherent ops for simple noncoherent platformsChristoph Hellwig1-0/+2
Convert everything not overriding dma-coherence.h to the generic noncoherent ops. The new dma-noncoherent.c file duplicates a lot of the code in dma-default.c, but that file will be gone by the end of this series. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19544/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: IP27: use dma_direct_opsChristoph Hellwig1-70/+0
IP27 is coherent and has a reasonably direct mapping, just with a little per-bus offset added into the dma address. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19542/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: use dma_direct_ops for coherent I/OChristoph Hellwig1-1/+1
Switch the simple cache coherent architectures that don't require any DMA address translation to dma_direct_ops. We'll soon use at least parts of the direct DMA ops implementation for all platforms, so select the symbol globally. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19540/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: loongson: remove loongson-3 handling from dma-coherence.hChristoph Hellwig1-15/+1
Loongson3 is dma coherent and uses swiotlb, so it will never used any of these helpers. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19541/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: Octeon: move swiotlb declarations out of dma-coherence.hChristoph Hellwig2-18/+3
No need to pull them into a global header. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19538/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: Octeon: remove mips dma-default stubsChristoph Hellwig1-48/+0
Octeon doesn't use the dma-default code, and now doesn't built it either, so these stubs can be removed. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19537/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: make the default mips dma implementation optionalChristoph Hellwig1-1/+3
Octeon and loonson64 already don't use it at all, and we're going to migrate more plaforms away from it. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19536/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: remove the mips_dma_map_ops indirectionChristoph Hellwig1-2/+2
And use mips_default_dma_map_ops directly. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19535/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: consolidate the swiotlb implementationsChristoph Hellwig4-22/+21
Octeon and Loongson share exactly the same code, move it into a common implementation, and use that implementation directly from get_arch_dma_ops. Also provide the expected dma-direct.h helpers directly instead of delegating to platform dma-coherence.h headers. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19534/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: Octeon: refactor swiotlb codeChristoph Hellwig1-2/+0
Share a common set of swiotlb operations, and to instead branch out in __phys_to_dma/__dma_to_phys for the PCI vs non-PCI case. Also use const structures for the PCI methods so that attackers can't use them as exploit vectors. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19532/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: remove CONFIG_DMA_COHERENTChristoph Hellwig2-5/+4
We can just check for !CONFIG_DMA_NONCOHERENT instead and simplify things a lot. Signed-off-by: Christoph Hellwig <[email protected]> Reviewed-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19530/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: simplify CONFIG_DMA_NONCOHERENT ifdefsChristoph Hellwig1-2/+2
CONFIG_DMA_MAYBE_COHERENT already selects CONFIG_DMA_NONCOHERENT, so we can remove the extra conditions. Signed-off-by: Christoph Hellwig <[email protected]> Reviewed-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19529/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: remove a dead ifdef from mach-ath25/dma-coherence.hChristoph Hellwig1-5/+0
ath25 is alwas non-coherent, so keeping these ifdefs doesn't make any sense. Signed-off-by: Christoph Hellwig <[email protected]> Reviewed-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19528/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-21atomics/treewide: Make unconditional inc/dec ops optionalMark Rutland1-38/+0
Many of the inc/dec ops are mandatory, but for most architectures inc/dec are simply trivial wrappers around their corresponding add/sub ops. Let's make all the inc/dec ops optional, so that we can get rid of these boilerplate wrappers. The instrumented atomics are updated accordingly. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <[email protected]> Reviewed-by: Will Deacon <[email protected]> Acked-by: Peter Zijlstra (Intel) <[email protected]> Acked-by: Palmer Dabbelt <[email protected]> Cc: Boqun Feng <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/lkml/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
2018-06-21atomics/treewide: Make test ops optionalMark Rutland1-84/+0
Some of the atomics return the result of a test applied after the atomic operation, and almost all architectures implement these as trivial wrappers around the underlying atomic. Specifically: * <atomic>_inc_and_test(v) is (<atomic>_inc_return(v) == 0) * <atomic>_dec_and_test(v) is (<atomic>_dec_return(v) == 0) * <atomic>_sub_and_test(i, v) is (<atomic>_sub_return(i, v) == 0) * <atomic>_add_negative(i, v) is (<atomic>_add_return(i, v) < 0) Rather than have these definitions duplicated in all architectures, with minor inconsistencies in formatting and documentation, let's make these operations optional, with default fallbacks as above. Implementations must now provide a preprocessor symbol. The instrumented atomics are updated accordingly. Both x86 and m68k have custom implementations, which are left as-is, given preprocessor symbols to avoid being overridden. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <[email protected]> Reviewed-by: Will Deacon <[email protected]> Acked-by: Geert Uytterhoeven <[email protected]> Acked-by: Peter Zijlstra (Intel) <[email protected]> Acked-by: Palmer Dabbelt <[email protected]> Cc: Boqun Feng <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/lkml/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
2018-06-21atomics/treewide: Make atomic64_fetch_add_unless() optionalMark Rutland1-24/+0
Architectures with atomic64_fetch_add_unless() provide a preprocessor symbol if they do so, and all other architectures have trivial C implementations of atomic64_add_unless() which are near-identical. Let's unify the trivial definitions of atomic64_fetch_add_unless() in <linux/atomic.h>, so that we always have both atomic64_fetch_add_unless() and atomic64_add_unless() with less boilerplate code. This means that atomic64_add_unless() is always implemented in core code, and the instrumented atomics are updated accordingly. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <[email protected]> Reviewed-by: Will Deacon <[email protected]> Acked-by: Peter Zijlstra (Intel) <[email protected]> Cc: Boqun Feng <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/lkml/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
2018-06-21atomics/treewide: Make atomic_fetch_add_unless() optionalMark Rutland1-24/+0
Several architectures these have a near-identical implementation based on atomic_read() and atomic_cmpxchg() which we can instead define in <linux/atomic.h>, so let's do so, using something close to the existing x86 implementation with try_cmpxchg(). Where an architecture provides its own atomic_fetch_add_unless(), it must define a preprocessor symbol for it. The instrumented atomics are updated accordingly. Note that arch/arc's existing atomic_fetch_add_unless() had redundant barriers, as these are already present in its atomic_cmpxchg() implementation. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Will Deacon <[email protected]> Acked-by: Geert Uytterhoeven <[email protected]> Acked-by: Peter Zijlstra (Intel) <[email protected]> Acked-by: Palmer Dabbelt <[email protected]> Cc: Boqun Feng <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Vineet Gupta <[email protected]> Link: https://lore.kernel.org/lkml/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
2018-06-21atomics/treewide: Make atomic64_inc_not_zero() optionalMark Rutland1-2/+0
We define a trivial fallback for atomic_inc_not_zero(), but don't do the same for atomic64_inc_not_zero(), leading most architectures to define the same boilerplate. Let's add a fallback in <linux/atomic.h>, and remove the redundant implementations. Note that atomic64_add_unless() is always defined in <linux/atomic.h>, and promotes its arguments to the requisite types, so we need not do this explicitly. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <[email protected]> Reviewed-by: Will Deacon <[email protected]> Acked-by: Peter Zijlstra (Intel) <[email protected]> Acked-by: Palmer Dabbelt <[email protected]> Cc: Boqun Feng <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/lkml/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
2018-06-21atomics/treewide: Rename __atomic_add_unless() => atomic_fetch_add_unless()Mark Rutland1-2/+2
While __atomic_add_unless() was originally intended as a building-block for atomic_add_unless(), it's now used in a number of places around the kernel. It's the only common atomic operation named __atomic*(), rather than atomic_*(), and for consistency it would be better named atomic_fetch_add_unless(). This lack of consistency is slightly confusing, and gets in the way of scripting atomics. Given that, let's clean things up and promote it to an official part of the atomics API, in the form of atomic_fetch_add_unless(). This patch converts definitions and invocations over to the new name, including the instrumented version, using the following script: ---- git grep -w __atomic_add_unless | while read line; do sed -i '{s/\<__atomic_add_unless\>/atomic_fetch_add_unless/}' "${line%%:*}"; done git grep -w __arch_atomic_add_unless | while read line; do sed -i '{s/\<__arch_atomic_add_unless\>/arch_atomic_fetch_add_unless/}' "${line%%:*}"; done ---- Note that we do not have atomic{64,_long}_fetch_add_unless(), which will be introduced by later patches. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <[email protected]> Reviewed-by: Will Deacon <[email protected]> Acked-by: Geert Uytterhoeven <[email protected]> Acked-by: Peter Zijlstra (Intel) <[email protected]> Acked-by: Palmer Dabbelt <[email protected]> Cc: Boqun Feng <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/lkml/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
2018-06-21MIPS/kprobes: Remove jprobe implementationMasami Hiramatsu1-13/+0
Remove arch dependent setjump/longjump functions and unused fields in kprobe_ctlblk for jprobes from arch/mips. Signed-off-by: Masami Hiramatsu <[email protected]> Acked-by: Thomas Gleixner <[email protected]> Cc: Ananth N Mavinakayanahalli <[email protected]> Cc: Andrew Morton <[email protected]> Cc: James Hogan <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: Steven Rostedt <[email protected]> Cc: [email protected] Cc: [email protected] Link: https://lore.kernel.org/lkml/152942451058.15209.3459785416221980965.stgit@devbox Signed-off-by: Ingo Molnar <[email protected]>
2018-06-19MIPS: Wire up io_pgetevents syscallPaul Burton1-6/+9
Wire up the io_pgetevents syscall that was introduced by commit 7a074e96dee6 ("aio: implement io_pgetevents"). Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19593/ Cc: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected]
2018-06-19MIPS: Wire up the restartable sequences (rseq) syscallPaul Burton1-6/+9
Wire up the restartable sequences (rseq) syscall for MIPS. This was introduced by commit d7822b1e24f2 ("rseq: Introduce restartable sequences system call") & MIPS now supports the prerequisites. Signed-off-by: Paul Burton <[email protected]> Reviewed-by: James Hogan <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19525/ Cc: Ralf Baechle <[email protected]> Cc: Mathieu Desnoyers <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Paul E. McKenney <[email protected]> Cc: Boqun Feng <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-19MIPS: io: Add barrier after register read in inX()Huacai Chen1-0/+2
While a barrier is present in the outX() functions before the register write, a similar barrier is missing in the inX() functions after the register read. This could allow memory accesses following inX() to observe stale data. This patch is very similar to commit a1cc7034e33d12dc1 ("MIPS: io: Add barrier after register read in readX()"). Because war_io_reorder_wmb() is both used by writeX() and outX(), if readX() need a barrier then so does inX(). Cc: [email protected] Signed-off-by: Huacai Chen <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19516/ Signed-off-by: Paul Burton <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: Fuxin Zhang <[email protected]> Cc: Zhangjin Wu <[email protected]> Cc: Huacai Chen <[email protected]>
2018-06-18MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratumTokunori Ikegami1-0/+3
The erratum and workaround are described by BCM5300X-ES300-RDS.pdf as below. R10: PCIe Transactions Periodically Fail Description: The BCM5300X PCIe does not maintain transaction ordering. This may cause PCIe transaction failure. Fix Comment: Add a dummy PCIe configuration read after a PCIe configuration write to ensure PCIe configuration access ordering. Set ES bit of CP0 configu7 register to enable sync function so that the sync instruction is functional. Resolution: hndpci.c: extpci_write_config() hndmips.c: si_mips_init() mipsinc.h CONF7_ES This is fixed by the CFE MIPS bcmsi chipset driver also for BCM47XX. Also the dummy PCIe configuration read is already implemented in the Linux BCMA driver. Enable ExternalSync in Config7 when CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y too so that the sync instruction is externalised. Signed-off-by: Tokunori Ikegami <[email protected]> Reviewed-by: Paul Burton <[email protected]> Acked-by: Hauke Mehrtens <[email protected]> Cc: Chris Packham <[email protected]> Cc: Rafał Miłecki <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/19461/ Signed-off-by: James Hogan <[email protected]>
2018-06-12Merge tag 'mips_4.18' of ↵Linus Torvalds7-12/+17
git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS updates from James Hogan: "These are the main MIPS changes for 4.18. Rough overview: - MAINTAINERS: Add Paul Burton as MIPS co-maintainer - Misc: Generic compiler intrinsics, Y2038 improvements, Perf+MT fixes - Platform support: Netgear WNR1000 V3, Microsemi Ocelot integrated switch, Ingenic watchdog cleanups More detailed summary: Maintainers: - Add Paul Burton as MIPS co-maintainer, as I soon won't have access to much MIPS hardware, nor enough time to properly maintain MIPS on my own. Miscellaneous: - Use generic GCC library routines from lib/ - Add notrace to generic ucmpdi2 implementation - Rename compiler intrinsic selects to GENERIC_LIB_* - vmlinuz: Use generic ashldi3 - y2038: Convert update/read_persistent_clock() to *_clock64() - sni: Remove read_persistent_clock() - perf: Fix perf with MT counting other threads - Probe for per-TC perf counters in cpu-probe.c - Use correct VPE ID for VPE tracing Minor cleanups: - Avoid unneeded built-in.a in DTS dirs - sc-debugfs: Re-use kstrtobool_from_user - memset.S: Reinstate delay slot indentation - VPE: Fix spelling "uneeded" -> "Unneeded" Platform support: BCM47xx: - Add support for Netgear WNR1000 V3 - firmware: Support small NVRAM partitions - Use __initdata for LEDs platform data Ingenic: - Watchdog driver & platform code improvements: - Disable clock after stopping counter - Use devm_* functions - Drop module remove function - Move platform reset code to restart handler in driver - JZ4740: Convert watchdog instantiation to DT - JZ4780: Fix watchdog DT node - qi_lb60_defconfig: Enable watchdog driver Microsemi: - Ocelot: Add support for integrated switch - pcb123: Connect phys to ports" * tag 'mips_4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits) MAINTAINERS: Add Paul Burton as MIPS co-maintainer MIPS: ptrace: Make FPU context layout comments match reality MIPS: memset.S: Reinstate delay slot indentation MIPS: perf: Fix perf with MT counting other threads MIPS: perf: Use correct VPE ID when setting up VPE tracing MIPS: perf: More robustly probe for the presence of per-tc counters MIPS: Probe for MIPS MT perf counters per TC MIPS: mscc: Connect phys to ports on ocelot_pcb123 MIPS: mscc: Add switch to ocelot MIPS: JZ4740: Drop old platform reset code MIPS: qi_lb60: Enable the jz4740-wdt driver MIPS: JZ4780: dts: Fix watchdog node MIPS: JZ4740: dts: Add bindings for the jz4740-wdt driver watchdog: JZ4740: Drop module remove function watchdog: JZ4740: Register a restart handler watchdog: JZ4740: Use devm_* functions watchdog: JZ4740: Disable clock after stopping counter MIPS: VPE: Fix spelling mistake: "uneeded" -> "unneeded" MIPS: Re-use kstrtobool_from_user() MIPS: Convert update_persistent_clock() to update_persistent_clock64() ...
2018-06-04Merge branch 'timers-2038-for-linus' of ↵Linus Torvalds4-41/+94
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull time/Y2038 updates from Thomas Gleixner: - Consolidate SySV IPC UAPI headers - Convert SySV IPC to the new COMPAT_32BIT_TIME mechanism - Cleanup the core interfaces and standardize on the ktime_get_* naming convention. - Convert the X86 platform ops to timespec64 - Remove the ugly temporary timespec64 hack * 'timers-2038-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits) x86: Convert x86_platform_ops to timespec64 timekeeping: Add more coarse clocktai/boottime interfaces timekeeping: Add ktime_get_coarse_with_offset timekeeping: Standardize on ktime_get_*() naming timekeeping: Clean up ktime_get_real_ts64 timekeeping: Remove timespec64 hack y2038: ipc: Redirect ipc(SEMTIMEDOP, ...) to compat_ksys_semtimedop y2038: ipc: Enable COMPAT_32BIT_TIME y2038: ipc: Use __kernel_timespec y2038: ipc: Report long times to user space y2038: ipc: Use ktime_get_real_seconds consistently y2038: xtensa: Extend sysvipc data structures y2038: powerpc: Extend sysvipc data structures y2038: sparc: Extend sysvipc data structures y2038: parisc: Extend sysvipc data structures y2038: mips: Extend sysvipc data structures y2038: arm64: Extend sysvipc compat data structures y2038: s390: Remove unneeded ipc uapi header files y2038: ia64: Remove unneeded ipc uapi header files y2038: alpha: Remove unneeded ipc uapi header files ...
2018-06-04Merge branch 'timers-core-for-linus' of ↵Linus Torvalds1-11/+0
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timers and timekeeping updates from Thomas Gleixner: - Core infrastucture work for Y2038 to address the COMPAT interfaces: + Add a new Y2038 safe __kernel_timespec and use it in the core code + Introduce config switches which allow to control the various compat mechanisms + Use the new config switch in the posix timer code to control the 32bit compat syscall implementation. - Prevent bogus selection of CPU local clocksources which causes an endless reselection loop - Remove the extra kthread in the clocksource code which has no value and just adds another level of indirection - The usual bunch of trivial updates, cleanups and fixlets all over the place - More SPDX conversions * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (24 commits) clocksource/drivers/mxs_timer: Switch to SPDX identifier clocksource/drivers/timer-imx-tpm: Switch to SPDX identifier clocksource/drivers/timer-imx-gpt: Switch to SPDX identifier clocksource/drivers/timer-imx-gpt: Remove outdated file path clocksource/drivers/arc_timer: Add comments about locking while read GFRC clocksource/drivers/mips-gic-timer: Add pr_fmt and reword pr_* messages clocksource/drivers/sprd: Fix Kconfig dependency clocksource: Move inline keyword to the beginning of function declarations timer_list: Remove unused function pointer typedef timers: Adjust a kernel-doc comment tick: Prefer a lower rating device only if it's CPU local device clocksource: Remove kthread time: Change nanosleep to safe __kernel_* types time: Change types to new y2038 safe __kernel_* types time: Fix get_timespec64() for y2038 safe compat interfaces time: Add new y2038 safe __kernel_timespec posix-timers: Make compat syscalls depend on CONFIG_COMPAT_32BIT_TIME time: Introduce CONFIG_COMPAT_32BIT_TIME time: Introduce CONFIG_64BIT_TIME in architectures compat: Enable compat_get/put_timespec64 always ...
2018-05-19Merge branch 'linus' into timers/2038Thomas Gleixner2-3/+12
Merge upstream to pick up changes on which pending patches depend on.
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