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2013-04-11MIPS: Get rid of the use of .macro in C code.Ralf Baechle2-205/+319
It fails with LTO and probably has always been a fragile. Signed-off-by: Ralf Baechle <[email protected]>
2013-04-11MIPS: Make declarations and definitions of tlbmiss_handler_setup_pgd match.Ralf Baechle1-4/+9
tlbmiss_handler_setup_pgd is run-time generated code and it was convenient to pretend the symbol was an array in the generator but a function for the users. LTO gcc won't tolerate this kind of lie anymore so solve the problem through a cast and function pointer instead. Signed-off-by: Ralf Baechle <[email protected]>
2013-04-11MIPS: Use inline function to access current thread pointer.Ralf Baechle1-2/+6
With LTE this fixes this issue: LDFINAL vmlinux.o arch/mips/built-in.o (symbol from plugin): In function `sgimc_init': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here kernel/built-in.o (symbol from plugin): In function `get_task_mm': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here mm/built-in.o (symbol from plugin): In function `iov_iter_single_seg_count': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here fs/built-in.o (symbol from plugin): In function `finish_no_open': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here ipc/built-in.o (symbol from plugin): In function `ipc_init_ids': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here security/built-in.o (symbol from plugin): In function `key_schedule_gc': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here crypto/built-in.o (symbol from plugin): In function `crypto_find_alg': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here block/built-in.o (symbol from plugin): In function `elv_rb_find': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here argv_split.o (symbol from plugin): In function `argv_free': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here dec_and_lock.o (symbol from plugin): In function `_atomic_dec_and_lock': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here extable.o (symbol from plugin): In function `sort_extable': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here flex_proportions.o (symbol from plugin): In function `fprop_global_init': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here idr.o (symbol from plugin): In function `idr_for_each': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here is_single_threaded.o (symbol from plugin): In function `current_is_single_threaded': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here kobject.o (symbol from plugin): In function `kobject_get': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here kobject_uevent.o (symbol from plugin): In function `add_uevent_var': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here plist.o (symbol from plugin): In function `plist_add': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here radix-tree.o (symbol from plugin): In function `radix_tree_lookup_slot': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here ratelimit.o (symbol from plugin): In function `___ratelimit': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here rwsem-spinlock.o (symbol from plugin): In function `__init_rwsem': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here show_mem.o (symbol from plugin): In function `show_mem': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here timerqueue.o (symbol from plugin): In function `timerqueue_iterate_next': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here vsprintf.o (symbol from plugin): In function `simple_strtoull': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here delay.o (symbol from plugin): In function `__delay': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here mips-atomic.o (symbol from plugin): In function `arch_local_irq_disable': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here uncached.o (symbol from plugin): In function `run_uncached': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here lib/built-in.o (symbol from plugin): In function `_bcd2bin': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here arch/mips/lib/built-in.o (symbol from plugin): In function `ioread8': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here drivers/built-in.o (symbol from plugin): In function `fb_notifier_call_chain': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here net/built-in.o (symbol from plugin): In function `sock_from_file': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here klist.o (symbol from plugin): In function `klist_init': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here It also makes the code a little more readable, so let's merge it. Signed-off-by: Ralf Baechle <[email protected]>
2013-04-08MIPS: Add linux/mm_types.h to pgtable.hCorey Minyard1-0/+1
With the addition of transparent huge pages, pgtable.h uses struct page. However, it is possible to include pgtable.h without anything defining struct page. So add the include to get it. Signed-off-by: Corey Minyard <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2013-04-08spi/bcm63xx: remove unused speed_hz variableJonas Gorski1-1/+0
speed_hz is a write only member, so we can safely remove it and its generation. Also fixes the missing clk_put after getting the periph clock. Signed-off-by: Jonas Gorski <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2013-03-19Fix breakage in MIPS siginfo handlingDavid Howells1-1/+1
MIPS's siginfo handling has been broken since this commit: commit 574c4866e33d648520a8bd5bf6f573ea6e554e88 Author: Al Viro <[email protected]> Date: Sun Nov 25 22:24:19 2012 -0500 consolidate kernel-side struct sigaction declarations for 64-bit BE MIPS CPUs. The UAPI variant looks like this: struct sigaction { unsigned int sa_flags; __sighandler_t sa_handler; sigset_t sa_mask; }; but the core kernel's variant looks like this: struct sigaction { #ifndef __ARCH_HAS_ODD_SIGACTION __sighandler_t sa_handler; unsigned long sa_flags; #else unsigned long sa_flags; __sighandler_t sa_handler; #endif #ifdef __ARCH_HAS_SA_RESTORER __sigrestore_t sa_restorer; #endif sigset_t sa_mask; }; The problem is that sa_flags has been changed from an unsigned int to an unsigned long. Fix this by making sa_flags unsigned int if __ARCH_HAS_ODD_SIGACTION is defined. Whilst we're at it, rename __ARCH_HAS_ODD_SIGACTION to __ARCH_HAS_IRIX_SIGACTION. Signed-off-by: David Howells <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Acked-by: Al Viro <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2013-03-19MIPS: BCM63XX: Make nvram checksum failure non fatalJonas Gorski1-3/+1
Some vendors modify the nvram layout moving the checksum to a different place or dropping entirely, so reduce the checksum failure to a warning. Reported-by: Álvaro Fernández Rojas <[email protected]> Signed-off-by: Jonas Gorski <[email protected]> Cc: [email protected] Cc: John Crispin <[email protected]> Cc: Maxime Bizon <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: Kevin Cernekee <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2013-03-19MIPS: Fix code generation for non-DSP capable CPUsFlorian Fainelli1-19/+190
Commit 32a7ede (MIPS: dsp: Add assembler support for DSP ASEs) has enabled the use of DSP ASE specific instructions such as rddsp and wrdsp under the idea that all code path that will make use of these two instructions are properly checking for cpu_has_dsp to ensure that the particular CPU we are running on *actually* supports DSP ASE. This commit actually causes the following oops on QEMU Malta emulating a MIPS 24Kc without the DSP ASE implemented: [ 7.960000] Reserved instruction in kernel [ 7.960000] Cpu 0 [ 7.960000] $ 0 : 00000000 00000000 00000014 00000005 [ 7.960000] $ 4 : 8fc2de48 00000001 00000000 8f59ddb0 [ 7.960000] $ 8 : 8f5ceec4 00000018 00000c00 00800000 [ 7.960000] $12 : 00000100 00000200 00000000 00457b84 [ 7.960000] $16 : 00000000 8fc2ba78 8f4ec980 00000001 [ 7.960000] $20 : 80418f90 00000000 00000000 000002dd [ 7.960000] $24 : 0000009c 7730d7b8 [ 7.960000] $28 : 8f59c000 8f59dd38 00000001 80104248 [ 7.960000] Hi : 0000001d [ 7.960000] Lo : 0000000b [ 7.960000] epc : 801041ec thread_saved_pc+0x2c/0x38 [ 7.960000] Not tainted [ 7.960000] ra : 80104248 get_wchan+0x48/0xac [ 7.960000] Status: 1000b703 KERNEL EXL IE [ 7.960000] Cause : 10800028 [ 7.960000] PrId : 00019300 (MIPS 24Kc) [ 7.960000] Modules linked in: [ 7.960000] Process killall (pid: 1574, threadinfo=8f59c000, task=8fd14558, tls=773aa440) [ 7.960000] Stack : 8fc2ba78 8012b008 0000000c 0000001d 00000000 00000000 8f58a380 8f58a380 8fc2ba78 80202668 8f59de78 8f468600 8f59de28 801b2a3c 8f59df00 8f98ba20 74696e69 8f468600 8f59de28 801b7308 0081c007 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8fc2bbb4 00000001 0000001d 0000000b 77f038cc 7fe80648 ffffffff ffffffff 00000000 00000001 0016e000 00000000 ... [ 7.960000] Call Trace: [ 7.960000] [<801041ec>] thread_saved_pc+0x2c/0x38 [ 7.960000] [<80104248>] get_wchan+0x48/0xac The disassembly of thread_saved_pc points to the following: 000006d0 <thread_saved_pc>: 6d0: 8c820208 lw v0,520(a0) 6d4: 3c030000 lui v1,0x0 6d8: 24630000 addiu v1,v1,0 6dc: 10430008 beq v0,v1,700 <thread_saved_pc+0x30> 6e0: 00000000 nop 6e4: 3c020000 lui v0,0x0 6e8: 8c43000c lw v1,12(v0) 6ec: 04620004 bltzl v1,700 <thread_saved_pc+0x30> 6f0: 00001021 move v0,zero 6f4: 8c840200 lw a0,512(a0) 6f8: 00031080 sll v0,v1,0x2 6fc: 7c44100a lwx v0,a0(v0) <------------ 700: 03e00008 jr ra 704: 00000000 nop If we specifically disable -mdsp/-mdspr2 for arch/mips/kernel/process.o, we get the following (non-crashing) assembly: 00000708 <thread_saved_pc>: 708: 8c820208 lw v0,520(a0) 70c: 3c030000 lui v1,0x0 710: 24630000 addiu v1,v1,0 714: 10430009 beq v0,v1,73c <thread_saved_pc+0x34> 718: 00000000 nop 71c: 3c020000 lui v0,0x0 720: 8c42000c lw v0,12(v0) 724: 04420005 bltzl v0,73c <thread_saved_pc+0x34> 728: 00001021 move v0,zero 72c: 8c830200 lw v1,512(a0) 730: 00021080 sll v0,v0,0x2 734: 00431021 addu v0,v0,v1 738: 8c420000 lw v0,0(v0) 73c: 03e00008 jr ra 740: 00000000 nop The specific line that leads a different assembly being produced is: unsigned long thread_saved_pc(struct task_struct *tsk) ... return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset]; <--- The problem here is that the compiler was given the right to use DSP instructions with the -mdsp / -mdspr2 command-line switches and performed some optimization for us and used DSP ASE instructions where we are not checking that the running CPU actually supports DSP ASE. This patch fixes the issue by partially reverting commit 32a7ede for arch/mips/kernel/Makefile in order to remove the -mdsp / -mdspr2 compiler command-line switches such that we are now guaranteed that the compiler will not optimize using DSP ASE reserved instructions. We also need to fixup the rddsp/wrdsp and m{t,h}{hi,lo}{0,1,2,3} macros in arch/mips/include/asm/mipsregs.h to tell the assembler that we are going to explicitely use DSP ASE reserved instructions. The comment in arch/mips/kernel/Makefile is also updated to reflect that. Signed-off-by: Florian Fainelli <[email protected]> Acked-by: Steven J. Hill <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Ralf Baechle <[email protected]>
2013-03-12MIPS: SEAD3: Enable LL/SC.Ralf Baechle1-1/+1
All synthesizable CPU cores that could be loaded into a SEAD3's FPGA are MIPS32 or MIPS64 CPUs that have ll/sc. Signed-off-by: Ralf Baechle <[email protected]>
2013-03-12MIPS: Get rid of CONFIG_CPU_HAS_LLSC againPaul Bolle1-4/+0
Commit f7ade3c168e4f437c11f57be012992bbb0e3075c ("MIPS: Get rid of CONFIG_CPU_HAS_LLSC") did what it promised to do. But since then that macro and its Kconfig symbol popped up again. Get rid of those again. Signed-off-by: Paul Bolle <[email protected]> Cc: Jonas Gorski <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/4978/ Signed-off-by: Ralf Baechle <[email protected]>
2013-03-03consolidate cond_syscall and SYSCALL_ALIAS declarationsAl Viro2-8/+3
take them to asm/linkage.h, with default in linux/linkage.h Signed-off-by: Al Viro <[email protected]>
2013-03-02Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds332-9834/+8992
Pull MIPS updates from Ralf Baechle: o Add basic support for the Mediatek/Ralink Wireless SoC family. o The Qualcomm Atheros platform is extended by support for the new QCA955X SoC series as well as a bunch of patches that get the code ready for OF support. o Lantiq and BCM47XX platform have a few improvements and bug fixes. o MIPS has sent a few patches that get the kernel ready for the upcoming microMIPS support. o The rest of the series is made up of small bug fixes and cleanups that relate to various parts of the MIPS code. The biggy in there is a whitespace cleanup. After I was sent another set of whitespace cleanup patches I decided it was the time to clean the whitespace "issues" for once and and that touches many files below arch/mips/. Fix up silly conflicts, mostly due to whitespace cleanups. * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (105 commits) MIPS: Quit exporting kernel internel break codes to uapi/asm/break.h MIPS: remove broken conditional inside vpe loader code MIPS: SMTC: fix implicit declaration of set_vi_handler MIPS: early_printk: drop __init annotations MIPS: Probe for and report hardware virtualization support. MIPS: ath79: add support for the Qualcomm Atheros AP136-010 board MIPS: ath79: add USB controller registration code for the QCA955X SoCs MIPS: ath79: add PCI controller registration code for the QCA955X SoCs MIPS: ath79: add WMAC registration code for the QCA955X SoCs MIPS: ath79: register UART for the QCA955X SoCs MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set, clear} MIPS: ath79: add GPIO setup code for the QCA955X SoCs MIPS: ath79: add IRQ handling code for the QCA955X SoCs MIPS: ath79: add clock setup code for the QCA955X SoCs MIPS: ath79: add SoC detection code for the QCA955X SoCs MIPS: ath79: add early printk support for the QCA955X SoCs MIPS: ath79: fix WMAC IRQ resource assignment mips: reserve elfcorehdr mips: Make sure kernel memory is in iomem MIPS: ath79: use dynamically allocated USB platform devices ...
2013-02-23Merge branch 'for-linus' of ↵Linus Torvalds4-13/+24
git://git.kernel.org/pub/scm/linux/kernel/git/viro/signal Pull signal handling cleanups from Al Viro: "This is the first pile; another one will come a bit later and will contain SYSCALL_DEFINE-related patches. - a bunch of signal-related syscalls (both native and compat) unified. - a bunch of compat syscalls switched to COMPAT_SYSCALL_DEFINE (fixing several potential problems with missing argument validation, while we are at it) - a lot of now-pointless wrappers killed - a couple of architectures (cris and hexagon) forgot to save altstack settings into sigframe, even though they used the (uninitialized) values in sigreturn; fixed. - microblaze fixes for delivery of multiple signals arriving at once - saner set of helpers for signal delivery introduced, several architectures switched to using those." * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/signal: (143 commits) x86: convert to ksignal sparc: convert to ksignal arm: switch to struct ksignal * passing alpha: pass k_sigaction and siginfo_t using ksignal pointer burying unused conditionals make do_sigaltstack() static arm64: switch to generic old sigaction() (compat-only) arm64: switch to generic compat rt_sigaction() arm64: switch compat to generic old sigsuspend arm64: switch to generic compat rt_sigqueueinfo() arm64: switch to generic compat rt_sigpending() arm64: switch to generic compat rt_sigprocmask() arm64: switch to generic sigaltstack sparc: switch to generic old sigsuspend sparc: COMPAT_SYSCALL_DEFINE does all sign-extension as well as SYSCALL_DEFINE sparc: kill sign-extending wrappers for native syscalls kill sparc32_open() sparc: switch to use of generic old sigaction sparc: switch sys_compat_rt_sigaction() to COMPAT_SYSCALL_DEFINE mips: switch to generic sys_fork() and sys_clone() ...
2013-02-21Merge branch 'for-linus' of ↵Linus Torvalds1-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial Pull trivial tree from Jiri Kosina: "Assorted tiny fixes queued in trivial tree" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (22 commits) DocBook: update EXPORT_SYMBOL entry to point at export.h Documentation: update top level 00-INDEX file with new additions ARM: at91/ide: remove unsused at91-ide Kconfig entry percpu_counter.h: comment code for better readability x86, efi: fix comment typo in head_32.S IB: cxgb3: delay freeing mem untill entirely done with it net: mvneta: remove unneeded version.h include time: x86: report_lost_ticks doesn't exist any more pcmcia: avoid static analysis complaint about use-after-free fs/jfs: Fix typo in comment : 'how may' -> 'how many' of: add missing documentation for of_platform_populate() btrfs: remove unnecessary cur_trans set before goto loop in join_transaction sound: soc: Fix typo in sound/codecs treewide: Fix typo in various drivers btrfs: fix comment typos Update ibmvscsi module name in Kconfig. powerpc: fix typo (utilties -> utilities) of: fix spelling mistake in comment h8300: Fix home page URL in h8300/README xtensa: Fix home page URL in Kconfig ...
2013-02-21Merge branch 'mips-next-3.9' of ↵Ralf Baechle22-271/+651
git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
2013-02-20MIPS: Quit exporting kernel internel break codes to uapi/asm/break.hDavid Daney1-0/+26
The internal codes are not part of the kernel's ABI. Signed-off-by: David Daney <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4932/ Signed-off-by: John Crispin <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2013-02-19MIPS: Probe for and report hardware virtualization support.David Daney3-1/+6
The presence of the MIPS Virtualization Application-Specific Extension is indicated by CP0_Config3[23]. Probe for this and report it in /proc/cpuinfo. Signed-off-by: David Daney <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4904/ Signed-off-by: John Crispin <[email protected]>
2013-02-19MIPS: ath79: add USB controller registration code for the QCA955X SoCsGabor Juhos1-0/+3
Register platfom devices for the built-in USB controllers of the SoCs. Cc: Rodriguez, Luis <[email protected]> Cc: Giori, Kathy <[email protected]> Cc: QCA Linux Team <[email protected]> Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4952/ Signed-off-by: John Crispin <[email protected]>
2013-02-19MIPS: ath79: add PCI controller registration code for the QCA955X SoCsGabor Juhos1-0/+13
Add SoC specific PCI IRQ map, and register platform devices for the two built-in PCIe RCs. Cc: Rodriguez, Luis <[email protected]> Cc: Giori, Kathy <[email protected]> Cc: QCA Linux Team <[email protected]> Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4951/ Signed-off-by: John Crispin <[email protected]>
2013-02-19MIPS: ath79: add WMAC registration code for the QCA955X SoCsGabor Juhos1-0/+3
The SoC has a built-in wireless MAC. Register a platform device for that to make it usable with the ath9k driver. Cc: Rodriguez, Luis <[email protected]> Cc: Giori, Kathy <[email protected]> Cc: QCA Linux Team <[email protected]> Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4956/ Signed-off-by: John Crispin <[email protected]>
2013-02-19MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set, clear}Gabor Juhos1-0/+1
The ath79_device_reset_* are causing BUG when those are used on the QCA955x SoCs. The patch adds the required code to avoid that. Cc: Rodriguez, Luis <[email protected]> Cc: Giori, Kathy <[email protected]> Cc: QCA Linux Team <[email protected]> Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4948/ Signed-off-by: John Crispin <[email protected]>
2013-02-19MIPS: ath79: add GPIO setup code for the QCA955X SoCsGabor Juhos1-0/+1
The existing code can handle the GPIO controller of the QCA955x SoCs. Add a minimal glue code to make it working. Cc: Rodriguez, Luis <[email protected]> Cc: Giori, Kathy <[email protected]> Cc: QCA Linux Team <[email protected]> Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4947/ Signed-off-by: John Crispin <[email protected]>
2013-02-19MIPS: ath79: add IRQ handling code for the QCA955X SoCsGabor Juhos2-1/+37
The IRQ routing in the QCA955x SoCs is slightly different from the routing implemented in the already supported SoCs. Cc: Rodriguez, Luis <[email protected]> Cc: Giori, Kathy <[email protected]> Cc: QCA Linux Team <[email protected]> Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4955/ Signed-off-by: John Crispin <[email protected]>
2013-02-19MIPS: ath79: add clock setup code for the QCA955X SoCsGabor Juhos1-0/+39
The patch adds code to get various clock frequencies from the PLLs used in the QCA955x SoCs. Cc: Rodriguez, Luis <[email protected]> Cc: Giori, Kathy <[email protected]> Cc: QCA Linux Team <[email protected]> Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4945/ Signed-off-by: John Crispin <[email protected]>
2013-02-19MIPS: ath79: add SoC detection code for the QCA955X SoCsGabor Juhos2-0/+19
Also add 'soc_is_qca955[68x]' helper functions and a Kconfig symbol for the SoC family. Cc: Rodriguez, Luis <[email protected]> Cc: Giori, Kathy <[email protected]> Cc: QCA Linux Team <[email protected]> Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4943/ Signed-off-by: John Crispin <[email protected]>
2013-02-19MIPS: ath79: add early printk support for the QCA955X SoCsGabor Juhos1-0/+2
The patch allows to see kernel messages on the QCA955X SoCs in early boot stage. Cc: Rodriguez, Luis <[email protected]> Cc: Giori, Kathy <[email protected]> Cc: QCA Linux Team <[email protected]> Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4944/ Signed-off-by: John Crispin <[email protected]>
2013-02-17ath79: remove ATH79_MISC_IRQ_* definesGabor Juhos1-13/+0
Use the ATH79_MISC_IRQ() macro instead. Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4930/ Signed-off-by: John Crispin <[email protected]>
2013-02-17ath79: add ATH79_CPU_IRQ() macroGabor Juhos1-7/+2
Remove the individual ATH79_CPU_IRQ_* constants and use the new macro instead of those. Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4929/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: pci-ar724x: setup command register of the PCI controllerGabor Juhos1-0/+2
The command register of the PCI controller is not initialized correctly by the bootloader on some boards and this leads to non working PCI bus. Add code to initialize the command register from the Linux code to avoid this. Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4916/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: add dummy pci_load_of_rangesGabor Juhos1-0/+5
The pci_load_of_ranges function is only available if CONFIG_OF is selected. If the function is used without CONFIG_OF being enabled it will cause a build error. Add a dummy inline function to avoid this. Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4911/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: ath79: remove unused ar7{1x,24}x_pcibios_init functionsGabor Juhos1-28/+0
The functions are unused now, so remove them. Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4909/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: ath79: move global PCI defines into a common headerGabor Juhos1-0/+24
The constants will be used by a subsequent patch. Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4907/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: add irqdomain support for the CPU IRQ controllerGabor Juhos1-0/+6
Add code to load a irq_domain for the MIPS IRQ controller from a devicetree file. Signed-off-by: Gabor Juhos <[email protected]> Signed-off-by: John Crispin <[email protected]> Acked-by: David Daney <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4902/
2013-02-17MIPS: ralink: adds support for RT305x SoC familyJohn Crispin1-0/+139
Add support code for rt3050, rt3052, rt3350, rt3352 and rt5350 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <[email protected]> Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4896/
2013-02-17MIPS: ralink: adds include filesJohn Crispin2-0/+64
Before we start adding the platform code we add the common include files. Signed-off-by: John Crispin <[email protected]> Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4893/
2013-02-17MIPS: ath79: simplify MISC IRQ handlingGabor Juhos1-0/+1
The current code uses multiple if statements for demultiplexing the different interrupt sources. Additionally, the MISC interrupt controller has 32 interrupt sources and the current code does not handles all of them. Get rid of the if statements and process all interrupt sources in a loop to fix these issues. Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4874/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: ath79: fix GPIO function selection for AR934x SoCsGabor Juhos1-0/+2
GPIO function selection is not working on the AR934x SoCs because the offset of the function selection register is different on those. Add a helper routine which returns the correct register address based on the SoC type, and use that in the 'ath79_gpio_function_*' routines. Signed-off-by: Gabor Juhos <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4870/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: Add new GIC clocksource.Steven J. Hill2-1/+2
Add new clocksource that uses the counter present on the MIPS Global Interrupt Controller. Signed-off-by: Steven J. Hill <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4681/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: dsp: Simplify the DSP macros.Steven J. Hill1-201/+30
Simplify the DSP macros for vanilla (non-microMIPS) kernels and toolchains that do not support the DSP ASEs. Signed-off-by: Steven J. Hill <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4687/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: dsp: Support toolchains without DSP ASE and microMIPS.Steven J. Hill1-0/+89
Add macros to support the DSP ASE with microMIPS kernels when the toolchain does not have support. Signed-off-by: Steven J. Hill <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4686/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: dsp: Add assembler support for DSP ASEs.Steven J. Hill1-17/+36
Newer toolchains support the DSP and DSP Rev2 instructions. This patch performs a check for that support and adds compiler and assembler flags for only the files that need use those instructions. Signed-off-by: Steven J. Hill <[email protected]> Acked-by: Florian Fainelli <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4752/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: Add support for the M14KEc core.Steven J. Hill3-0/+7
Signed-off-by: Steven J. Hill <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4682/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: Clean-ups for MIPS Technologies Inc. generic header file.Steven J. Hill1-21/+7
Clean up standard header text and remove unused #define. Signed-off-by: Steven J. Hill <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4703/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: Netlogic: No hazards needed for XLR/XLSJayachandran C1-1/+1
TLB and COP0 hazards are handled in hardware for Netlogic XLR/XLS SoCs. Update hazards.h to pick more optimal set of definitions when compiling for XLR/XLS. Signed-off-by: Jayachandran C <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4788/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: Netlogic: Use PIC timer as a clocksourceJayachandran C2-5/+55
The XLR/XLS/XLP PIC has a 8 countdown timers which run at the PIC frequencey. One of these can be used as a clocksource to provide timestamps that is common across cores. This can be used in place of the count/compare clocksource which is per-CPU. On XLR/XLS PIC registers are 32-bit, so we just use the lower 32-bits of the PIC counter. On XLP, the whole 64-bit can be used. Provide common macros and functions for PIC timer registers on XLR/XLS and XLP, and use them to register a PIC clocksource. Signed-off-by: Jayachandran C <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4786/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: Netlogic: Split XLP L1 i-cache among threadsJayachandran C1-0/+2
Since we now use r4k cache code for Netlogic XLP, it is better to split L1 icache among the active threads, so that threads won't step on each other while flushing icache. The L1 dcache is already split among the threads in the core. Signed-off-by: Jayachandran C <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4787/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: Netlogic: Optimize EIMR/EIRR accesses in 32-bitJayachandran C1-0/+79
Provide functions ack_c0_eirr(), set_c0_eimr(), clear_c0_eimr() and read_c0_eirr_and_eimr() that do the EIMR and EIRR operations and update the interrupt handling code to use these functions. Also, use the EIMR register functions to mask interrupts in the irq code. The 64-bit interrupt request and mask registers (EIRR and EIMR) are accessed when the interrupts are off, and the common operations are to set or clear a bit in these registers. Using the 64-bit c0 access functions for these operations is not optimal in 32-bit, because it will disable/restore interrupts and split/join the 64-bit value during each register access. Signed-off-by: Jayachandran C <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4790/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: lantiq: rework external irq codeJohn Crispin1-0/+1
This code makes the irqs used by the EIU loadable from the DT. Additionally we add a helper that allows the pinctrl layer to map external irqs to real irq numbers. Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4818/
2013-02-17MIPS: lantiq: adds static clock for PP32John Crispin1-0/+1
The Lantiq DSL SoCs have an internal networking processor. Add code to read the static clock rate. Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4815/
2013-02-15MIPS: Add printing of ISA version in cpuinfo.Steven J. Hill1-0/+13
Display the MIPS ISA version release in the /proc/cpuinfo file. [[email protected]: Add support for MIPS I ... IV legacy architecture revisions. Also differenciate between MIPS32 and MIPS64 versions instead of lumping them together as just r1 and r2. Note to application programmers: this indicates the CPU's ISA level It does not imply the current execution environment does support it. For example an O32 application seeing "mips64r2" would still be restricted by by the execution environment to 32-bit - but the kernel could run mips64r2 code. The same for a 32-bit kernel running on a 64-bit processor. This field doesn't include ASEs or optional architecture modules nor other detailed flags such as the availability of an FPU.] Signed-off-by: Steven J. Hill <[email protected]> Cc: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/4714/ Signed-off-by: Ralf Baechle <[email protected]>
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