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2018-07-30MIPS: Make (UN)CAC_ADDR() PHYS_OFFSET-agnosticPaul Burton3-6/+2
Converting an address between cached & uncached (typically addresses in (c)kseg0 & (c)kseg1 or 2 xkphys regions) should not depend upon PHYS_OFFSET in any way - we're converting from a virtual address in one unmapped region to a virtual address in another unmapped region. For some reason our CAC_ADDR() & UNCAC_ADDR() macros make use of PAGE_OFFSET, which typically includes PHYS_OFFSET. This means that platforms with a non-zero PHYS_OFFSET typically have to workaround miscalculation by these 2 macros by also defining UNCAC_BASE to a value that isn't really correct. It appears that an attempt has previously been made to address this with commit 3f4579252aa1 ("MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET") which was later undone by commit ed3ce16c3d2b ("Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET"") which also introduced the ar7 workaround. That attempt at a fix was roughly equivalent, but essentially caused the CAC_ADDR() & UNCAC_ADDR() macros to cancel out PHYS_OFFSET by adding & then subtracting it again. In his revert Leonid is correct that using PHYS_OFFSET makes no sense in the context of these macros, but appears to have missed its inclusion via PAGE_OFFSET which means PHYS_OFFSET actually had an effect after the revert rather than before it. Here we fix this by modifying CAC_ADDR() & UNCAC_ADDR() to stop using PAGE_OFFSET (& thus PHYS_OFFSET), instead using __pa() & __va() along with UNCAC_BASE. For UNCAC_ADDR(), __pa() will convert a cached address to a physical address which we can simply use as an offset from UNCAC_BASE to obtain an address in the uncached region. For CAC_ADDR() we can undo the effect of UNCAC_ADDR() by subtracting UNCAC_BASE and using __va() on the result. With this change made, remove definitions of UNCAC_BASE from the ar7 & pic32 platforms which appear to have defined them only to workaround this problem. Signed-off-by: Paul Burton <[email protected]> References: 3f4579252aa1 ("MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET") References: ed3ce16c3d2b ("Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET"") Patchwork: https://patchwork.linux-mips.org/patch/20046/ Cc: Florian Fainelli <[email protected]> Cc: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: Vladimir Kondratiev <[email protected]>
2018-07-27MIPS: VDSO: Prevent use of smp_processor_id()Paul Burton1-1/+11
VDSO code should not be using smp_processor_id(), since it is executed in user mode. Introduce a VDSO-specific path which will cause a compile-time or link-time error (depending upon support for __compiletime_error) if the VDSO ever incorrectly attempts to use smp_processor_id(). [Matt Redfearn <[email protected]>: Move before change to smp_processor_id in series] Signed-off-by: Paul Burton <[email protected]> Signed-off-by: Matt Redfearn <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/17932/ Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected]
2018-07-27MIPS: remove mips_swiotlb_opsChristoph Hellwig1-2/+3
mips_swiotlb_ops differs from the generic swiotlb_dma_ops only in that it contains a mb() barrier after each operations that maps or syncs dma memory to the device. The dma operations are defined to not be memory barriers, but instead the write* operations to kick the DMA off are supposed to contain them. For mips this handled by war_io_reorder_wmb(), which evaluates to the stronger wmb() instead of the pure compiler barrier barrier() for just those platforms that use swiotlb, so I think we are covered properly. [[email protected]: - Include linux/swiotlb.h to fix build failures for configs with CONFIG_SWIOTLB=y.] Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/20038/ Cc: David Daney <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected]
2018-07-27Revert "MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratum"Rafał Miłecki1-3/+0
This reverts commit 2a027b47dba6 ("MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratum"). Enabling ExternalSync caused a regression for BCM4718A1 (used e.g. in Netgear E3000 and ASUS RT-N16): it simply hangs during PCIe initialization. It's likely that BCM4717A1 is also affected. I didn't notice that earlier as the only BCM47XX devices with PCIe I own are: 1) BCM4706 with 2 x 14e4:4331 2) BCM4706 with 14e4:4360 and 14e4:4331 it appears that BCM4706 is unaffected. While BCM5300X-ES300-RDS.pdf seems to document that erratum and its workarounds (according to quotes provided by Tokunori) it seems not even Broadcom follows them. According to the provided info Broadcom should define CONF7_ES in their SDK's mipsinc.h and implement workaround in the si_mips_init(). Checking both didn't reveal such code. It *could* mean Broadcom also had some problems with the given workaround. Signed-off-by: Rafał Miłecki <[email protected]> Signed-off-by: Paul Burton <[email protected]> Reported-by: Michael Marley <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/20032/ URL: https://bugs.openwrt.org/index.php?do=details&task_id=1688 Cc: Tokunori Ikegami <[email protected]> Cc: Hauke Mehrtens <[email protected]> Cc: Chris Packham <[email protected]> Cc: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected]
2018-07-26MIPS: TXx9: remove useless RTC definitionsAlexandre Belloni1-29/+0
The RTC definitions were moved to the driver, remove them from the platform header. [[email protected]: - Also remove the unused tx4939_rtcptr which would use struct tx4939_rtc_reg if it were ever expanded.] Signed-off-by: Alexandre Belloni <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/20024/ Cc: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: [email protected]
2018-07-24MIPS: ath79: finetune cpu-overridesFelix Fietkau1-0/+6
This patch adds a few additional cpu feature overrides so that they do not need to be probed at runtime. Signed-off-by: Felix Fietkau <[email protected]> Signed-off-by: John Crispin <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19914/ Cc: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected]
2018-07-24MIPS: ath79: fix system restartFelix Fietkau1-0/+1
This patch disables irq on reboot to fix hang issues that were observed due to pending interrupts. Signed-off-by: Felix Fietkau <[email protected]> Signed-off-by: John Crispin <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19913/ Cc: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected]
2018-07-24MIPS: ath79: add support for QCA953x QCA956x TP9343Matthias Schiffer1-0/+33
This patch adds support for 2 new types of QCA silicon. TP9343 is essentially the same as the QCA956X but is licensed by TPLink. Signed-off-by: Weijie Gao <[email protected]> Signed-off-by: Matthias Schiffer <[email protected]> Signed-off-by: John Crispin <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19911/ Cc: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected]
2018-07-24MIPS: ath79: add lots of missing registersGabor Juhos1-1/+770
This patch adds many new registers for various QCA MIPS SoCs. The patch is an aggragate of many contributions made to OpenWrt. Signed-off-by: Gabor Juhos <[email protected]> Signed-off-by: Henryk Heisig <[email protected]> Signed-off-by: Matthias Schiffer <[email protected]> Signed-off-by: Weijie Gao <[email protected]> Signed-off-by: Felix Fietkau <[email protected]> Signed-off-by: Julien Dusser <[email protected]> Signed-off-by: John Crispin <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19910/ Cc: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected]
2018-07-24MIPS: Octeon: Remove extern declarations.Steven J. Hill7-11/+22
Get rid of extern declarations in .c functions and included the necessary header file. Also remove unused UART declares. Signed-off-by: Steven J. Hill <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19477/ Cc: [email protected]
2018-07-24MIPS: Hardcode cpu_has_* where known at compile time due to ISAPaul Burton1-69/+107
Many architectural features have over time moved from being optional to either be required or removed by newer architecture releases. This means that in many cases we can know at compile time whether a feature will be supported or not purely due to the knowledge we have about the ISA the kernel build is targeting. This patch introduces a bunch of utility macros for checking for supported options, ASEs & combinations of those with ISA revisions. It then makes use of these in the default definitions of cpu_has_* macros. The result is that many of the macros become compile-time constant, allowing more optimisation opportunities for the compiler - particularly with kernels built for later ISA revisions. To demonstrate the effect of this patch, the following table shows the size in bytes of the kernel binary as reported by scripts/bloat-o-meter for v4.12-rc4 maltasmvp_defconfig kernels with & without this patch. A variant of maltasmvp_defconfig with CONFIG_CPU_MIPS32_R6 selected is also shown, to demonstrate that MIPSr6 systems benefit more due to extra features becoming required by that architecture revision. Builds of pistachio_defconfig are also shown, as although this is a MIPSr2 platform it doesn't hardcode any features in a machine-specific cpu-feature-overrides.h, which allows it to gain more from this patch than the equivalent Malta r2 build. Config | Before | After | Change ----------------|---------|---------|--------- maltasmvp | 7248316 | 7247714 | -602 maltasmvp + r6 | 6955595 | 6950777 | -4818 pistachio | 8650977 | 8363898 | -287079 Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/16360/ Cc: Joshua Kinard <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected]
2018-07-24mips: use asm-generic version of msi.hThomas Petazzoni1-0/+1
This is necessary to be able to include <linux/msi.h> when CONFIG_GENERIC_MSI_IRQ_DOMAIN is enabled. Without this, a build with CONFIG_GENERIC_MSI_IRQ_DOMAIN fails with: In file included from include/linux/kvm_host.h:20:0, from arch/mips/kernel/asm-offsets.c:24: >> include/linux/msi.h:197:10: fatal error: asm/msi.h: No such file or directory #include <asm/msi.h> ^~~~~~~~~~~ compilation terminated. make[2]: *** [arch/mips/kernel/asm-offsets.s] Error 1 make[2]: Target '__build' not remade because of errors. make[1]: *** [prepare0] Error 2 make[1]: Target 'prepare' not remade because of errors. make: *** [sub-make] Error 2 Signed-off-by: Thomas Petazzoni <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19986/ Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected] Cc: Marc Zyngier <[email protected]> Cc: Hanna Hawa <[email protected]>
2018-07-23MIPS: Loongson64: Define and use some CP0 registersHuacai Chen2-12/+14
Defines CP0_CONFIG3, CP0_CONFIG6, CP0_PAGEGRAIN and use them in kernel-entry-init.h for Loongson64. Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19264/ Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: Fuxin Zhang <[email protected]> Cc: Zhangjin Wu <[email protected]> Cc: Huacai Chen <[email protected]>
2018-07-23MIPS: Loongson: Add Loongson-3A R3.1 basic supportHuacai Chen1-25/+26
Loongson-3A R3.1 is the bugfix revision of Loongson-3A R3. All Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3A R3 Loongson-3A3000 0x6309 Loongson-3A R3.1 Loongson-3A3000 0x630d Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19263/ Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: Fuxin Zhang <[email protected]> Cc: Zhangjin Wu <[email protected]> Cc: Huacai Chen <[email protected]>
2018-07-23MIPS: Change definition of cpu_relax() for Loongson-3Huacai Chen1-0/+13
Linux expects that if a CPU modifies a memory location, then that modification will eventually become visible to other CPUs in the system. Loongson 3 CPUs include a Store Fill Buffer (SFB) which sits between a core & its L1 data cache, queueing memory accesses & allowing for faster forwarding of data from pending stores to younger loads from the core. Unfortunately the SFB prioritizes loads such that a continuous stream of loads may cause a pending write to be buffered indefinitely. This is problematic if we end up with 2 CPUs which each perform a store that the other polls for - one or both CPUs may end up with their stores buffered in the SFB, never reaching cache due to the continuous reads from the poll loop. Such a deadlock condition has been observed whilst running qspinlock code. This patch changes the definition of cpu_relax() to smp_mb() for Loongson-3, forcing a flush of the SFB on SMP systems which will cause any pending writes to make it as far as the L1 caches where they will become visible to other CPUs. If the kernel is not compiled for SMP support, this will expand to a barrier() as before. This workaround matches that currently implemented for ARM when CONFIG_ARM_ERRATA_754327=y, which was introduced by commit 534be1d5a2da ("ARM: 6194/1: change definition of cpu_relax() for ARM11MPCore"). Although the workaround is only required when the Loongson 3 SFB functionality is enabled, and we only began explicitly enabling that functionality in v4.7 with commit 1e820da3c9af ("MIPS: Loongson-3: Introduce CONFIG_LOONGSON3_ENHANCEMENT"), existing or future firmware may enable the SFB which means we may need the workaround backported to earlier kernels too. [[email protected]: - Reword commit message & comment. - Limit stable backport to v3.15+ where we support Loongson 3 CPUs.] Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Paul Burton <[email protected]> References: 534be1d5a2da ("ARM: 6194/1: change definition of cpu_relax() for ARM11MPCore") References: 1e820da3c9af ("MIPS: Loongson-3: Introduce CONFIG_LOONGSON3_ENHANCEMENT") Patchwork: https://patchwork.linux-mips.org/patch/19830/ Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: Fuxin Zhang <[email protected]> Cc: Zhangjin Wu <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] # v3.15+
2018-07-20mips: mm: Discard ioremap_cacheable_cow() methodSerge Semin1-7/+0
This macro substitution is the shortcut to map cacheable IO memory with coherent and write-back attributes. Since it is entirely unused by kernel, lets just remove it. Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Paul Burton <[email protected]> Suggested-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19937/ CC: Paul Burton <[email protected]> Cc: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: Sinan Kaya <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected]
2018-07-19MIPS: Correct the 64-bit DSP accumulator register sizeMaciej W. Rozycki1-1/+1
Use the `unsigned long' rather than `__u32' type for DSP accumulator registers, like with the regular MIPS multiply/divide accumulator and general-purpose registers, as all are 64-bit in 64-bit implementations and using a 32-bit data type leads to contents truncation on context saving. Update `arch_ptrace' and `compat_arch_ptrace' accordingly, removing casts that are similarly not used with multiply/divide accumulator or general-purpose register accesses. Signed-off-by: Maciej W. Rozycki <[email protected]> Signed-off-by: Paul Burton <[email protected]> Fixes: e50c0a8fa60d ("Support the MIPS32 / MIPS64 DSP ASE.") Patchwork: https://patchwork.linux-mips.org/patch/19329/ Cc: Alexander Viro <[email protected]> Cc: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] # 2.6.15+
2018-07-18MIPS: jz4740: Move jz4740_nand.h header to include/linux/platform_data/jz4740Boris Brezillon1-34/+0
This way we will be able to compile the jz4740_nand driver when COMPILE_TEST=y. Signed-off-by: Boris Brezillon <[email protected]> Acked-by: Paul Burton <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2018-07-18MIPS: txx9: Move the ndfc.h header to include/linux/platform_data/txx9Boris Brezillon1-30/+0
This way we will be able to compile the ndfmc driver when COMPILE_TEST=y. Signed-off-by: Boris Brezillon <[email protected]> Acked-by: Paul Burton <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2018-07-17mips: unify prom_putchar() declarationsAlexander Sverdlin3-2/+2
prom_putchar() is used centrally in early printk infrastructure therefore at least MIPS should agree on the function return type. [[email protected]: - Include linux/types.h in asm/setup.h to gain the bool typedef before we start include asm/setup.h elsewhere. - Include asm/setup.h in all files that use or define prom_putchar(). - Also standardise on signed rather than unsigned char argument.] Signed-off-by: Alexander Sverdlin <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19842/ Cc: [email protected] Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: Jonas Gorski <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: Kate Stewart <[email protected]> Cc: Philippe Ombredanne <[email protected]>
2018-07-17Merge tag 'v4.18-rc5' into locking/core, to pick up fixesIngo Molnar2-0/+5
Signed-off-by: Ingo Molnar <[email protected]>
2018-07-12MIPS: Cleanup R10000_LLSC_WAR logic in atomic.hJoshua Kinard1-147/+32
This patch reduces down the conditionals in MIPS atomic code that deal with a silicon bug in early R10000 cpus that required a workaround of a branch-likely instruction following a store-conditional in order to to guarantee the whole ll/sc sequence is atomic. As the only real difference is a branch-likely instruction (beqzl) over a standard branch (beqz), the conditional is reduced down to a single preprocessor check at the top to pick the required instruction. This requires writing the uses in assembler, thus we discard the non-R10000 case that uses a mixture of a C do...while loop with embedded assembler that was added back in commit 7837314d141c ("MIPS: Get rid of branches to .subsections."). A note found in the git log for commit 5999eca25c1f ("[MIPS] Improve branch prediction in ll/sc atomic operations.") is also addressed. The macro definition for the branch instruction and the code comment derives from a patch sent in earlier by Paul Burton for various cmpxchg cleanups. [[email protected]: - Minor whitespace fix for checkpatch.] Signed-off-by: Joshua Kinard <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/17736/ Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: "Maciej W. Rozycki" <[email protected]> Cc: [email protected]
2018-07-12MIPS: Fix delay slot bug in `atomic*_sub_if_positive' for R10000_LLSC_WARJoshua Kinard1-20/+12
This patch fixes an old bug in MIPS ll/sc atomics, in the `atomic_sub_if_positive' and `atomic64_sub_if_positive' functions, for the R10000_LLSC_WAR case where the result of the subu/dsubu instruction would potentially not be made available to the sc/scd instruction due to being in the delay-slot of the branch-likely (beqzl) instruction. This also removes the need for the `noreorder' directive, allowing GAS to use delay slot scheduling as needed. The same fix is also applied to the standard branch (beqz) case in preparation for a follow-up patch that will cleanup/merge the R10000_LLSC_WAR and non-R10K sections together. Signed-off-by: Joshua Kinard <[email protected]> Signed-off-by: Paul Burton <[email protected]> Tested-by: Joshua Kinard <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/17735/ Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: "Maciej W. Rozycki" <[email protected]> Cc: [email protected]
2018-07-10mips: mm: Discard ioremap_uncached_accelerated() methodSerge Semin1-6/+2
Adaptive ioremap_wc() method is now available as of commit 9748e33e26c6 ("mips: mm: Create UCA-based ioremap_wc() method"). We can use it to obtain UnCached Accelerated (UCA) mappings safely on all MIPS systems, and so we don't need the MIPS-specific ioremap_uncached_accelerated() any longer. This macro hard-coded the UCA Cache Coherency Attribute (CCA) in a manner that isn't safe for kernels that may run on different CPUs, and it is also entirely unused so we can trivially remove it. [[email protected]: - Reword the commit message a little. - Remove CC stable.] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19790/ Cc: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2018-07-10mips: mm: Create UCA-based ioremap_wc() methodSerge Semin1-0/+23
Modern MIPS cores (like P5600/6600, M5150/6520, end so on) which got L2-cache on chip also can enable a special type Cache-Coherency attribute (CCA) named UnCached Accelerated attribute (UCA). In this way uncached accelerated accesses are treated the same way as non-accelerated uncached accesses, but uncached stores are gathered together for more efficient bus utilization. So to speak this CCA enables uncached transactions to better utilize bus bandwidth via burst transactions. This is exactly why ioremap_wc() method has been introduced in Linux. Alas MIPS-platform code hasn't implemented it so far, instead default one has been used which was an alias to ioremap_nocache. In order to fix this we added MIPS-specific ioremap_wc() macro substituted by generic __ioremap_mode() method call with writecombine CPU-info field passed. It shall create real ioremap_wc() method if CPU-cache supports UCA feature and fall-back to _CACHE_UNCACHED attribute if one doesn't. Additionally platform-specific io.h shall declare ARCH_HAS_IOREMAP_WC macro as indication of architectural definition of ioremap_wc() (similar to x86/powerpc). [[email protected]: - Remove CC stable, this is new functionality.] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19789/ Cc: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2018-07-03MIPS: Octeon: Simplify CIU register functions.Steven J. Hill1-94/+22
Collapse and simplify switch statements in functions. Signed-off-by: Steven J. Hill <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19713/ Cc: [email protected] Cc: Chandrakala Chavva <[email protected]>
2018-07-03MIPS: Octeon: Create simple macro for CIU registers.Steven J. Hill1-28/+32
Create new CVMX_CIU_ADDR macro to improve readability. Signed-off-by: Steven J. Hill <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19712/ Cc: [email protected] Cc: Chandrakala Chavva <[email protected]>
2018-07-03MIPS: Octeon: Remove all unused CIU macros.Steven J. Hill1-52/+18
Get rid of all unused CIU macros and sort them. Verified with 'make allyesconfig' build test. [[email protected]: - Also checked via convoluted grep invocation for use of all removed macros within arch/mips/ & drivers/.] Signed-off-by: Steven J. Hill <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19710/ Cc: [email protected] Cc: Chandrakala Chavva <[email protected]>
2018-07-03MIPS: Octeon: Convert CIU types to use bitfields.Steven J. Hill1-128/+56
Convert remaining structures to use __BITFIELD_FIELD macro. Also straighten up the description text and whitespace. Signed-off-by: Steven J. Hill <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19709/ Cc: [email protected] Cc: Chandrakala Chavva <[email protected]>
2018-07-03MIPS: Octeon: Unify QLM data types in CIU header.Steven J. Hill1-37/+2
Data types 'cvmx_ciu_qlm0' and 'cvmx_ciu_qlm1' are identical in their usage and structure. Combine them and update the PCIe code. Signed-off-by: Steven J. Hill <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19708/ Cc: [email protected] Cc: Chandrakala Chavva <[email protected]>
2018-07-03MIPS: Octeon: Remove unused CIU types.Steven J. Hill1-9629/+0
Remove all unused data types. Verified with a 'make allyesconfig' and Cavium platform. [[email protected]: - Also checked via convoluted grep invocation for use of all removed structs & unions within arch/mips/ & drivers/.] Signed-off-by: Steven J. Hill <[email protected]> Signed-off-by: Paul Burton <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19711/ Cc: [email protected] Cc: Chandrakala Chavva <[email protected]>
2018-06-26Merge branch 'linus' into perf/core, to pick up fixesIngo Molnar2-0/+5
Signed-off-by: Ingo Molnar <[email protected]>
2018-06-24MIPS: Schedule on CPUs we need to lose FPU for a mode switchPaul Burton1-2/+0
Commit 6b8322576e9d ("MIPS: Force CPUs to lose FP context during mode switches") ensures that we react to PR_SET_FP_MODE prctl syscalls quickly by broadcasting an IPI in order to cause CPUs to lose FPU access when necessary. Whilst it achieves that, unfortunately it causes all sorts of strange race conditions because: 1) The IPI may arrive at a point where the FPU is in the process of being enabled, but that process is not yet complete leading to a state we aren't prepared to handle. For example: [ 370.215903] do_cpu invoked from kernel context![#1]: [ 370.221064] CPU: 0 PID: 963 Comm: fp-prctl Not tainted 4.9.0-rc5-00323-g210db32-dirty #226 [ 370.229420] task: a8000000fd672e00 task.stack: a8000000fd630000 [ 370.235399] $ 0 : 0000000000000000 0000000000000001 0000000000000001 a8000000fd630000 [ 370.243882] $ 4 : a8000000fd672e00 0000000000000000 0000000000000453 0000000000000000 [ 370.252317] $ 8 : 0000000000000000 a8000000fd637c28 1000000000000000 0000000000000010 [ 370.260753] $12 : 00000000140084e0 ffffffff80109c00 0000000000000000 0000000000000002 [ 370.269179] $16 : ffffffff8092f080 a8000000fd672e00 ffffffff80107fe8 a8000000fd485000 [ 370.277612] $20 : ffffffff8084d328 ffffffff80940000 0000000000000009 ffffffff80930000 [ 370.286038] $24 : 0000000000000000 900000001612048c [ 370.294476] $28 : a8000000fd630000 a8000000fd637ac0 ffffffff80937300 ffffffff8010807c [ 370.302909] Hi : 0000000000000000 [ 370.306595] Lo : 0000000000000200 [ 370.310376] epc : ffffffff80115d38 _save_fp+0x10/0xa0 [ 370.315784] ra : ffffffff8010807c prepare_for_fp_mode_switch+0x94/0x1b0 [ 370.322707] Status: 140084e2 KX SX UX KERNEL EXL [ 370.327980] Cause : 1080002c (ExcCode 0b) [ 370.332091] PrId : 0001a428 (MIPS P6600) [ 370.336179] Modules linked in: [ 370.339486] Process fp-prctl (pid: 963, threadinfo=a8000000fd630000, task=a8000000fd672e00, tls=00000000756e67d0) [ 370.349724] Stack : 0000000000000000 a8000000fd557dc0 0000000000000000 ffffffff801ca8e0 [ 370.358161] 0000000000000000 a8000000fd637b9c 0000000000000009 ffffffff80923780 [ 370.366575] ffffffff80850000 ffffffff8011610c 00000000000000b8 ffffffff801a5084 [ 370.374989] ffffffff8084a370 ffffffff8084a388 ffffffff80923780 ffffffff80923828 [ 370.383395] 0000000000010000 ffffffff809237a8 0000000000020000 ffffffff80a40000 [ 370.391817] 000000000000007c 00000000004a0000 00000000756dedd0 ffffffff801a5188 [ 370.400230] a800000002014900 0000000000000001 ffffffff80923780 0000000080923828 [ 370.408644] ffffffff80923780 ffffffff80923780 ffffffff80923828 ffffffff801a521c [ 370.417066] ffffffff80923780 ffffffff80923828 0000000000010000 ffffffff801a8f84 [ 370.425472] ffffffff80a40000 a8000000fd637c20 ffffffff80a39240 0000000000000001 [ 370.433885] ... [ 370.436562] Call Trace: [ 370.439222] [<ffffffff80115d38>] _save_fp+0x10/0xa0 [ 370.444305] [<ffffffff8010807c>] prepare_for_fp_mode_switch+0x94/0x1b0 [ 370.451035] [<ffffffff801ca8e0>] flush_smp_call_function_queue+0xf8/0x230 [ 370.457991] [<ffffffff8011610c>] ipi_call_interrupt+0xc/0x20 [ 370.463814] [<ffffffff801a5084>] __handle_irq_event_percpu+0xc4/0x1a8 [ 370.470404] [<ffffffff801a5188>] handle_irq_event_percpu+0x20/0x68 [ 370.476734] [<ffffffff801a521c>] handle_irq_event+0x4c/0x88 [ 370.482486] [<ffffffff801a8f84>] handle_edge_irq+0x12c/0x210 [ 370.488316] [<ffffffff801a47a0>] generic_handle_irq+0x38/0x48 [ 370.494280] [<ffffffff804a2dbc>] gic_handle_shared_int+0x194/0x268 [ 370.500616] [<ffffffff801a47a0>] generic_handle_irq+0x38/0x48 [ 370.506529] [<ffffffff80107e60>] do_IRQ+0x18/0x28 [ 370.511445] [<ffffffff804a1524>] plat_irq_dispatch+0xc4/0x140 [ 370.517339] [<ffffffff80106230>] ret_from_irq+0x0/0x4 [ 370.522583] [<ffffffff8010fad4>] do_ri+0x4fc/0x7e8 [ 370.527546] [<ffffffff80106220>] ret_from_exception+0x0/0x10 2) The IPI may arrive during kernel use of the FPU, since we generally only disable preemption around use of the FPU & leave interrupts enabled. This can lead to us unexpectedly losing access to the FPU in places where it previously had not been possible. For example: do_cpu invoked from kernel context![#2]: CPU: 2 PID: 7338 Comm: fp-prctl Tainted: G D 4.7.0-00424-g49b0c82 #2 task: 838e4000 ti: 88d38000 task.ti: 88d38000 $ 0 : 00000000 00000001 ffffffff 88d3fef8 $ 4 : 838e4000 88d38004 00000000 00000001 $ 8 : 3400fc01 801f8020 808e9100 24000000 $12 : dbffffff 807b69d8 807b0000 00000000 $16 : 00000000 80786150 00400fc4 809c0398 $20 : 809c0338 0040273c 88d3ff28 808e9d30 $24 : 808e9d30 00400fb4 $28 : 88d38000 88d3fe88 00000000 8011a2ac Hi : 0040273c Lo : 88d3ff28 epc : 80114178 _restore_fp+0x10/0xa0 ra : 8011a2ac mipsr2_decoder+0xd5c/0x1660 Status: 1400fc03 KERNEL EXL IE Cause : 1080002c (ExcCode 0b) PrId : 0001a920 (MIPS I6400) Modules linked in: Process fp-prctl (pid: 7338, threadinfo=88d38000, task=838e4000, tls=766527d0) Stack : 00000000 00000000 00000000 88d3fe98 00000000 00000000 809c0398 809c0338 808e9100 00000000 88d3ff28 00400fc4 00400fc4 0040273c 7fb69e18 004a0000 004a0000 004a0000 7664add0 8010de18 00000000 00000000 88d3fef8 88d3ff28 808e9100 00000000 766527d0 8010e534 000c0000 85755000 8181d580 00000000 00000000 00000000 004a0000 00000000 766527d0 7fb69e18 004a0000 80105c20 ... Call Trace: [<80114178>] _restore_fp+0x10/0xa0 [<8011a2ac>] mipsr2_decoder+0xd5c/0x1660 [<8010de18>] do_ri+0x90/0x6b8 [<80105c20>] ret_from_exception+0x0/0x10 At first glance a simple fix may seem to be to disable interrupts around kernel use of the FPU rather than merely preemption, however this would introduce further overhead outside of the mode switch path & doesn't solve the third problem: 3) The IPI may arrive whilst the kernel is running code that will lead to a preempt_disable() call & FPU usage soon. If this happens then the IPI will be serviced & we'll proceed to enable an FPU whilst the mode switch is in progress, leading to strange & inconsistent behaviour. Further to all of this is a separate but related problem: 4) There are various paths through which we may enable the FPU without the user having triggered a coprocessor 1 disabled exception. These paths are those in which we emulate instructions & then enable the FPU with the expectation that the user might execute an FP instruction shortly afterwards. However these paths have not previously checked whether an FP mode switch is underway for the task, and therefore could enable the FPU whilst such a mode switch is in progress leading to strange & inconsistent behaviour for user code. This patch fixes all of the above by taking a step back & re-examining our approach to FP mode switches. Up until now we have taken these basic steps: a) Prevent any threads that are part of the affected process from being able to obtain ownership of the FPU. b) Cause any threads that are part of the affected process and already have ownership of an FPU to lose it. c) Set the thread flags for each thread that is part of the affected process to reflect the new FP mode. d) Allow threads to obtain ownership of the FPU again. This approach is however more complex than necessary. All that we really require is that the mode switch has occurred for all threads that are part of the affected process before mips_set_process_fp_mode(), and thus the PR_SET_FP_MODE prctl() syscall, returns. This doesn't require that we stop threads from owning or using an FPU whilst a mode switch occurs, only that we force them to relinquish it after the mode switch has occurred such that they next own an FPU with the correct mode configured. Our basic steps therefore simplify to: A) Set the thread flags for each thread that is part of the affected process to reflect the new FP mode. B) Cause any threads that are part of the affected process and already have ownership of an FPU to lose it. We implement B) by forcing each CPU which might be running a thread which is part of the affected process to schedule a no-op function, which causes the affected thread to lose its FPU ownership when it is descheduled. The end result is simpler FP mode switching with less overhead in the FPU enable path (ie. enable_restore_fp_context()) and fewer moving parts. Signed-off-by: Paul Burton <[email protected]> Fixes: 9791554b45a2 ("MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS") Fixes: 6b8322576e9d ("MIPS: Force CPUs to lose FP context during mode switches") Cc: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: stable <[email protected]> # v4.0+
2018-06-24MIPS: remove unneeded includes from dma-mapping.hChristoph Hellwig1-8/+0
Keep this file as light as possible as it gets pulled into every driver using dma mapping APIs. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19552/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: remove the old dma-default implementationChristoph Hellwig2-76/+0
Now unused. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19551/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: bmips: use generic dma noncoherent opsChristoph Hellwig2-70/+0
Provide phys_to_dma/dma_to_phys helpers, and the special arch_sync_dma_for_cpu_all hook, everything else is generic Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19550/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: jazz: split dma mapping operations from dma-defaultChristoph Hellwig2-61/+4
Jazz actually has a very basic IOMMU, so split the ops into a separate implementation from the generic default support (which is about to go away anyway). Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19548/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: ath25: use generic dma noncoherent opsChristoph Hellwig1-71/+0
Provide phys_to_dma/dma_to_phys helpers only if PCI support is enabled, everything else is generic. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19547/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: IP32: use generic dma noncoherent opsChristoph Hellwig1-92/+0
Provide phys_to_dma/dma_to_phys helpers, everything else is generic. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19546/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: loongson64: use generic dma noncoherent opsChristoph Hellwig1-69/+0
Provide phys_to_dma/dma_to_phys helpers, everything else is generic. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19545/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: use generic dma noncoherent ops for simple noncoherent platformsChristoph Hellwig1-0/+2
Convert everything not overriding dma-coherence.h to the generic noncoherent ops. The new dma-noncoherent.c file duplicates a lot of the code in dma-default.c, but that file will be gone by the end of this series. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19544/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: IP27: use dma_direct_opsChristoph Hellwig1-70/+0
IP27 is coherent and has a reasonably direct mapping, just with a little per-bus offset added into the dma address. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19542/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: use dma_direct_ops for coherent I/OChristoph Hellwig1-1/+1
Switch the simple cache coherent architectures that don't require any DMA address translation to dma_direct_ops. We'll soon use at least parts of the direct DMA ops implementation for all platforms, so select the symbol globally. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19540/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: loongson: remove loongson-3 handling from dma-coherence.hChristoph Hellwig1-15/+1
Loongson3 is dma coherent and uses swiotlb, so it will never used any of these helpers. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19541/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: Octeon: move swiotlb declarations out of dma-coherence.hChristoph Hellwig2-18/+3
No need to pull them into a global header. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19538/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: Octeon: remove mips dma-default stubsChristoph Hellwig1-48/+0
Octeon doesn't use the dma-default code, and now doesn't built it either, so these stubs can be removed. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19537/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: make the default mips dma implementation optionalChristoph Hellwig1-1/+3
Octeon and loonson64 already don't use it at all, and we're going to migrate more plaforms away from it. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19536/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: remove the mips_dma_map_ops indirectionChristoph Hellwig1-2/+2
And use mips_default_dma_map_ops directly. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19535/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: consolidate the swiotlb implementationsChristoph Hellwig4-22/+21
Octeon and Loongson share exactly the same code, move it into a common implementation, and use that implementation directly from get_arch_dma_ops. Also provide the expected dma-direct.h helpers directly instead of delegating to platform dma-coherence.h headers. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19534/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
2018-06-24MIPS: Octeon: refactor swiotlb codeChristoph Hellwig1-2/+0
Share a common set of swiotlb operations, and to instead branch out in __phys_to_dma/__dma_to_phys for the PCI vs non-PCI case. Also use const structures for the PCI methods so that attackers can't use them as exploit vectors. Signed-off-by: Christoph Hellwig <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/19532/ Signed-off-by: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: David Daney <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Tom Bogendoerfer <[email protected]> Cc: Huacai Chen <[email protected]> Cc: [email protected] Cc: [email protected]
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