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Add the following instructions for use by eBPF on mipsr6:
insn_ddivu_r6, insn_divu_r6, insn_dmodu, insn_dmulu, insn_modu,
insn_mulu, insn_seleqz, insn_selnez
Signed-off-by: Hassan Naveed <[email protected]>
Reviewed-by: Paul Burton <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Ralf Baechle <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Alexei Starovoitov <[email protected]>
Cc: Daniel Borkmann <[email protected]>
Cc: open list:MIPS <[email protected]>
Cc: open list <[email protected]>
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Jitting of BPF_K is supported already, but not BPF_X. This patch complete
the support for the latter on both MIPS and microMIPS.
Cc: Paul Burton <[email protected]>
Cc: [email protected]
Acked-by: Paul Burton <[email protected]>
Signed-off-by: Jiong Wang <[email protected]>
Signed-off-by: Alexei Starovoitov <[email protected]>
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Follow on patches for eBPF JIT require these additional instructions:
insn_bgtz, insn_blez, insn_break, insn_ddivu, insn_dmultu,
insn_dsbh, insn_dshd, insn_dsllv, insn_dsra32, insn_dsrav,
insn_dsrlv, insn_lbu, insn_movn, insn_movz, insn_multu, insn_nor,
insn_sb, insn_sh, insn_slti, insn_dinsu, insn_lwu
... so, add them.
Sort the insn_* enumeration values alphabetically.
Signed-off-by: David Daney <[email protected]>
Cc: Alexei Starovoitov <[email protected]>
Cc: Daniel Borkmann <[email protected]>
Cc: Matt Redfearn <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/16367/
Signed-off-by: Ralf Baechle <[email protected]>
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We always either target MIPS32/MIPS64 or microMIPS, and always include
one & only one of uasm-mips.c or uasm-micromips.c. Therefore the
abstraction of the ISA in asm/uasm.h declaring functions for either ISA
is redundant & needless. Remove it to simplify the code.
This is largely the result of the following:
:%s/ISAOPC(\(.\{-}\))/uasm_i##\1/
:%s/ISAFUNC(\(.\{-}\))/\1/
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Paul Burton <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/15844/
Signed-off-by: Ralf Baechle <[email protected]>
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The follow-on BPF JIT patches use the LHU instruction, so add it.
Signed-off-by: David Daney <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Alexei Starovoitov <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/15743/
Signed-off-by: Ralf Baechle <[email protected]>
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Add include guards in asm/uasm.h to allow it to be safely used by a new
header asm/tlbex.h in the next patch to expose TLB exception building
functions for KVM to use.
Signed-off-by: James Hogan <[email protected]>
Acked-by: Ralf Baechle <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: Paolo Bonzini <[email protected]>
Cc: "Radim Krčmář" <[email protected]>
Cc: [email protected]
Cc: [email protected]
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Add MTHI/MTLO instructions for writing to the hi & lo registers to uasm
so that KVM can use uasm for generating its entry point code at runtime.
Signed-off-by: James Hogan <[email protected]>
Acked-by: Ralf Baechle <[email protected]>
Cc: [email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
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Add DI instruction for disabling interrupts to uasm so that KVM can use
uasm for generating its entry point code at runtime.
Signed-off-by: James Hogan <[email protected]>
Acked-by: Ralf Baechle <[email protected]>
Cc: [email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
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Add CFCMSA/CTCMSA instructions for accessing MSA control registers to
uasm so that KVM can use uasm for generating its entry point code at
runtime.
Signed-off-by: James Hogan <[email protected]>
Acked-by: Ralf Baechle <[email protected]>
Cc: [email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
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Add CFC1/CTC1 instructions for accessing FP control registers to uasm so
that KVM can use uasm for generating its entry point code at runtime.
Signed-off-by: James Hogan <[email protected]>
Acked-by: Ralf Baechle <[email protected]>
Cc: [email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
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Loongson-3A R2 has pwbase/pwfield/pwsize/pwctl registers in CP0 (this
is very similar to HTW) and lwdir/lwpte/lddir/ldpte instructions which
can be used for fast TLB refill.
[[email protected]: Resolve conflict.]
Signed-off-by: Huacai Chen <[email protected]>
Cc: Aurelien Jarno <[email protected]>
Cc: Steven J . Hill <[email protected]>
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/12754/
Signed-off-by: Ralf Baechle <[email protected]>
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New instructions for Extended Physical Addressing (XPA) functionality.
Signed-off-by: Steven J. Hill <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/8453/
Signed-off-by: Ralf Baechle <[email protected]>
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It will be used later on by bpf-jit
Signed-off-by: Markos Chandras <[email protected]>
Cc: [email protected]
Cc: Markos Chandras <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/7120/
Signed-off-by: Ralf Baechle <[email protected]>
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It will be used later on by the SLT instruction.
Signed-off-by: Markos Chandras <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/7119/
Signed-off-by: Ralf Baechle <[email protected]>
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It will be used later on by bpf-jit
[[email protected]: Resolved conflict.]
Signed-off-by: Markos Chandras <[email protected]>
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It will be used later on by bpf-jit
[[email protected]: Resolved conflict.]
Signed-off-by: Markos Chandras <[email protected]>
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It will be used later on by bpf-jit
[[email protected]: Resolved conflict.]
Signed-off-by: Markos Chandras <[email protected]>
Cc: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/6736/
Signed-off-by: Ralf Baechle <[email protected]>
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It will be used later on by bpf-jit
[[email protected]: Resolved conflict.]
Signed-off-by: Markos Chandras <[email protected]>
Cc: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/6733/
Signed-off-by: Ralf Baechle <[email protected]>
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It will be used later on by bpf-jit
[[email protected]: Resolved conflict.]
Signed-off-by: Markos Chandras <[email protected]>
Cc: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/6732/
Signed-off-by: Ralf Baechle <[email protected]>
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It will be used later on by bpf-jit
[[email protected]: Resolved conflict.]
Signed-off-by: Markos Chandras <[email protected]>
Cc: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/6731/
Signed-off-by: Ralf Baechle <[email protected]>
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It will be used later on by bpf-jit
[[email protected]: Resolved conflict.]
Signed-off-by: Markos Chandras <[email protected]>
Cc: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/6730/
Signed-off-by: Ralf Baechle <[email protected]>
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It will be used later on by bpf-jit
[[email protected]: Resolved conflict.]
Signed-off-by: Markos Chandras <[email protected]>
Cc: [email protected]
Cc: Markos Chandras <[email protected]>
Patchwork: http://patchwork.linux-mips.org/patch/6728/
Signed-off-by: Ralf Baechle <[email protected]>
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It will be used later on by bpf-jit
[[email protected]: Resolved conflict.]
Signed-off-by: Markos Chandras <[email protected]>
Cc: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/6727/
Signed-off-by: Ralf Baechle <[email protected]>
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It will be used later on by bpf-jit
[[email protected]: Fixed conflict due to other preceeding conflicts.]
Signed-off-by: Markos Chandras <[email protected]>
Cc: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/6726/
Signed-off-by: Ralf Baechle <[email protected]>
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It will be used later on by bpf-jit
[[email protected]: Fixed conflict with
49e9529b9d43773307b8c73bd251b71784830c3d [MIPS: uasm: add jalr instruction].
Signed-off-by: Markos Chandras <[email protected]>
Cc: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/6725/
Signed-off-by: Ralf Baechle <[email protected]>
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It will be used later on by the sllv and srlv instructions.
Signed-off-by: Markos Chandras <[email protected]>
Cc: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/6723/
Signed-off-by: Ralf Baechle <[email protected]>
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This patch allows use of the MT ASE yield instruction from uasm. It will
be used by a subsequent patch.
Signed-off-by: Paul Burton <[email protected]>
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This patch allows use of the wait instruction from uasm. It will be used
by a subsequent patch.
Signed-off-by: Paul Burton <[email protected]>
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This patch allows use of the sync instruction from uasm. It will be used
by a subsequent patch.
Signed-off-by: Paul Burton <[email protected]>
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This patch allows use of the jalr instruction from uasm. It will be used
by a subsequent patch.
Signed-off-by: Paul Burton <[email protected]>
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This patch allows for use of the beq instruction with labels from uasm,
much as bne & others already do. It will be used by a subsequent patch.
Signed-off-by: Paul Burton <[email protected]>
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commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
from asm files. MIPS is interesting in this respect, because there
are also uasm users hiding behind their own renamed versions of the
__cpuinit macros.
[1] https://lkml.org/lkml/2013/5/20/589
[[email protected]: Folded in Paul's followup fix.]
Signed-off-by: Paul Gortmaker <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/5494/
Patchwork: https://patchwork.linux-mips.org/patch/5495/
Patchwork: https://patchwork.linux-mips.org/patch/5509/
Signed-off-by: Ralf Baechle <[email protected]>
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The macros did not properly take into account the ISA that
the kernel was being compiled with. A classic MIPS kernel
will have the standard 'uasm_i_##op' macro functions with
'MM_uasm_i_##op' macro functions for the microMIPS version.
A pure microMIPS kernel will have the standard macros with
'CL_uasm_i_##op' macro functions for the classic version.
Signed-off-by: Steven J. Hill <[email protected]>
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Add new file 'uasm-micromips.c' that allows the micro assembler
to generate microMIPS ISA code. It can be included in the kernel
alongside the classic ISA as long as the platform supports the
microMIPS ISA.
Signed-off-by: Steven J. Hill <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/4923/
Signed-off-by: Ralf Baechle <[email protected]>
(cherry picked from commit 5f011a866afbd03a5379f67f4e70e5efbdfc16e9)
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Split 'uasm.c' into two files. The new file 'uasm-mips.c' has the
functions specific to the classic MIPS ISA. The 'uasm.c' file
contains common code that can be used by classic or other ISAs
that could be supported by the kernel.
Signed-off-by: Steven J. Hill <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/4922/
Signed-off-by: Ralf Baechle <[email protected]>
(cherry picked from commit 0961103562ab958fa74f35043bf4f72e51ed6155)
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Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.
Signed-off-by: Ralf Baechle <[email protected]>
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These are MIPS32R2 instructions for merging and extracting bit fields
from one GPR into another.
Signed-off-by: Steven J. Hill <[email protected]>
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A number of new instructions have been added to the micro assembler causing
the list to no longer be in alphabetical order. This patch fixes up the name
ordering.
Signed-off-by: Steven J. Hill <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/3789/
Signed-off-by: Ralf Baechle <[email protected]>
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Putting module.h into widely used headers just bogs cpp down with reams of
stuff that isn't needed. Here, we only need visibility to EXPORT_SYMBOL.
Signed-off-by: Paul Gortmaker <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/3450/
Signed-off-by: Ralf Baechle <[email protected]>
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This can be used from either 32-bit or 64-bit code to generate logical
right shifts of any constant amount.
Signed-off-by: David Daney <[email protected]>
To: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/2576/
Signed-off-by: Ralf Baechle <[email protected]>
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Needed by Octeon II optimized TLB handlers.
Signed-off-by: David Daney <[email protected]>
To: [email protected]
Pachwork: https://patchwork.linux-mips.org/patch/1903/
Signed-off-by: Ralf Baechle <[email protected]>
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these are already defined, but declaring them allow them to be used
outside of uasm.c.
Signed-off-by: David Daney <[email protected]>
To: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/1872/
Signed-off-by: Ralf Baechle <[email protected]>
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Signed-off-by: David Daney <[email protected]>
To: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/1875/
Signed-off-by: Ralf Baechle <[email protected]>
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A 'select EXPORT_UASM' in Kconfig will cause the uasm to be exported
for use in modules. When it is exported, all the uasm data and code
cease to be __init and __initdata.
Also daddiu_bug cannot be __cpuinitdata if uasm is exported. The
cleanest thing is to just make it normal data.
Signed-off-by: David Daney <[email protected]>
To: [email protected]
To: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/1500/
Signed-off-by: Ralf Baechle <[email protected]>
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These are OCTEON specific instructions.
Signed-off-by: David Daney <[email protected]>
To: [email protected]
To: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/1496/
Signed-off-by: Ralf Baechle <[email protected]>
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Signed-off-by: David Daney <[email protected]>
To: [email protected]
To: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/1495/
Signed-off-by: Ralf Baechle <[email protected]>
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This allows us to clean up the code by not having to explicitly code
checks for shift amounts greater than 32.
Signed-off-by: David Daney <[email protected]>
To: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/1153/
Signed-off-by: Ralf Baechle <[email protected]>
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This is needed for the fix of the M3 workaround.
Signed-off-by: Ralf Baechle <[email protected]>
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Signed-off-by: David Daney <[email protected]>
To: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/976/
Signed-off-by: Ralf Baechle <[email protected]>
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The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBR and
ROTR support in uasm. We also add a UASM_i_ROTR macro.
Signed-off-by: David Daney <[email protected]>
To: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/953/
Signed-off-by: Ralf Baechle <[email protected]>
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