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2015-08-03MIPS: Flush RPS on kernel entry with EVAJames Hogan1-0/+25
When EVA is enabled, flush the Return Prediction Stack (RPS) present on some MIPS cores on entry to the kernel from user mode. This is important specifically for interAptiv with EVA enabled, otherwise kernel mode RPS mispredicts may trigger speculative fetches of user return addresses, which may be sensitive in the kernel address space due to EVA's overlapping user/kernel address spaces. Signed-off-by: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: Markos Chandras <[email protected]> Cc: Leonid Yegoshin <[email protected]> Cc: [email protected] Cc: <[email protected]> # 3.15.x- Patchwork: https://patchwork.linux-mips.org/patch/10812/ Signed-off-by: Ralf Baechle <[email protected]>
2015-02-17MIPS: asm: stackframe: Do not preserve the HI/LO registers on MIPS R6Leonid Yegoshin1-4/+4
The HI/LO registers have been removed from MIPS R6. Instructions such as MULT and DIV have been replaced with a new pair of instructions for the HI/LO operations for example: MULT -> MUL, MUH DIV -> DIV, MOD So we avoid preserving the pre-R6 HI/LO registers in MIPS R6 Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]>
2014-05-24MIPS: MT: Remove SMTC supportRalf Baechle1-195/+1
Nobody is maintaining SMTC anymore and there also seems to be no userbase. Which is a pity - the SMTC technology primarily developed by Kevin D. Kissell <[email protected]> is an ingenious demonstration for the MT ASE's power and elegance. Based on Markos Chandras <[email protected]> patch https://patchwork.linux-mips.org/patch/6719/ which while very similar did no longer apply cleanly when I tried to merge it plus some additional post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to merge once upon a time. Signed-off-by: Ralf Baechle <[email protected]>
2014-03-31MIPS: Fix gigaton of warning building with microMIPS.Ralf Baechle1-1/+1
With binutils 2.24 the attempt to switch with microMIPS mode to MIPS III mode through .set mips3 results in *lots* of warnings like {standard input}: Assembler messages: {standard input}:397: Warning: the 64-bit MIPS architecture does not support the `smartmips' extension during a kernel build. Fixed by using .set arch=r4000 instead. This breaks support for building the kernel with binutils 2.13 which was supported for 32 bit kernels only anyway and 2.14 which was a bad vintage for MIPS anyway. Signed-off-by: Ralf Baechle <[email protected]>
2013-10-29MIPS: Move definition of SMP processor id register to header fileJayachandran C1-18/+6
The definition of the CP0 register used to save the smp processor id is repicated in many files, move them all to thread_info.h. Signed-off-by: Jayachandran C <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5708/ Signed-off-by: Ralf Baechle <[email protected]>
2013-07-01MIPS: Don't save/restore OCTEON wide multiplier state on syscalls.David Daney1-15/+14
The ABI allows these to be clobbered on syscalls, so only save and restore the multiplier state when the temporary registers need to be preserved. Signed-off-by: David Daney <[email protected]> Cc: [email protected] Cc: David Daney <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/5540/ Signed-off-by: Ralf Baechle <[email protected]>
2013-05-09MIPS: microMIPS: Add support for exception handling.Steven J. Hill1-6/+6
All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <[email protected]>
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle1-7/+7
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <[email protected]>
2011-09-21MIPS: Don't clobber CP0_STATUS value for CONFIG_MIPS_MT_SMTCDavid Daney1-2/+2
Reported-by: Edgar E. Iglesias <[email protected]> Signed-off-by: David Daney <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/2753/ Signed-off-by: Ralf Baechle <[email protected]>
2011-03-31Fix common misspellingsLucas De Marchi1-1/+1
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <[email protected]>
2010-04-30MIPS: Loongson-2F: Use CONFIG_CPU_JUMP_WORKAROUNDS to control workarounds.Wu Zhangjin1-1/+1
Signed-off-by: Wu Zhangjin <[email protected]> Cc: linux-mips <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/1106/ Signed-off-by: Ralf Baechle <[email protected]>
2010-04-12MIPS: Loongson-2F: Flush the branch target history in BTB and RASWu Zhangjin1-0/+19
As per chapter 15 "Errata: Issue of Out-of-order in loongson"[1] to work around the Loongson 2F erratum we need to do: "When switching from user mode to kernel mode, you should flush the branch target history such as BTB and RAS." [1] Chinese version: http://www.loongson.cn/uploadfile/file/200808211 [2] English version of chapter 15: http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source Signed-off-by: Wu Zhangjin <[email protected]> Cc: [email protected] Cc: Shinya Kuribayashi <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/1066/ Signed-off-by: Ralf Baechle <[email protected]>
2009-12-17MIPS: Put PGD in C0_CONTEXT for 64-bit R2 processors.David Daney1-10/+10
Processors that support the mips64r2 ISA can in four instructions convert a shifted PGD pointer stored in the upper bits of c0_context into a usable pointer. By doing this we save a memory load and associated potential cache miss in the TLB exception handlers. Since the upper bits of c0_context were holding the CPU number, we move this to the upper bits of c0_xcontext which doesn't have enough bits to hold the PGD pointer, but has plenty for the CPU number. Signed-off-by: David Daney <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2009-12-17MIPS: Reorder operations in stackframe.h for better schedulingDavid Daney1-8/+12
Reorder PT ops to avoid pipeline stalls. Signed-off-by: David Daney <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2009-01-11MIPS: Cavium OCTEON multiplier state preservation.David Daney1-0/+17
For OCTEON, implement a save and restore of the multiplier state across context switches. Signed-off-by: Tomaso Paoletti <[email protected]> Signed-off-by: David Daney <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2008-10-11MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle1-0/+574
Signed-off-by: Ralf Baechle <[email protected]>
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