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2010-08-05MIPS: Octeon: Allow more than 3.75GB of memory with PCIeDavid Daney1-0/+13
We reserve the 3.75GB - 4GB region of PCIe address space for device to device transfers, making the corresponding physical memory under direct mapping unavailable for DMA. To allow for PCIe DMA to all physical memory we map this chunk of physical memory with BAR1. Because of the resulting discontinuity in the mapping function, we remove a page of memory at each end of the range so multi-page DMA buffers can never be allocated that span the range. Signed-off-by: David Daney <[email protected]> To: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/1535/ Signed-off-by: Ralf Baechle <[email protected]>
2010-08-05MIPS: Octeon: Implement delays with cycle counter.David Daney1-0/+1
Power throttling make deterministic delay loops impossible. Re-implement delays using the cycle counter. This also allows us to get rid of the code that calculates loops per jiffy. Signed-off-by: David Daney <[email protected]> To: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/1317/ Signed-off-by: Ralf Baechle <[email protected]>
2010-08-05MIPS: Octeon: HOTPLUG_CPU fixes.David Daney1-0/+2
* Rename camel-case InitTLBStart_addr to octeon_bootloader_entry_addr. * Convert calls to cvmx_read64_uint32(), to simple pointer dereferences. * Set proper ebase. * Don't confuse coreid and cpu numbers. * Try to maintain consistent bootloader coremask. * Update the signature and boot_init_vector of supported bootloaders. Signed-off-by: David Daney <[email protected]> To: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/1491/ Signed-off-by: Ralf Baechle <[email protected]>
2010-02-27MIPS: Cleanup switches with cases that can be mergedRoel Kluin1-6/+2
Signed-off-by: Roel Kluin <[email protected]> To: [email protected] To: Andrew Morton <[email protected]> To: LKML <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/860/ Signed-off-by: Ralf Baechle <[email protected]>
2010-02-27MIPS: Octeon: Add I2C platform device.David Daney1-0/+5
Signed-off-by: David Daney <[email protected]> To: [email protected] To: [email protected] To: [email protected] To: [email protected] Cc: Rade Bozic <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/847/ Signed-off-by: Ralf Baechle <[email protected]>
2009-12-17MIPS: Modularize COP2 handlingRalf Baechle1-0/+1
Away with the daemons of ifdef; get ready for future COP2 users. Signed-off-by: Ralf Baechle <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/708/
2009-12-17MIPS: Octeon: Add register definitions for MGMT Ethernet driver.David Daney2-0/+1442
Signed-off-by: David Daney <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2009-12-17NET: Add driver for Octeon MDIO buses.David Daney1-0/+178
The Octeon SOC has two types of Ethernet ports, each type with its own driver. However, the PHYs for all the ports are controlled by a common MDIO bus. Because the mdio driver is not associated with a particular driver, but is instead a system level resource, we create s stand-alone driver for it. As for the driver, we put the register definitions in arch/mips/include/asm/octeon where most of the other Octeon register definitions live. This is a platform driver with the platform device for "mdio-octeon" being registered in the platform startup code. Signed-off-by: David Daney <[email protected]> Acked-by: David S. Miller <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2009-09-17MIPS: Octeon: Add hardware RNG platform device.David Daney1-0/+88
Add a platform device for the Octeon Random Number Generator (RNG). Signed-off-by: David Daney <[email protected]> Acked-by: Herbert Xu <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2009-09-17MIPS: Octeon: Check all CCAs in cvmx_write_csr.David Daney1-1/+1
The current code only checks CCA of 0 when deciding if a dummy read is needed. Since the kernel can (and does) use other CCAs we need to mask out the CCA bits from the address. Since the address constant now fits in 16 bits, there is an added benefit that smaller code is generated. Signed-off-by: David Daney <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2009-07-03MIPS: Reorganize Cavium OCTEON PCI support.David Daney1-0/+45
Move the cavium PCI files to the arch/mips/pci directory. Also cleanup comment formatting and code layout. Code from pci-common.c, was moved into other files. Signed-off-by: David Daney <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2009-06-17MIPS: Cavium-Octeon: Add more chip specific feature tests.David Daney1-0/+27
The octeon-ethernet driver needs to check for additional chip specific features, we add them to the octeon_has_feature() framework. Signed-off-by: David Daney <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2009-06-17MIPS: Cavium-Octeon: Add more board type constants.David Daney1-0/+13
The bootloader now uses additional board type constants. The octeon-ethernet driver needs some of the new values. Signed-off-by: David Daney <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2009-06-17MIPS: Add named alloc functions to OCTEON boot monitor memory allocator.David Daney1-0/+85
The various Octeon ethernet drivers use these new functions. Signed-off-by: David Daney <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2009-06-17MIPS: Add Cavium OCTEON PCI support.David Daney4-0/+90
This patch adds support for PCI and PCIe to the base Cavium OCTEON processor support. Signed-off-by: David Daney <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2009-06-17MIPS: Add register definitions for PCI.David Daney7-0/+9341
Here we add the register definitions for the processor blocks used by the following PCI support patch. Signed-off-by: David Daney <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2009-01-11MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.David Daney1-0/+248
These are the rest of the new files needed to add OCTEON processor support to the Linux kernel. Other than Makefile and Kconfig which should be obvious, we have: csrc-octeon.c -- Clock source driver for OCTEON. dma-octeon.c -- Helper functions for mapping DMA memory. flash_setup.c -- Register on-board flash with the MTD subsystem. octeon-irq.c -- OCTEON interrupt controller managment. octeon-memcpy.S -- Optimized memcpy() implementation. serial.c -- Register 8250 platform driver and early console. setup.c -- Early architecture initialization. smp.c -- OCTEON SMP support. octeon_switch.S -- Scheduler context switch for OCTEON. c-octeon.c -- OCTEON cache controller support. cex-oct.S -- OCTEON cache exception handler. asm/mach-cavium-octeon/*.h -- Architecture include files. Signed-off-by: Tomaso Paoletti <[email protected]> Signed-off-by: David Daney <[email protected]> Signed-off-by: Ralf Baechle <[email protected]> create mode 100644 arch/mips/cavium-octeon/Kconfig create mode 100644 arch/mips/cavium-octeon/Makefile create mode 100644 arch/mips/cavium-octeon/csrc-octeon.c create mode 100644 arch/mips/cavium-octeon/dma-octeon.c create mode 100644 arch/mips/cavium-octeon/flash_setup.c create mode 100644 arch/mips/cavium-octeon/octeon-irq.c create mode 100644 arch/mips/cavium-octeon/octeon-memcpy.S create mode 100644 arch/mips/cavium-octeon/serial.c create mode 100644 arch/mips/cavium-octeon/setup.c create mode 100644 arch/mips/cavium-octeon/smp.c create mode 100644 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/irq.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/war.h create mode 100644 arch/mips/include/asm/octeon/octeon.h create mode 100644 arch/mips/kernel/octeon_switch.S create mode 100644 arch/mips/mm/c-octeon.c create mode 100644 arch/mips/mm/cex-oct.S
2009-01-11MIPS: Add Cavium OCTEON processor support files to ↵David Daney10-0/+2393
arch/mips/cavium-octeon/executive and asm/octeon. These files are used to coordinate resource sharing between all of the programs running on the OCTEON SOC. The OCTEON processor has many CPU cores (current parts have up to 16, but more are possible). It also has a variety of on-chip hardware blocks for things like network acceleration, encryption and RAID. One typical configuration is to run Linux on several of the CPU cores, and other dedicated applications on the other cores. Resource allocation between the various programs running on the system (Linux kernel and other dedicated applications) needs to be coordinated. The code we use to do this we call the 'executive'. All of this resource allocation and sharing code is gathered together in the executive directory. Included in the patch set are the following files: cvmx-bootmem.c and cvmx-sysinfo.c -- Coordinate memory allocation. All memory used by the Linux kernel is obtained here at boot time. cvmx-l2c.c -- Coordinates operations on the shared level 2 cache. octeon-model.c -- Probes chip capabilities and version. The corresponding headers are in asm/octeon. Signed-off-by: Tomaso Paoletti <[email protected]> Signed-off-by: David Daney <[email protected]> Signed-off-by: Ralf Baechle <[email protected]> create mode 100644 arch/mips/cavium-octeon/executive/Makefile create mode 100644 arch/mips/cavium-octeon/executive/cvmx-bootmem.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-l2c.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-sysinfo.c create mode 100644 arch/mips/cavium-octeon/executive/octeon-model.c create mode 100644 arch/mips/include/asm/octeon/cvmx-asm.h create mode 100644 arch/mips/include/asm/octeon/cvmx-bootinfo.h create mode 100644 arch/mips/include/asm/octeon/cvmx-bootmem.h create mode 100644 arch/mips/include/asm/octeon/cvmx-l2c.h create mode 100644 arch/mips/include/asm/octeon/cvmx-packet.h create mode 100644 arch/mips/include/asm/octeon/cvmx-spinlock.h create mode 100644 arch/mips/include/asm/octeon/cvmx-sysinfo.h create mode 100644 arch/mips/include/asm/octeon/cvmx.h create mode 100644 arch/mips/include/asm/octeon/octeon-feature.h create mode 100644 arch/mips/include/asm/octeon/octeon-model.h
2009-01-11MIPS: Add Cavium OCTEON processor CSR definitionsDavid Daney10-0/+7657
Here we define the addresses and bit-fields of the Configuration and Status Registers (CSRs) for some of the hardware functional units on the OCTEON SOC. Definitions are needed for: CIU -- Central Interrupt Unit. GPIO -- General Purpose Input Output. IOB -- Input / Output {Busing,Bridge}. IPD -- Input Packet Data unit. L2C -- Level-2 Cache controller. L2D -- Level-2 Data cache. L2T -- Level-2 cache Tag. LED -- Light Emitting Diode controller. MIO -- Miscellaneous Input / Output. POW -- Packet Order / Work unit. Signed-off-by: Tomaso Paoletti <[email protected]> Signed-off-by: David Daney <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
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