aboutsummaryrefslogtreecommitdiff
path: root/arch/mips/include/asm/mipsregs.h
AgeCommit message (Collapse)AuthorFilesLines
2014-11-24MIPS: cpu-probe: Set the FTLB probability bit on supported coresMarkos Chandras1-0/+2
Make use of the Config6/FLTBP bit to set the probability of a TLBWR instruction to hit the FTLB or the VTLB. A value of 0 (which may be the default value on certain cores, such as proAptiv or P5600) means that a TLBWR instruction will never hit the VTLB which leads to performance limitations since it effectively decreases the number of available TLB slots. Signed-off-by: Markos Chandras <[email protected]> Reviewed-by: James Hogan <[email protected]> Cc: <[email protected]> # v3.15+ Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8368/ Signed-off-by: Ralf Baechle <[email protected]>
2014-11-07MIPS: Fix build with binutils 2.24.51+Manuel Lauss1-1/+10
Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <[email protected]> Cc: Linux-MIPS <[email protected]> Cc: Matthew Fortune <[email protected]> Cc: Markos Chandras <[email protected]> Cc: Maciej W. Rozycki <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <[email protected]>
2014-08-02MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFTDan Carpenter1-1/+0
The MIPS_CONF4_FTLBSETS_SHIFT define is cut and pasted twice so we can remove the second define. Signed-off-by: Dan Carpenter <[email protected]> Cc: Steven J. Hill <[email protected]> Cc: Markos Chandras <[email protected]> Cc: John Crispin <[email protected]> Cc: Paul Burton <[email protected]> Cc: Leonid Yegoshin <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7063/ Signed-off-by: Ralf Baechle <[email protected]>
2014-08-02MIPS: define MAAR register accessors & bitsPaul Burton1-0/+12
Add accessor macros for the Memory Accessibility Attribute Registers (MAARs), the bits contained within the MAARs & the Config5.MRP bit indicating their presence. The only current use of the MAARs is to enable speculative accesses to regions of memory. Besides the potential performance benefits of speculative accesses, they are a requirement for the P5600 core to handle non-128b-aligned MSA vector loads & stores rather than generating an address error. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7329/ Signed-off-by: Ralf Baechle <[email protected]>
2014-08-02MIPS: kernel: cpu-probe: Detect unique RI/XI exceptionsLeonid Yegoshin1-0/+1
Detect if the core supports unique exception codes for the Read-Inhibit and Execute-Inhibit exceptions and set the option accordingly. The RI/XI exception support is detected by setting the 27th bit (IEC) of the PageGrain C0 register and reading back the value of that register to verify the bit is enabled. Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7340/ Signed-off-by: Ralf Baechle <[email protected]>
2014-08-02MIPS: asm: Add register definitions for Hardware Table WalkerMarkos Chandras1-0/+44
Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7326/ Signed-off-by: Ralf Baechle <[email protected]>
2014-05-30MIPS: Add function get_ebase_cpunumDavid Daney1-0/+9
This returns the CPUNum from the low order Ebase bits. Signed-off-by: David Daney <[email protected]> Signed-off-by: Andreas Herrmann <[email protected]> Cc: [email protected] Cc: James Hogan <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7012/ Signed-off-by: Ralf Baechle <[email protected]>
2014-05-24MIPS: MT: Remove SMTC supportRalf Baechle1-132/+1
Nobody is maintaining SMTC anymore and there also seems to be no userbase. Which is a pity - the SMTC technology primarily developed by Kevin D. Kissell <[email protected]> is an ingenious demonstration for the MT ASE's power and elegance. Based on Markos Chandras <[email protected]> patch https://patchwork.linux-mips.org/patch/6719/ which while very similar did no longer apply cleanly when I tried to merge it plus some additional post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to merge once upon a time. Signed-off-by: Ralf Baechle <[email protected]>
2014-05-23MIPS: Disable MIPS16/microMIPS crap for platforms not supporting these ASEs.Ralf Baechle1-1/+8
Signed-off-by: Ralf Baechle <[email protected]>
2014-03-26MIPS: Add MSA register definitions & accessPaul Burton1-0/+1
This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-06MIPS: Add CP0 CMGCRBase definitions & accessorPaul Burton1-0/+6
The CMGCRBase register is defined by the PRA specification as an optional register which indicates the physical base of the MIPS Coherence Manager Global Control Register block. This patch simply adds a definition for the base address field within the register, along with an accessor function for reading the register. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6356/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-06MIPS: Define Config1 cache field shifts & sizesPaul Burton1-0/+12
These fields will be used from assembly code in a subsequent commit, and defining the size & offset of each field makes that use easier. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6355/ Signed-off-by: Ralf Baechle <[email protected]>
2014-03-06MIPS: mm: c-r4k: Detect instruction cache aliasesMarkos Chandras1-0/+3
The *Aptiv cores can use the CONF7/IAR bit to detect if the core has hardware support to remove instruction cache aliasing. This also defines the CONF7/AR bit in order to avoid using the '16' magic number. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/6499/ Signed-off-by: Ralf Baechle <[email protected]>
2014-01-23MIPS: include linux/types.hQais Yousef1-0/+1
The file uses u16 type but doesn't include its definition explicitly I was getting this error when including this header in my driver: arch/mips/include/asm/mipsregs.h:644:33: error: unknown type name ‘u16’ Signed-off-by: Qais Yousef <[email protected]> Reviewed-by: Steven J. Hill <[email protected]> Acked-by: David Daney <[email protected]> Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/6212/
2014-01-22MIPS: Add support for FTLBsLeonid Yegoshin1-0/+2
The Fixed Page Size TLB (FTLB) is a set-associative dual entry TLB. Its purpose is to reduce the number of TLB misses by increasing the effective TLB size and keep the implementation complexity to minimum levels. A supported core can have both VTLB and FTLB. Reviewed-by: James Hogan <[email protected]> Reviewed-by: Paul Burton <[email protected]> Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/6139/
2014-01-22MIPS: Add function for flushing the TLB using the TLBINV instructionLeonid Yegoshin1-0/+13
Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/6136/
2014-01-22MIPS: features: Add initial support for Segmentation Control registersSteven J. Hill1-0/+29
MIPS32R3 introduced a new set of Segmentation Control registers which increase the flexibility of the segmented-based memory scheme. Signed-off-by: Steven J. Hill <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/6131/
2014-01-22MIPS: Add missing bits for Config registersLeonid Yegoshin1-2/+38
Signed-off-by: Leonid Yegoshin <[email protected]> Signed-off-by: Markos Chandras <[email protected]> Acked-by: David Daney <[email protected]> Signed-off-by: John Crispin <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/6128/
2013-09-19MIPS: Add MIPS R5 config5 register.Ralf Baechle1-0/+7
Signed-off-by: Ralf Baechle <[email protected]>
2013-07-01MIPS: microMIPS: Fix improper definition of ISA exception bit.Steven J. Hill1-1/+1
The ISA exception bit selects whether exceptions are taken in classic or microMIPS mode. This bit is Config3.ISAOnExc and was improperly defined as bits 16 and 17 instead of just bit 16. A new function was added so that platforms could set this bit when running a kernel compiled with only microMIPS instructions. Signed-off-by: Steven J. Hill <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5377/ Signed-off-by: Ralf Baechle <[email protected]>
2013-05-09MIPS: microMIPS: Add support for exception handling.Steven J. Hill1-0/+1
All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <[email protected]>
2013-05-01MIPS: microMIPS: Add instruction utility macros.Steven J. Hill1-0/+18
Add two new macros for microMIPS. One checks if an exception was taken in either microMIPS or classic MIPS mode. The other checks if a microMIPS instruction is 16-bit or 32-bit in length. [[email protected]: Removed unnecessary parenthesis as noted by Sergei Shtylyov <[email protected]>] Signed-off-by: Steven J. Hill <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: Sergei Shtylyov <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/4924/ Signed-off-by: Ralf Baechle <[email protected]> (cherry picked from commit 49df26472338b935fd5781bf94a77a88b148a716)
2013-03-19MIPS: Fix code generation for non-DSP capable CPUsFlorian Fainelli1-19/+190
Commit 32a7ede (MIPS: dsp: Add assembler support for DSP ASEs) has enabled the use of DSP ASE specific instructions such as rddsp and wrdsp under the idea that all code path that will make use of these two instructions are properly checking for cpu_has_dsp to ensure that the particular CPU we are running on *actually* supports DSP ASE. This commit actually causes the following oops on QEMU Malta emulating a MIPS 24Kc without the DSP ASE implemented: [ 7.960000] Reserved instruction in kernel [ 7.960000] Cpu 0 [ 7.960000] $ 0 : 00000000 00000000 00000014 00000005 [ 7.960000] $ 4 : 8fc2de48 00000001 00000000 8f59ddb0 [ 7.960000] $ 8 : 8f5ceec4 00000018 00000c00 00800000 [ 7.960000] $12 : 00000100 00000200 00000000 00457b84 [ 7.960000] $16 : 00000000 8fc2ba78 8f4ec980 00000001 [ 7.960000] $20 : 80418f90 00000000 00000000 000002dd [ 7.960000] $24 : 0000009c 7730d7b8 [ 7.960000] $28 : 8f59c000 8f59dd38 00000001 80104248 [ 7.960000] Hi : 0000001d [ 7.960000] Lo : 0000000b [ 7.960000] epc : 801041ec thread_saved_pc+0x2c/0x38 [ 7.960000] Not tainted [ 7.960000] ra : 80104248 get_wchan+0x48/0xac [ 7.960000] Status: 1000b703 KERNEL EXL IE [ 7.960000] Cause : 10800028 [ 7.960000] PrId : 00019300 (MIPS 24Kc) [ 7.960000] Modules linked in: [ 7.960000] Process killall (pid: 1574, threadinfo=8f59c000, task=8fd14558, tls=773aa440) [ 7.960000] Stack : 8fc2ba78 8012b008 0000000c 0000001d 00000000 00000000 8f58a380 8f58a380 8fc2ba78 80202668 8f59de78 8f468600 8f59de28 801b2a3c 8f59df00 8f98ba20 74696e69 8f468600 8f59de28 801b7308 0081c007 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8fc2bbb4 00000001 0000001d 0000000b 77f038cc 7fe80648 ffffffff ffffffff 00000000 00000001 0016e000 00000000 ... [ 7.960000] Call Trace: [ 7.960000] [<801041ec>] thread_saved_pc+0x2c/0x38 [ 7.960000] [<80104248>] get_wchan+0x48/0xac The disassembly of thread_saved_pc points to the following: 000006d0 <thread_saved_pc>: 6d0: 8c820208 lw v0,520(a0) 6d4: 3c030000 lui v1,0x0 6d8: 24630000 addiu v1,v1,0 6dc: 10430008 beq v0,v1,700 <thread_saved_pc+0x30> 6e0: 00000000 nop 6e4: 3c020000 lui v0,0x0 6e8: 8c43000c lw v1,12(v0) 6ec: 04620004 bltzl v1,700 <thread_saved_pc+0x30> 6f0: 00001021 move v0,zero 6f4: 8c840200 lw a0,512(a0) 6f8: 00031080 sll v0,v1,0x2 6fc: 7c44100a lwx v0,a0(v0) <------------ 700: 03e00008 jr ra 704: 00000000 nop If we specifically disable -mdsp/-mdspr2 for arch/mips/kernel/process.o, we get the following (non-crashing) assembly: 00000708 <thread_saved_pc>: 708: 8c820208 lw v0,520(a0) 70c: 3c030000 lui v1,0x0 710: 24630000 addiu v1,v1,0 714: 10430009 beq v0,v1,73c <thread_saved_pc+0x34> 718: 00000000 nop 71c: 3c020000 lui v0,0x0 720: 8c42000c lw v0,12(v0) 724: 04420005 bltzl v0,73c <thread_saved_pc+0x34> 728: 00001021 move v0,zero 72c: 8c830200 lw v1,512(a0) 730: 00021080 sll v0,v0,0x2 734: 00431021 addu v0,v0,v1 738: 8c420000 lw v0,0(v0) 73c: 03e00008 jr ra 740: 00000000 nop The specific line that leads a different assembly being produced is: unsigned long thread_saved_pc(struct task_struct *tsk) ... return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset]; <--- The problem here is that the compiler was given the right to use DSP instructions with the -mdsp / -mdspr2 command-line switches and performed some optimization for us and used DSP ASE instructions where we are not checking that the running CPU actually supports DSP ASE. This patch fixes the issue by partially reverting commit 32a7ede for arch/mips/kernel/Makefile in order to remove the -mdsp / -mdspr2 compiler command-line switches such that we are now guaranteed that the compiler will not optimize using DSP ASE reserved instructions. We also need to fixup the rddsp/wrdsp and m{t,h}{hi,lo}{0,1,2,3} macros in arch/mips/include/asm/mipsregs.h to tell the assembler that we are going to explicitely use DSP ASE reserved instructions. The comment in arch/mips/kernel/Makefile is also updated to reflect that. Signed-off-by: Florian Fainelli <[email protected]> Acked-by: Steven J. Hill <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Ralf Baechle <[email protected]>
2013-02-21Merge branch 'mips-next-3.9' of ↵Ralf Baechle1-186/+125
git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
2013-02-19MIPS: Probe for and report hardware virtualization support.David Daney1-0/+1
The presence of the MIPS Virtualization Application-Specific Extension is indicated by CP0_Config3[23]. Probe for this and report it in /proc/cpuinfo. Signed-off-by: David Daney <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4904/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: dsp: Simplify the DSP macros.Steven J. Hill1-201/+30
Simplify the DSP macros for vanilla (non-microMIPS) kernels and toolchains that do not support the DSP ASEs. Signed-off-by: Steven J. Hill <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4687/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: dsp: Support toolchains without DSP ASE and microMIPS.Steven J. Hill1-0/+89
Add macros to support the DSP ASE with microMIPS kernels when the toolchain does not have support. Signed-off-by: Steven J. Hill <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4686/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: dsp: Add assembler support for DSP ASEs.Steven J. Hill1-17/+36
Newer toolchains support the DSP and DSP Rev2 instructions. This patch performs a check for that support and adds compiler and assembler flags for only the files that need use those instructions. Signed-off-by: Steven J. Hill <[email protected]> Acked-by: Florian Fainelli <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4752/ Signed-off-by: John Crispin <[email protected]>
2013-02-17MIPS: Add support for the M14KEc core.Steven J. Hill1-0/+1
Signed-off-by: Steven J. Hill <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4682/ Signed-off-by: John Crispin <[email protected]>
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle1-199/+199
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <[email protected]>
2013-02-01MIPS: Whitespace cleanups and reformatting.Steven J. Hill1-11/+15
Signed-off-by: Steven J. Hill <[email protected]> Cc: [email protected] Cc: Steven J. Hill <[email protected]> Cc: Kevin Cernekee <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/4781/ Signed-off-by: Ralf Baechle <[email protected]>
2012-12-13MIPS: PMC-Sierra Yosemite: Remove support.Ralf Baechle1-8/+0
Nobody seems to be interested anymore and upstream also never had an ethernet driver. Signed-off-by: Ralf Baechle <[email protected]>
2012-12-12MIPS: Control huge tlb support via Kconfig symbol MIPS_HUGE_TLB_SUPPORTDavid Daney1-1/+1
We need Huge TLBs for HUGETLB_PAGE, or the soon to follow TRANSPARENT_HUGEPAGE. collect this information under a single Kconfig symbol. Signed-off-by: David Daney <[email protected]>
2012-10-11MIPS: Add detection of DSP ASE Revision 2.Steven J. Hill1-0/+1
[[email protected]: This patch really only detects the ASE and passes its existence on to userland via /proc/cpuinfo. The DSP ASE Rev 2. adds new resources but no resources that would need management by the kernel.] Signed-off-by: Steven J. Hill <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/4165/ Signed-off-by: Ralf Baechle <[email protected]>
2012-10-11MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt)Al Cooper1-0/+2
The PCI (Program Counter Interrupt) bit in the "cause" register is mandatory for MIPS32R2 cores, but has also been added to some R1 cores (BMIPS5000). This change adds a cpu feature bit to make it easier to check for and use this feature. Signed-off-by: Al Cooper <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/4106/ Signed-off-by: Ralf Baechle <[email protected]>
2012-09-28Merge branch 'ralf-3.7' of ↵Ralf Baechle1-0/+2
git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
2012-09-13MIPS: Add base architecture support for RI and XI.Steven J. Hill1-0/+1
Originally both Read Inhibit (RI) and Execute Inhibit (XI) were supported by the TLB only for a SmartMIPS core. The MIPSr3(TM) Architecture now defines an optional feature to implement these TLB bits separately. Support for one or both features can be checked by looking at the Config3.RXI bit. Signed-off-by: Steven J. Hill <[email protected]> Acked-by: David Daney <[email protected]>
2012-09-13MIPS: Add support for the 1074K core.Steven J. Hill1-0/+2
Signed-off-by: Steven J. Hill <[email protected]>
2011-12-07MIPS: BMIPS: Add set/clear CP0 macros for BMIPS operationsKevin Cernekee1-1/+8
Several BMIPS-specific CP0 registers are used for SMP boot and other operations. Signed-off-by: Kevin Cernekee <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/2956/ Signed-off-by: Ralf Baechle <[email protected]>
2011-10-24MIPS: Add accessor macros for 64-bit performance counter registers.David Daney1-0/+8
Signed-off-by: David Daney <[email protected]> To: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/2789/ Signed-off-by: Ralf Baechle <[email protected]>
2011-03-31Fix common misspellingsLucas De Marchi1-2/+2
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <[email protected]>
2010-10-29MIPS: Add BMIPS CP0 register definitionsKevin Cernekee1-0/+51
Signed-off-by: Kevin Cernekee <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Tested-by: Florian Fainelli <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/1708/ Signed-off-by: Ralf Baechle <[email protected]
2010-08-05MIPS: Define ST0_NMI in asm/mipsregs.hDavid Daney1-0/+1
This is used by the forthcoming OCTEON watchdog patch. Signed-off-by: David Daney <[email protected]> To: [email protected] To: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/1498/ Signed-off-by: Ralf Baechle <[email protected]>
2010-05-15 MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1Shane McDonald1-1/+8
In the FPU emulator code of the MIPS, the Cause bits of the FCSR register are not currently writeable by the ctc1 instruction. In odd corner cases, this can cause problems. For example, a case existed where a divide-by-zero exception was generated by the FPU, and the signal handler attempted to restore the FPU registers to their state before the exception occurred. In this particular setup, writing the old value to the FCSR register would cause another divide-by-zero exception to occur immediately. The solution is to change the ctc1 instruction emulator code to allow the Cause bits of the FCSR register to be writeable. This is the behaviour of the hardware that the code is emulating. This problem was found by Shane McDonald, but the credit for the fix goes to Kevin Kissell. In Kevin's words: I submit that the bug is indeed in that ctc_op: case of the emulator. The Cause bits (17:12) are supposed to be writable by that instruction, but the CTC1 emulation won't let them be updated by the instruction. I think that actually if you just completely removed lines 387-388 [...] things would work a good deal better. At least, it would be a more accurate emulation of the architecturally defined FPU. If I wanted to be really, really pedantic (which I sometimes do), I'd also protect the reserved bits that aren't necessarily writable. Signed-off-by: Shane McDonald <[email protected]> To: [email protected] To: [email protected] To: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/1205/ Signed-off-by: Ralf Baechle <[email protected]> ---
2010-02-27MIPS: Add accessor functions and bit definitions for c0_PageGrainDavid Daney1-0/+11
Signed-off-by: David Daney <[email protected]> To: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/950/ Signed-off-by: Ralf Baechle <[email protected]>
2010-02-27MIPS: Decode c0_config4 for large TLBs.David Daney1-0/+4
For processors that have more than 64 TLBs, we need to decode both config1 and config4 to determine the total number TLBs. Signed-off-by: David Daney <[email protected]> To: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/866/ Signed-off-by: Ralf Baechle <[email protected]>
2010-01-28MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQsDavid VomLehn1-0/+12
The MIPS processor is limited to 64 external interrupt sources. Using a greater number without IRQ sharing requires reading platform-specific registers. On such platforms, reading the IntCtl register to determine which interrupt corresponds to a timer interrupt will not work. On MIPSR2 systems there is a solution - the TI bit in the Cause register, specifically indicates that a timer interrupt has occured. This patch uses that bit to detect interrupts for MIPSR2 processors, which may be expected to work regardless of how the timer interrupt may be routed in the hardware. Signed-off-by: David VomLehn ([email protected]) To: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/804/ Signed-off-by: Ralf Baechle <[email protected]>
2009-06-17MIPS: Add hugetlbfs page defines.David Daney1-0/+16
Signed-off-by: David Daney <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2009-05-14MIPS: Fix sign-extension bug in 32-bit kernel on 32-bit hardware.Ralf Baechle1-4/+4
Probably nobody does arithmetic on cp0 register values so this has never bitten. Signed-off-by: Ralf Baechle <[email protected]>
2009-05-14MIPS: Cavium: Add support for 8k and 32k page sizes.Ralf Baechle1-0/+11
Beyond the requirements of the architecture standard Cavium also supports 8k and 32k pages. Signed-off-by: Ralf Baechle <[email protected]> Acked-by: David Daney <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.