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2013-04-08spi/bcm63xx: remove unused speed_hz variableJonas Gorski1-1/+0
speed_hz is a write only member, so we can safely remove it and its generation. Also fixes the missing clk_put after getting the periph clock. Signed-off-by: Jonas Gorski <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2013-03-19MIPS: BCM63XX: Make nvram checksum failure non fatalJonas Gorski1-3/+1
Some vendors modify the nvram layout moving the checksum to a different place or dropping entirely, so reduce the checksum failure to a warning. Reported-by: Álvaro Fernández Rojas <[email protected]> Signed-off-by: Jonas Gorski <[email protected]> Cc: [email protected] Cc: John Crispin <[email protected]> Cc: Maxime Bizon <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: Kevin Cernekee <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle5-16/+16
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <[email protected]>
2012-12-13Merge branch 'mips-next' of http://dev.phrozen.org/githttp/mips-next into ↵Ralf Baechle4-24/+78
mips-for-linux-next
2012-12-13MIPS: PMC-Sierra Yosemite: Remove support.Ralf Baechle1-1/+0
Nobody seems to be interested anymore and upstream also never had an ethernet driver. Signed-off-by: Ralf Baechle <[email protected]>
2012-11-20MIPS: BCM63XX: fix BCM6345 clocks bitsFlorian Fainelli1-7/+12
BCM6345 has an intermediate 16-bits wide test control register between the peripheral identifier register, and its clock control register is only 16-bits wide contrary to other platforms where it is 32-bits wide. By shifting all clocks bits by 16-bits to the left we ensure they get written to the proper clock control register, without adding specific BCM6345 handling in the clock code. Signed-off-by: Florian Fainelli <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4555/ Signed-off-by: John Crispin <[email protected]>
2012-11-09MIPS: BCM63XX: move nvram functions into their own fileJonas Gorski2-17/+35
Refactor nvram related functions into its own unit for easier expansion and exposure of the values to other drivers. Signed-off-by: Jonas Gorski <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4516 Signed-off-by: John Crispin <[email protected]>
2012-11-09MIPS: BCM63XX: add core reset helperJonas Gorski1-0/+21
Add a reset helper for resetting the different cores. Signed-off-by: Jonas Gorski <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4455 Signed-off-by: John Crispin <[email protected]>
2012-11-09MIPS: BCM63XX: add softreset register description for BCM6358Jonas Gorski1-0/+10
The softreset register description for BCM6358 was missing, so add it. Signed-off-by: Jonas Gorski <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4454 Signed-off-by: John Crispin <[email protected]>
2012-10-11MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.Ralf Baechle1-0/+1
Most supported systems currently hardwire cpu_has_dsp to 0, so we also can disable support for cpu_has_dsp2 resulting in a slightly smaller kernel. Signed-off-by: Ralf Baechle <[email protected]>
2012-10-09Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds5-12/+309
Pull MIPS update from Ralf Baechle: "This is the MIPS update for 3.7. A fair chunk of them are platform updates to the Cavium Octeon SOC (which involves machine generated header files of considerable size), Atheros ATH79xx, RMI aka Netlogic aka Broadcom XLP, Broadcom BCM63xx platforms. Support for the commercial MIPS simulator MIPSsim has been removed as MIPS Technologies is shifting away from this product and Qemu is offering various more powerful platforms. The generic MIPS code can now also probe for no-execute / write-only TLB features implemented without the full SmartMIPS extension as permitted by the latest MIPS processor architecture. Lots of small changes to generic code." * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (78 commits) MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x MIPS: BCM63XX: Properly handle mac address octet overflow MIPS: Kconfig: Avoid build errors by hiding USE_OF from the user. MIPS: Replace `-' in defconfig filename wth `_' for consistency. MIPS: Wire kcmp syscall. MIPS: MIPSsim: Remove the MIPSsim platform. MIPS: NOTIFY_RESUME is not needed in TIF masks MIPS: Merge the identical "return from syscall" per-ABI code MIPS: Unobfuscate _TIF..._MASK MIPS: Prevent hitting do_notify_resume() with !user_mode(regs). MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'. MIPS: Add base architecture support for RI and XI. MIPS: Optimise TLB handlers for MIPS32/64 R2 cores. MIPS: uasm: Add INS and EXT instructions. MIPS: Avoid pipeline stalls on some MIPS32R2 cores. MIPS: Make VPE count to be one-based. MIPS: Add new end of interrupt functionality for GIC. MIPS: Add EIC support for GIC. MIPS: Code clean-ups for the GIC. ...
2012-10-05Merge branch 'master' of git://dev.phrozen.org/mips-next into ↵Ralf Baechle2-4/+5
mips-for-linux-next
2012-10-02UAPI: (Scripted) Convert #include "..." to #include <path/...> in kernel ↵David Howells1-1/+1
system headers Convert #include "..." to #include <path/...> in kernel system headers. Signed-off-by: David Howells <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Acked-by: Thomas Gleixner <[email protected]> Acked-by: Paul E. McKenney <[email protected]> Acked-by: Dave Jones <[email protected]>
2012-09-27Merge branch 'broadcom' of git://dev.phrozen.org/mips-next into ↵Ralf Baechle5-8/+304
mips-for-linux-next
2012-08-30MIPS: BCM63XX: Create platform_device for USBDKevin Cernekee2-0/+22
Signed-off-by: Kevin Cernekee <[email protected]> Reviewed-by: Jonas Gorski <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4111/ Signed-off-by: John Crispin <[email protected]>
2012-08-30MIPS: BCM63XX: Add register and IRQ definitions for USB 2.0 deviceKevin Cernekee2-1/+221
Signed-off-by: Kevin Cernekee <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4084/ Signed-off-by: John Crispin <[email protected]>
2012-08-30MIPS: BCM63XX: Fix USB IRQ definitions for 6328Kevin Cernekee1-2/+2
OHCI/EHCI are in the high (second) word. Not currently used by any driver. Signed-off-by: Kevin Cernekee <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4026/ Signed-off-by: John Crispin <[email protected]>
2012-08-30MIPS: BCM63XX: Add register definitions for USBD dependenciesKevin Cernekee2-3/+11
The USB 2.0 device depends on some functionality in other blocks, such as GPIO and USBH. Add those register definitions here. Signed-off-by: Kevin Cernekee <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4025/ Signed-off-by: John Crispin <[email protected]>
2012-08-30MIPS: BCM63XX: Add new IUDMA definitions needed for USBDKevin Cernekee2-2/+14
Signed-off-by: Kevin Cernekee <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4083/ Signed-off-by: John Crispin <[email protected]>
2012-08-30MIPS: BCM63XX: Move DMA descriptor definition into common header fileKevin Cernekee1-0/+34
The "IUDMA" engine used by bcm63xx_enet is also used by other blocks, such as the USB 2.0 device. Move the definitions into a common file so that they do not need to be duplicated in each driver. Signed-off-by: Kevin Cernekee <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4082/ Signed-off-by: John Crispin <[email protected]>
2012-08-24MIPS: BCM63XX: remove bogus ENETSW_TXDMA interrupts from BCM6328Jonas Gorski1-4/+4
These were erroneously copied from BCM6368. BCM6328 does not expose the ENETSW_TXDMA interrupts, and BCM_6328_HIGH_IRQ_BASE + 7 is actually used for the second UART. Signed-off-by: Jonas Gorski <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4090/ Signed-off-by: John Crispin <[email protected]>
2012-08-24MIPS: BCM63XX: add external irq support for BCM6345Maxime Bizon1-0/+1
Add the missing definitions for BCM6345. Signed-off-by: Maxime Bizon <[email protected]> Signed-off-by: Jonas Gorski <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/4091/ Signed-off-by: John Crispin <[email protected]>
2012-08-17MIPS: BCM63xx: Fix SPI message control register handling for BCM6338/6348.Florian Fainelli2-3/+12
BCM6338 and BCM6348 have a message control register width of 8 bits, instead of 16-bits like what the SPI driver assumes right now. Also the SPI message type shift value of 14 is actually 6 for these SoCs. This resulted in transmit FIFO corruption because we were writing 16-bits to an 8-bits wide register, thus spanning on the first byte of the transmit FIFO, which had already been filed in bcm63xx_spi_fill_txrx_fifo(). Fix this by passing the message control register width and message type shift through platform data back to the SPI driver so that it can use it properly. Signed-off-by: Florian Fainelli <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/3983/ Signed-off-by: Ralf Baechle <[email protected]>
2012-07-24MIPS: BCM63XX: Add PCIe Support for BCM6328Jonas Gorski3-0/+69
Add support for the PCIe port found on BCM6328. Signed-off-by: Jonas Gorski <[email protected]> Cc: [email protected] Cc: Maxime Bizon <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: Kevin Cernekee <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/3956/ Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2012-07-24MIPS: BCM63XX: Add basic BCM6328 supportJonas Gorski5-1/+169
This includes CPU speed, memory size detection and working UART, but lacking the appropriate drivers, no support for attached flash. Signed-off-by: Jonas Gorski <[email protected]> Cc: [email protected] Cc: Maxime Bizon <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: Kevin Cernekee <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/3951/ Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2012-07-24MIPS: BCM63XX: Add flash type detectionJonas Gorski2-0/+15
On BCM6358 and BCM6368 the attached flash type is exposed through a bootstrapping register. Use it for auto detecting the flash type on those and default to parallel flash for earlier SoCs. Signed-off-by: Jonas Gorski <[email protected]> Cc: [email protected] Cc: Maxime Bizon <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: Kevin Cernekee <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/3954/ Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2012-07-24MIPS: BCM63XX: Move flash registration out of board_bcm963xx.cJonas Gorski1-0/+6
board_bcm963xx.c is already large enough. Signed-off-by: Jonas Gorski <[email protected]> Cc: [email protected] Cc: Maxime Bizon <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: Kevin Cernekee <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/3952/ Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2012-07-24MIPS: BCM63XX: add RNG peripheral definitionsFlorian Fainelli2-0/+23
Signed-off-by: Florian Fainelli <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/3326/ Signed-off-by: Ralf Baechle <[email protected]>
2012-07-23MIPS: BCM63xx: Add stub to register the SPI platform driverFlorian Fainelli1-0/+89
This patch adds the necessary stub to register the SPI platform driver. Since the registers are shuffled between the 4 BCM63xx CPUs supported by this SPI driver we also need to generate the internal register layout and export this layout for the driver to use it properly. Signed-off-by: Florian Fainelli <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/3321/ Signed-off-by: Ralf Baechle <[email protected]>
2012-07-23MIPS: BCM63xx: Define internal registers offsets of the SPI controllerFlorian Fainelli1-0/+119
BCM6338, BCM6348, BCM6358 and BCM6368 basically use the same SPI controller though the internal registers are shuffled, which still allows a common driver to drive that IP block. Signed-off-by: Florian Fainelli <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/3318/ Signed-off-by: Ralf Baechle <[email protected]>
2012-07-23MIPS: BCM63xx: Remove SPI2 registerFlorian Fainelli1-9/+1
This register was introduced with the support of the BCM6368 CPU in the idea that its internal layout was different from the other CPUs SPI controller. The controller is actually the same as the one present on BCM6358 so we can remove this register and use the usual SPI register instead. Signed-off-by: Florian Fainelli <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/3316/ Signed-off-by: Ralf Baechle <[email protected]>
2012-07-23MIPS: BCM63xx: Define SPI register sizes.Florian Fainelli1-0/+4
There are two distinct sizes for the SPI register depending on the SoC generation (6338 & 6348 vs 6358 & 6368). Signed-off-by: Florian Fainelli <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/3314/ Signed-off-by: Ralf Baechle <[email protected]>
2012-07-23MIPS: BCM63xx: Define BCM6358 SPI base addressFlorian Fainelli1-1/+1
Signed-off-by: Florian Fainelli <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/3315/ Signed-off-by: Ralf Baechle <[email protected]>
2012-07-23MIPS: BCM63xx: Add IRQ_SPI and CPU specific SPI IRQ valuesFlorian Fainelli1-0/+7
Signed-off-by: Florian Fainelli <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/3320/ Signed-off-by: Ralf Baechle <[email protected]>
2012-07-23MIPS: BCM63XX: Be consistent in clock bits enable namingFlorian Fainelli1-18/+18
Remove the _CLK suffix from the BCM6368 clock bits definitions to be consistent with what is already present. Signed-off-by: Florian Fainelli <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/3312/ Signed-off-by: Ralf Baechle <[email protected]>
2012-07-19MIPS: BCM63XX: Fix BCM6368 IPSec clock bitFlorian Fainelli1-1/+1
The IPsec clock bit is 18 and not 17. Signed-off-by: Florian Fainelli <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/3323/ Signed-off-by: Ralf Baechle <[email protected]>
2012-05-15MIPS: BCM63XX: Add missing include for bcm63xx_gpio.hJonas Gorski1-0/+1
bcm63xx_gpio.h uses macros defined in bcm63xx_cpu.h without including it, leading to the following build failure: CC [M] drivers/mmc/core/cd-gpio.o In file included from arch/mips/include/asm/mach-bcm63xx/gpio.h:4:0, from arch/mips/include/asm/gpio.h:4, from include/linux/gpio.h:30, from drivers/mmc/core/cd-gpio.c:12: arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h: In function 'bcm63xx_gpio_count': arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:10:2: error: implicit declaration of function 'bcm63xx_get_cpu_id' arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:11:7: error: 'BCM6358_CPU_ID' undeclared (first use in this function) arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:11:7: note: each undeclared identifier is reported only once for each function it appears in arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:13:7: error: 'BCM6338_CPU_ID' undeclared (first use in this function) arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:15:7: error: 'BCM6345_CPU_ID' undeclared (first use in this function) arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:17:7: error: 'BCM6368_CPU_ID' undeclared (first use in this function) arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:19:7: error: 'BCM6348_CPU_ID' undeclared (first use in this function) make[7]: *** [drivers/mmc/core/cd-gpio.o] Error 1 Signed-off-by: Jonas Gorski <[email protected]> Cc: [email protected] Cc: [email protected] Cc: Maxime Bizon <[email protected]> Cc: Florian Fainelli <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2012-01-14Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds7-235/+658
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (119 commits) MIPS: Delete unused function add_temporary_entry. MIPS: Set default pci cache line size. MIPS: Flush huge TLB MIPS: Octeon: Remove SYS_SUPPORTS_HIGHMEM. MIPS: Octeon: Add support for OCTEON II PCIe MIPS: Octeon: Update PCI Latency timer and enable more error reporting. MIPS: Alchemy: Update cpu-feature-overrides MIPS: Alchemy: db1200: Improve PB1200 detection. MIPS: Alchemy: merge Au1000 and Au1300-style IRQ controller code. MIPS: Alchemy: chain IRQ controllers to MIPS IRQ controller MIPS: Alchemy: irq: register pm at irq init time MIPS: Alchemy: Touchscreen support on DB1100 MIPS: Alchemy: Hook up IrDA on DB1000/DB1100 net/irda: convert au1k_ir to platform driver. MIPS: Alchemy: remove unused board headers MTD: nand: make au1550nd.c a platform_driver MIPS: Netlogic: Mark Netlogic chips as SMT capable MIPS: Netlogic: Add support for XLP 3XX cores MIPS: Netlogic: Merge some of XLR/XLP wakup code MIPS: Netlogic: Add default XLP config. ... Fix up trivial conflicts in arch/mips/kernel/{perf_event_mipsxx.c, traps.c} and drivers/tty/serial/Makefile
2012-01-09MIPS: BCM63XX: bcm963xx_tag.h: make crc fields integersJonas Gorski1-6/+5
All CRC32 fields are 32 bit integers, so define them as such to prevent unnecessary casts if we want to use them. Signed-off-by: Jonas Gorski <[email protected]> Signed-off-by: David Woodhouse <[email protected]>
2011-12-07MIPS: BCM63xx: Fix GPIO set/get for BCM6345Florian Fainelli1-0/+1
On BCM6345, the register offsets for the set/get GPIO registers is wrong. Use the same logic as the one present in arch/mips/bcm63xx/irq.c to define the correct gpio_out_low_reg value when support for BCM6345 is compiled in. Signed-off-by: Florian Fainelli <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/3010/ Signed-off-by: Ralf Baechle <[email protected]>
2011-12-07MIPS: BCM63xx: Remove BCM6345 hacks to read base boot addressFlorian Fainelli1-1/+1
Though BCM6345 does not technically have the same MPI register layout than the other SoCs, reading the chip-select registers is done the same way, and particularly for chip-select 0, which is the boot flash. Signed-off-by: Florian Fainelli <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/3009/ Signed-off-by: Ralf Baechle <[email protected]>
2011-12-07MIPS: BCM63xx: Fix SDRAM size computation for BCM6345Florian Fainelli1-0/+2
Instead of hardcoding the amount of available RAM, read the number of effective multiples of 8MB from SDRAM_MBASE_REG. Signed-off-by: Florian Fainelli <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/3008/ Signed-off-by: Ralf Baechle <[email protected]>
2011-12-07MIPS: BCM63XX: Add support for bcm6368 CPU.Maxime Bizon4-2/+212
Signed-off-by: Maxime Bizon <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/2892/ Signed-off-by: Ralf Baechle <[email protected]>
2011-12-07MIPS: BCM63XX: Add external irq support for non 6348 CPUs.Maxime Bizon1-9/+22
Signed-off-by: Maxime Bizon <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/2899/ Signed-off-by: Ralf Baechle <[email protected]>
2011-12-07MIPS: BCM63XX: Introduce bcm_readq & bcm_writeq.Maxime Bizon1-0/+2
Needed for upcoming 6368 CPU support. [[email protected]: Changed function names as per Sergei's comments.] Signed-off-by: Maxime Bizon <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/2896/ Signed-off-by: Ralf Baechle <[email protected]>
2011-12-07MIPS: BCM63XX: Prepare irq code to handle different external irq hardware ↵Maxime Bizon2-7/+12
implementation. External irq only works for 6348, change code to prepare support of other CPUs. Signed-off-by: Maxime Bizon <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/2895/ Signed-off-by: Ralf Baechle <[email protected]>
2011-12-07MIPS: BCM63XX: Change irq code to prepare for per-cpu peculiarity.Maxime Bizon1-2/+8
No functionnal change is introduced by this patch. Signed-off-by: Maxime Bizon <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/2894/ Signed-off-by: Ralf Baechle <[email protected]>
2011-12-07MIPS: BCM63XX: Add more register sets & missing register definitions.Maxime Bizon2-2/+261
Needed for upcoming 6368 CPU support. Signed-off-by: Maxime Bizon <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/2893/ Signed-off-by: Ralf Baechle <[email protected]>
2011-12-07MIPS: BCM63XX: Cleanup cpu registers.Maxime Bizon1-212/+99
Use preprocessor when possible to avoid duplicated and error-prone code. Signed-off-by: Maxime Bizon <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/2897/ Signed-off-by: Ralf Baechle <[email protected]>
2011-12-07MIPS: BCM63XX: Hook up plat_ioremap to intercept soc registers remapping.Maxime Bizon1-0/+38
Internal SOC registers can be directly accessed, no need to waste a TLB entry. Signed-off-by: Maxime Bizon <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/2890/ Signed-off-by: Ralf Baechle <[email protected]>
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