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Based on 2 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 4122 file(s).
Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Enrico Weigelt <[email protected]>
Reviewed-by: Kate Stewart <[email protected]>
Reviewed-by: Allison Randal <[email protected]>
Cc: [email protected]
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Now that we've gotten rid of clk_readl() we can remove io.h from the
clk-provider header and push out the io.h include to any code that isn't
already including the io.h header but using things like readl/writel,
etc.
Found with this grep:
git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \
xargs git grep -l \
-e '\<__iowrite32_copy\>' --or \
-e '\<__ioread32_copy\>' --or \
-e '\<__iowrite64_copy\>' --or \
-e '\<ioremap_page_range\>' --or \
-e '\<ioremap_huge_init\>' --or \
-e '\<arch_ioremap_pud_supported\>' --or \
-e '\<arch_ioremap_pmd_supported\>' --or \
-e '\<devm_ioport_map\>' --or \
-e '\<devm_ioport_unmap\>' --or \
-e '\<IOMEM_ERR_PTR\>' --or \
-e '\<devm_ioremap\>' --or \
-e '\<devm_ioremap_nocache\>' --or \
-e '\<devm_ioremap_wc\>' --or \
-e '\<devm_iounmap\>' --or \
-e '\<devm_ioremap_release\>' --or \
-e '\<devm_memremap\>' --or \
-e '\<devm_memunmap\>' --or \
-e '\<__devm_memremap_pages\>' --or \
-e '\<pci_remap_cfgspace\>' --or \
-e '\<arch_has_dev_port\>' --or \
-e '\<arch_phys_wc_add\>' --or \
-e '\<arch_phys_wc_del\>' --or \
-e '\<memremap\>' --or \
-e '\<memunmap\>' --or \
-e '\<arch_io_reserve_memtype_wc\>' --or \
-e '\<arch_io_free_memtype_wc\>' --or \
-e '\<__io_aw\>' --or \
-e '\<__io_pbw\>' --or \
-e '\<__io_paw\>' --or \
-e '\<__io_pbr\>' --or \
-e '\<__io_par\>' --or \
-e '\<__raw_readb\>' --or \
-e '\<__raw_readw\>' --or \
-e '\<__raw_readl\>' --or \
-e '\<__raw_readq\>' --or \
-e '\<__raw_writeb\>' --or \
-e '\<__raw_writew\>' --or \
-e '\<__raw_writel\>' --or \
-e '\<__raw_writeq\>' --or \
-e '\<readb\>' --or \
-e '\<readw\>' --or \
-e '\<readl\>' --or \
-e '\<readq\>' --or \
-e '\<writeb\>' --or \
-e '\<writew\>' --or \
-e '\<writel\>' --or \
-e '\<writeq\>' --or \
-e '\<readb_relaxed\>' --or \
-e '\<readw_relaxed\>' --or \
-e '\<readl_relaxed\>' --or \
-e '\<readq_relaxed\>' --or \
-e '\<writeb_relaxed\>' --or \
-e '\<writew_relaxed\>' --or \
-e '\<writel_relaxed\>' --or \
-e '\<writeq_relaxed\>' --or \
-e '\<readsb\>' --or \
-e '\<readsw\>' --or \
-e '\<readsl\>' --or \
-e '\<readsq\>' --or \
-e '\<writesb\>' --or \
-e '\<writesw\>' --or \
-e '\<writesl\>' --or \
-e '\<writesq\>' --or \
-e '\<inb\>' --or \
-e '\<inw\>' --or \
-e '\<inl\>' --or \
-e '\<outb\>' --or \
-e '\<outw\>' --or \
-e '\<outl\>' --or \
-e '\<inb_p\>' --or \
-e '\<inw_p\>' --or \
-e '\<inl_p\>' --or \
-e '\<outb_p\>' --or \
-e '\<outw_p\>' --or \
-e '\<outl_p\>' --or \
-e '\<insb\>' --or \
-e '\<insw\>' --or \
-e '\<insl\>' --or \
-e '\<outsb\>' --or \
-e '\<outsw\>' --or \
-e '\<outsl\>' --or \
-e '\<insb_p\>' --or \
-e '\<insw_p\>' --or \
-e '\<insl_p\>' --or \
-e '\<outsb_p\>' --or \
-e '\<outsw_p\>' --or \
-e '\<outsl_p\>' --or \
-e '\<ioread8\>' --or \
-e '\<ioread16\>' --or \
-e '\<ioread32\>' --or \
-e '\<ioread64\>' --or \
-e '\<iowrite8\>' --or \
-e '\<iowrite16\>' --or \
-e '\<iowrite32\>' --or \
-e '\<iowrite64\>' --or \
-e '\<ioread16be\>' --or \
-e '\<ioread32be\>' --or \
-e '\<ioread64be\>' --or \
-e '\<iowrite16be\>' --or \
-e '\<iowrite32be\>' --or \
-e '\<iowrite64be\>' --or \
-e '\<ioread8_rep\>' --or \
-e '\<ioread16_rep\>' --or \
-e '\<ioread32_rep\>' --or \
-e '\<ioread64_rep\>' --or \
-e '\<iowrite8_rep\>' --or \
-e '\<iowrite16_rep\>' --or \
-e '\<iowrite32_rep\>' --or \
-e '\<iowrite64_rep\>' --or \
-e '\<__io_virt\>' --or \
-e '\<pci_iounmap\>' --or \
-e '\<virt_to_phys\>' --or \
-e '\<phys_to_virt\>' --or \
-e '\<ioremap_uc\>' --or \
-e '\<ioremap\>' --or \
-e '\<__ioremap\>' --or \
-e '\<iounmap\>' --or \
-e '\<ioremap\>' --or \
-e '\<ioremap_nocache\>' --or \
-e '\<ioremap_uc\>' --or \
-e '\<ioremap_wc\>' --or \
-e '\<ioremap_wc\>' --or \
-e '\<ioremap_wt\>' --or \
-e '\<ioport_map\>' --or \
-e '\<ioport_unmap\>' --or \
-e '\<ioport_map\>' --or \
-e '\<ioport_unmap\>' --or \
-e '\<xlate_dev_kmem_ptr\>' --or \
-e '\<xlate_dev_mem_ptr\>' --or \
-e '\<unxlate_dev_mem_ptr\>' --or \
-e '\<virt_to_bus\>' --or \
-e '\<bus_to_virt\>' --or \
-e '\<memset_io\>' --or \
-e '\<memcpy_fromio\>' --or \
-e '\<memcpy_toio\>'
I also reordered a couple includes when they weren't alphabetical and
removed clk.h from kona, replacing it with clk-provider.h because
that driver doesn't use clk consumer APIs.
Acked-by: Geert Uytterhoeven <[email protected]>
Cc: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Acked-by: Tero Kristo <[email protected]>
Acked-by: Sekhar Nori <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Acked-by: Mark Brown <[email protected]>
Cc: Chris Zankel <[email protected]>
Acked-by: Max Filippov <[email protected]>
Acked-by: John Crispin <[email protected]>
Acked-by: Heiko Stuebner <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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With the target now being fully OF based, we can drop the legacy clock
registration code. All clocks are now probed via devicetree.
Signed-off-by: John Crispin <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Felix Fietkau <[email protected]>
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With the target now being fully OF based, we can drop the legacy mach
files. Boards can now boot fully of devicetree files.
Signed-off-by: John Crispin <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Felix Fietkau <[email protected]>
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On AR934x, the MDIO reference clock can be configured to a fixed 100 MHz
clock. If that feature is not used, it defaults to the main reference
clock, like on all other SoC.
Signed-off-by: Felix Fietkau <[email protected]>
Signed-off-by: John Crispin <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
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Use the same functions as the legacy code
Signed-off-by: Felix Fietkau <[email protected]>
Signed-off-by: John Crispin <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
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It can be autodetected for many SoCs using the strapping options.
If the clock is specified in DT, the autodetected value is ignored
Signed-off-by: Felix Fietkau <[email protected]>
Signed-off-by: John Crispin <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
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Preparation for passing the mapped base via DT
Signed-off-by: Felix Fietkau <[email protected]>
Signed-off-by: John Crispin <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
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Preparation for reusing functions for DT
Signed-off-by: Felix Fietkau <[email protected]>
Signed-off-by: John Crispin <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
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Preparation for transitioning the legacy clock setup code over
to OF.
Signed-off-by: Felix Fietkau <[email protected]>
Signed-off-by: John Crispin <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
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This patch adds support for 2 new types of QCA silicon. TP9343 is
essentially the same as the QCA956X but is licensed by TPLink.
Signed-off-by: Weijie Gao <[email protected]>
Signed-off-by: Matthias Schiffer <[email protected]>
Signed-off-by: John Crispin <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/19911/
Cc: James Hogan <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: [email protected]
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Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.
Signed-off-by: Rob Herring <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/16783/
Signed-off-by: Ralf Baechle <[email protected]>
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Historically a lot of these existed because we did not have
a distinction between what was modular code and what was providing
support to modules via EXPORT_SYMBOL and friends. That changed
when we forked out support for the latter into the export.h file.
This means we should be able to reduce the usage of module.h
in code that is obj-y Makefile or bool Kconfig. In the case of
some code where it is modular, we can extend that to also include
files that are building basic support functionality but not related
to loading or registering the final module; such files also have
no need whatsoever for module.h
The advantage in removing such instances is that module.h itself
sources about 15 other headers; adding significantly to what we feed
cpp, and it can obscure what headers we are effectively using.
Since module.h might have been the implicit source for init.h
(for __init) and for export.h (for EXPORT_SYMBOL) we consider each
instance for the presence of either and replace/add as needed.
Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
Build coverage of all the mips defconfigs revealed the module.h
header was masking a couple of implicit include instances, so
we add the appropriate headers there.
Signed-off-by: Paul Gortmaker <[email protected]>
Cc: David Daney <[email protected]>
Cc: John Crispin <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: "Steven J. Hill" <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/15131/
[[email protected]: Preserve sort order where it already exists]
Signed-off-by: James Hogan <[email protected]>
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Free memory mapping, if ath79_clocks_init_dt_ng is not successful.
Signed-off-by: Arvind Yadav <[email protected]>
Fixes: 3bdf1071ba7d ("MIPS: ath79: update devicetree clock support for AR9132")
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/14915/
Signed-off-by: Ralf Baechle <[email protected]>
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'clk_register_fixed_rate()' returns an error pointer in case of error, not
NULL. So test it with IS_ERR.
Signed-off-by: Christophe JAILLET <[email protected]>
Acked-by: Aban Bedel <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/14464/
Signed-off-by: Ralf Baechle <[email protected]>
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clk_register_fixed_factor returns an ERR_PTR in case of an error and
should have an IS_ERR check instead of a null check.
The Coccinelle semantic patch used to find this issue is as follows:
@@
expression e;
statement S;
@@
*e = clk_register_fixed_factor(...);
if (!e) S
Signed-off-by: Amitoj Kaur Chawla <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/13894/
Signed-off-by: Ralf Baechle <[email protected]>
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This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate
CLK_IS_ROOT", 2016-02-02) so remove it.
Signed-off-by: Stephen Boyd <[email protected]>
Cc: Antony Pavlov <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/13133/
Signed-off-by: Ralf Baechle <[email protected]>
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Signed-off-by: Antony Pavlov <[email protected]>
Cc: Gabor Juhos <[email protected]>
Cc: Alban Bedel <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/12879/
Signed-off-by: Ralf Baechle <[email protected]>
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Current ath79 clock.c code does not read reference clock and
pll setup from devicetree. E.g. you can set any clock rate value
in board DTS but it will have no effect on the real clk calculation.
This patch fixes some AR9132 devicetree clock support defects:
* clk initialization function ath79_clocks_init_dt_ng()
is introduced; it actually gets pll block base register
address and reference clock from devicetree;
* pll register parsing code is moved to the separate
ar724x_clk_init() function; this function
can be called from platform code or from devicetree code.
Also mips_hpt_frequency value is set from dt, so the appropriate
clock parameter is added to the cpu@0 devicetree node.
The same approach can be used for adding AR9331 devicetree support.
Signed-off-by: Antony Pavlov <[email protected]>
Cc: Gabor Juhos <[email protected]>
Cc: Alban Bedel <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/12876/
Signed-off-by: Ralf Baechle <[email protected]>
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The include/dt-bindings/clock/ath79-clk.h header file
is introduced so we can use symbolic identifiers for SoC clocks.
Signed-off-by: Antony Pavlov <[email protected]>
Cc: Gabor Juhos <[email protected]>
Cc: Alban Bedel <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/12875/
Signed-off-by: Ralf Baechle <[email protected]>
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The reference clock on ar913x is at 40MHz and not 5MHz. The current
implementation use the wrong reference rate because it doesn't take
the PLL divider in account. But if we fix the code to use the divider
it becomes identical with the implementation for ar724x, so just drop
the broken ar913x implementation.
Signed-off-by: Alban Bedel <[email protected]>
Tested-by: Antony Pavlov <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/12871/
Signed-off-by: Ralf Baechle <[email protected]>
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According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
input clock as the REF_CLK instead of 5MHz.
The correct CPU PLL calculation procedure is as follows:
CPU_PLL = (FB * REF_CLK) / REF_DIV / 2.
This patch is compatible with the current calculation procedure with
default FB and REF_DIV values.
Tested on AR7240, AR7241 and AR7242.
Signed-off-by: Weijie Gao <[email protected]>
Signed-off-by: Alban Bedel <[email protected]> (Fixed the commit log message)
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/12870/
Signed-off-by: Ralf Baechle <[email protected]>
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Allow using the SoC clocks in the device tree.
Signed-off-by: Alban Bedel <[email protected]>
Cc: [email protected]
Signed-off-by: Ralf Baechle <[email protected]>
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Make the code simpler and open the way for device tree clocks.
[[email protected]: Resolved conflict with 2a552da6 (MIPS/IRQCHIP: Move
irq_chip from arch/mips to drivers/irqchip.)]
Signed-off-by: Alban Bedel <[email protected]>
Cc: [email protected]
Cc: Andrew Bresticker <[email protected]>
Cc: Qais Yousef <[email protected]>
Cc: Wolfram Sang <[email protected]>
Cc: Sergey Ryazanov <[email protected]>
Cc: Gabor Juhos <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9774/
Signed-off-by: Ralf Baechle <[email protected]>
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This register is named PLL_FB and is not a divider but a multiplier.
To make things less confusing rename the ARxxxx_PLL_DIV_SHIFT and
ARxxxx_PLL_DIV_MASK macros to ARxxxx_PLL_FB_SHIFT and
ARxxxx_PLL_FB_MASK.
Signed-off-by: Alban Bedel <[email protected]>
Cc: [email protected]
Cc: Andrew Bresticker <[email protected]>
Cc: Qais Yousef <[email protected]>
Cc: Wolfram Sang <[email protected]>
Cc: Sergey Ryazanov <[email protected]>
Cc: Gabor Juhos <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9772/
Signed-off-by: Ralf Baechle <[email protected]>
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The ath79 code uses static clock devices and
provides its own clk_{get,put} implementations.
Change the code to use dynamically allocated
clock devices and register the clocks within
the clkdev framework.
Additionally, remove the local clk_{get,put}
implementation. The clkdev framework has a
common implementation of those.
Also move the call of ath79_clock_init() from
plat_mem_init() to plat_time_init(). Otherwise
it would not be possible to use memory allocation
functions from ath79clock_init() becasuse the
memory subsystem is not yet initialized when
plat_mem_init() runs.
Signed-off-by: Gabor Juhos <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/5780/
Signed-off-by: Ralf Baechle <[email protected]>
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Use local variables for ref, cpu, ddr and ahb
rates in SoC specific clock init functions.
The patch has no functional changes, it is
an interim change in preparation of the next
patch.
Signed-off-by: Gabor Juhos <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/5781/
Signed-off-by: Ralf Baechle <[email protected]>
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Instead of accessing the rate field of the static
clock devices directly, use the recently introduced
helper function to get the rate of the basic clocks.
The static ath79_{ahb,cpu,ddr,ref}_clk variables
will be removed by a subsequent patch. The actual
change is in preparation of that.
Also move the clock frequency printing code into
the plat_time_init function. We are getting the
cpu clock rate there already so we can save an
extra call of the helper.
Signed-off-by: Gabor Juhos <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/5782/
Signed-off-by: Ralf Baechle <[email protected]>
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The ath79 platform uses similar code to get the
rate of various clocks during init. Separate the
similar code into a new helper function and use
that to avoid code duplication.
Signed-off-by: Gabor Juhos <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/5778/
Signed-off-by: Ralf Baechle <[email protected]>
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The reference clock rate is passed in the first
argument of the function. Use that instead of the
rate of the global ath79_ref_clk variable.
Signed-off-by: Gabor Juhos <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/5779/
Signed-off-by: Ralf Baechle <[email protected]>
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The watchdog device on the AR933x is connected to
the AHB clock, however the current code uses the
reference clock. Due to the wrong rate, the watchdog
driver can't calculate correct register values for
a given timeout value and the watchdog unexpectedly
restarts the system.
The code uses the wrong value since the initial
commit 04225e1d227c8e68d685936ecf42ac175fec0e54
(MIPS: ath79: add AR933X specific clock init)
The patch fixes the code to use the correct clock
rate to avoid the problem.
Cc: [email protected]
Signed-off-by: Felix Fietkau <[email protected]>
Signed-off-by: Gabor Juhos <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/5777/
Signed-off-by: Ralf Baechle <[email protected]>
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git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
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The patch adds code to get various clock frequencies
from the PLLs used in the QCA955x SoCs.
Cc: Rodriguez, Luis <[email protected]>
Cc: Giori, Kathy <[email protected]>
Cc: QCA Linux Team <[email protected]>
Signed-off-by: Gabor Juhos <[email protected]>
Patchwork: http://patchwork.linux-mips.org/patch/4945/
Signed-off-by: John Crispin <[email protected]>
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Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.
Signed-off-by: Ralf Baechle <[email protected]>
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Besides the CPU and DDR PLLs, the CPU and DDR frequencies
can be derived from other PLLs in the SRIF block on the
AR934x SoCs. The current code does not checks if the SRIF
PLLs are used and this can lead to incorrectly calculated
CPU/DDR frequencies.
Fix it by calculating the frequencies from SRIF PLLs if
those are used on a given board.
Signed-off-by: Gabor Juhos <[email protected]>
Cc: <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/4324/
Signed-off-by: Ralf Baechle <[email protected]>
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The current dividers in the code are wrong and this
leads to broken CPU frequency calculation on boards
where the fractional part is used.
For example, if the SoC is running from a 40MHz
reference clock, refdiv=1, nint=14, outdiv=0 and
nfrac=31 the real frequency is 579.375MHz but the
current code calculates 569.687MHz instead.
Because the system time is indirectly related to
the CPU frequency the broken computation causes
drift in the system time.
The correct divider is 2^6 for the CPU PLL and 2^10
for the DDR PLL. Use the correct values to fix the
issue.
Signed-off-by: Gabor Juhos <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/4305/
Signed-off-by: Ralf Baechle <[email protected]>
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Signed-off-by: Gabor Juhos <[email protected]>
Acked-by: Luis R. Rodriguez <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/3507/
Signed-off-by: Ralf Baechle <[email protected]>
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Signed-off-by: Gabor Juhos <[email protected]>
Cc: [email protected]
Cc: Kathy Giori <[email protected]>
Cc: "Luis R. Rodriguez" <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/2522/
Signed-off-by: Ralf Baechle <[email protected]>
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This patch adds initial support for various Atheros SoCs based on the
MIPS 24Kc core. The following models are supported at the moment:
- AR7130
- AR7141
- AR7161
- AR9130
- AR9132
- AR7240
- AR7241
- AR7242
The current patch contains minimal support only, but the resulting
kernel can boot into user-space with using of an initramfs image on
various boards which are using these SoCs. Support for more built-in
devices and individual boards will be implemented in further patches.
Signed-off-by: Gabor Juhos <[email protected]>
Signed-off-by: Imre Kaloz <[email protected]>
Cc: [email protected]
Cc: Luis R. Rodriguez <[email protected]>
Cc: Cliff Holden <[email protected]>
Cc: Kathy Giori <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/1947/
Signed-off-by: Ralf Baechle <[email protected]>
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