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This register describes the silicon id and chip unique id. It varies
between CPU revisions, but is always part of the SCU.
Reviewed-by: Andrew Jeffery <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Joel Stanley <[email protected]>
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There was a request to preprocess the module linker script like we
do for the vmlinux one. (https://lkml.org/lkml/2020/8/21/512)
The difference between vmlinux.lds and module.lds is that the latter
is needed for external module builds, thus must be cleaned up by
'make mrproper' instead of 'make clean'. Also, it must be created
by 'make modules_prepare'.
You cannot put it in arch/$(SRCARCH)/kernel/, which is cleaned up by
'make clean'. I moved arch/$(SRCARCH)/kernel/module.lds to
arch/$(SRCARCH)/include/asm/module.lds.h, which is included from
scripts/module.lds.S.
scripts/module.lds is fine because 'make clean' keeps all the
build artifacts under scripts/.
You can add arch-specific sections in <asm/module.lds.h>.
Signed-off-by: Masahiro Yamada <[email protected]>
Tested-by: Jessica Yu <[email protected]>
Acked-by: Will Deacon <[email protected]>
Acked-by: Geert Uytterhoeven <[email protected]>
Acked-by: Palmer Dabbelt <[email protected]>
Reviewed-by: Kees Cook <[email protected]>
Acked-by: Jessica Yu <[email protected]>
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Enabling off mode was only reachable deeply hidden
in the debugfs. As powersaving is an important feature,
move the option out of its shady place.
The debugfs file can still be used to override the default.
Use the presence of a device compatible to ti,twl4030-idle or
ti,twl4030-idle-osc-off as an indicator that the board is wired correctly
for off mode.
Signed-off-by: Andreas Kemnade <[email protected]>
[[email protected]: updated to fix a checkpatch warning]
Signed-off-by: Tony Lindgren <[email protected]>
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Enable usb device for sam9x60ek board.
Signed-off-by: Cristian Birsan <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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The MMU off code path in ll_get_coherency_base() attempts to decide
whether the coherency fabric is mapped by testing the value of
coherency_base, which carries its virtual address if its mapped, and
0x0 otherwise.
However, what the code actually does is take the virtual address of
the coherency_base symbol, and compare it with 0x0, which are never
equal, and so the branch is never taken. In fact, with the MMU off,
dereferencing the VA of coherency_base is not possible to begin with,
nor can its value be relied upon with the MMU off since it is not
cleaned to the Dcache as is done with coherency_phys_base in
armada_370_coherency_init().
Instead, the value of coherency_phys_base is returned, which results
in the correct behavior since it will be 0x0 as well if the coherency
fabric is not mapped, and it is accessible with the MMU off. So just
drop the comparison and the branch.
Fixes: 30cdef97107370a7 ("ARM: mvebu: make the coherency_ll.S functions work with no coherency fabric")
Cc: Thomas Petazzoni <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Signed-off-by: Ard Biesheuvel <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
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Add arm-pmu node on stm32mp15.
Signed-off-by: Alexandre Torgue <[email protected]>
Signed-off-by: Marek Vasut <[email protected]> # update to linux-next
Tested-by: Marek Vasut <[email protected]> # on DH PDK2 and Avenger96
Signed-off-by: Alexandre Torgue <[email protected]>
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This patch adds FMC2 External Bus Interface support on stm32mp157c.
Signed-off-by: Christophe Kerello <[email protected]>
Signed-off-by: Alexandre Torgue <[email protected]>
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The "eMMC high-speed DDR mode (3.3V I/O)" at 50MHz is supported on
the eMMC-interface of the lxa-mc1. Set it in the device tree to
benefit from the speed improvement.
Signed-off-by: Ahmad Fatoum <[email protected]>
Signed-off-by: Holger Assmann <[email protected]>
Signed-off-by: Alexandre Torgue <[email protected]>
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The display PWM channel is number 3 (PWM2 CH4), make it so.
Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board")
Signed-off-by: Marek Vasut <[email protected]>
Cc: Alexandre Torgue <[email protected]>
Cc: Maxime Coquelin <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: [email protected]
To: [email protected]
Signed-off-by: Alexandre Torgue <[email protected]>
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The DH AV96 has RTS/CTS lines available on UART7, describe them in DT.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Alexandre Torgue <[email protected]>
Cc: Maxime Coquelin <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: [email protected]
To: [email protected]
Signed-off-by: Alexandre Torgue <[email protected]>
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On the production revision of the SoM, 587-200, the PHY reset GPIO and
touchscreen IRQs are swapped to prevent collision between EXTi IRQs,
reflect that in DT.
Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board")
Signed-off-by: Marek Vasut <[email protected]>
Cc: Alexandre Torgue <[email protected]>
Cc: Maxime Coquelin <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: [email protected]
To: [email protected]
Signed-off-by: Alexandre Torgue <[email protected]>
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Previously the FIFO on the stm32h743 usart was not utilized, because
the stm32f7 compatible configures it without FIFO support.
Signed-off-by: Tobias Schramm <[email protected]>
Signed-off-by: Alexandre Torgue <[email protected]>
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The stm32 spi driver tries to determine the fifo size of spi devices
dynamically. However, if the spi was already configured by the bootloader
the fifo size check can become an endless loop, because the driver
expects the spi to be in its initial "after device reset" state. The
driver does already support resetting the spi device at probe, thus this
patch adds only the required device tree properties
Signed-off-by: Tobias Schramm <[email protected]>
Signed-off-by: Alexandre Torgue <[email protected]>
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Declare LTDC (display controller) on stm32h743.
Signed-off-by: Tobias Schramm <[email protected]>
Signed-off-by: Alexandre Torgue <[email protected]>
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The DH PDK2 has RTS/CTS lines available on UART8, describe them in DT.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Alexandre Torgue <[email protected]>
Cc: Maxime Coquelin <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: [email protected]
To: [email protected]
Signed-off-by: Alexandre Torgue <[email protected]>
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The QSPI CS2 is not used on DHCOM, remove the pinmux settings.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Alexandre Torgue <[email protected]>
Cc: Maxime Coquelin <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: [email protected]
To: [email protected]
Signed-off-by: Alexandre Torgue <[email protected]>
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Add extra RTS/CTS line pinmux for STM32MP1 UART8.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Alexandre Torgue <[email protected]>
Cc: Maxime Coquelin <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: [email protected]
To: [email protected]
Acked-by: Fabrice Gasnier <[email protected]>
Signed-off-by: Alexandre Torgue <[email protected]>
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Add support for Seeed Studio's stm32mp157c odyssey board.
Board consists of SoM with stm32mp157c with 4GB eMMC and 512 MB DDR3 RAM
and carrier board with USB and ETH interfaces, SD card connector,
wifi and BT chip AP6236.
In this patch only basic kernel boot is supported and interfacing
SD card and on-board eMMC.
Signed-off-by: Marcin Sloniewski <[email protected]>
Reviewed-by: Ahmad Fatoum <[email protected]>
Signed-off-by: Alexandre Torgue <[email protected]>
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The KSZ9031 PHY skew timings for rxc/txc, originally set to achieve
the desired phase shift between clock- and data-signal, now trigger a
kernel warning when used in rgmii-id mode:
*-skew-ps values should be used only with phy-mode = "rgmii"
This is because commit bcf3440c6dd7 ("net: phy: micrel: add phy-mode
support for the KSZ9031 PHY") now configures own timings when
phy-mode = "rgmii-id". Device trees wanting to set their own delays
should use phy-mode "rgmii" instead as the warning prescribes.
The "standard" timings now used with "rgmii-id" work fine on this
board, so drop the explicit timings in the device tree and thereby
silence the warning.
Fixes: 666b5ca85cd3 ("ARM: dts: stm32: add STM32MP1-based Linux Automation MC-1 board")
Signed-off-by: Holger Assmann <[email protected]>
Acked-by: Ahmad Fatoum <[email protected]>
Signed-off-by: Alexandre Torgue <[email protected]>
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The DH PDK2 board is capable of USB OTG on the X14 USB Mini-AB connector,
fill in the missing bits to make USB OTG possible instead of peripheral.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Alexandre Torgue <[email protected]>
Cc: Maxime Coquelin <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: [email protected]
To: [email protected]
Signed-off-by: Alexandre Torgue <[email protected]>
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The AV96 uses sdmmc2_d47_pins_c and sdmmc2_d47_sleep_pins_c, which
differ from sdmmc2_d47_pins_b and sdmmc2_d47_sleep_pins_b in one
pin, SDMMC2_D5, which is PA15 in the former and PA9 in the later.
The PA15 is correct on AV96, so fix this. This error is likely a
result of rebasing across the stm32mp1 DT pinctrl rework.
Fixes: 611325f68102 ("ARM: dts: stm32: Add eMMC attached to SDMMC2 on AV96")
Signed-off-by: Marek Vasut <[email protected]>
Cc: Alexandre Torgue <[email protected]>
Cc: Maxime Coquelin <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: [email protected]
To: [email protected]
Signed-off-by: Alexandre Torgue <[email protected]>
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Add DT for DH DRC02 unit, which is a universal controller device.
The system has two ethernet ports, two CANs, RS485 and RS232, USB,
capacitive buttons and an OLED display.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Alexandre Torgue <[email protected]>
Cc: Maxime Coquelin <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: [email protected]
To: [email protected]
Signed-off-by: Alexandre Torgue <[email protected]>
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The PHY and the VIO regulator is populated on the SoM, move it
into the SoM DT.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Alexandre Torgue <[email protected]>
Cc: Maxime Coquelin <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: [email protected]
To: [email protected]
Signed-off-by: Alexandre Torgue <[email protected]>
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If cpu_cluster_pm_enter() fails, we need to set MPU power domain back
to enabled to prevent the next WFI from potentially triggering an
undesired MPU power domain state change.
We already do this for omap_enter_idle_smp() but are missing it for
omap_enter_idle_coupled().
Fixes: 55be2f50336f ("ARM: OMAP2+: Handle errors for cpu_pm")
Signed-off-by: Tony Lindgren <[email protected]>
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Pull networking fixes from Jakub Kicinski:
- fix failure to add bond interfaces to a bridge, the offload-handling
code was too defensive there and recent refactoring unearthed that.
Users complained (Ido)
- fix unnecessarily reflecting ECN bits within TOS values / QoS marking
in TCP ACK and reset packets (Wei)
- fix a deadlock with bpf iterator. Hopefully we're in the clear on
this front now... (Yonghong)
- BPF fix for clobbering r2 in bpf_gen_ld_abs (Daniel)
- fix AQL on mt76 devices with FW rate control and add a couple of AQL
issues in mac80211 code (Felix)
- fix authentication issue with mwifiex (Maximilian)
- WiFi connectivity fix: revert IGTK support in ti/wlcore (Mauro)
- fix exception handling for multipath routes via same device (David
Ahern)
- revert back to a BH spin lock flavor for nsid_lock: there are paths
which do require the BH context protection (Taehee)
- fix interrupt / queue / NAPI handling in the lantiq driver (Hauke)
- fix ife module load deadlock (Cong)
- make an adjustment to netlink reply message type for code added in
this release (the sole change touching uAPI here) (Michal)
- a number of fixes for small NXP and Microchip switches (Vladimir)
[ Pull request acked by David: "you can expect more of this in the
future as I try to delegate more things to Jakub" ]
* git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net: (167 commits)
net: mscc: ocelot: fix some key offsets for IP4_TCP_UDP VCAP IS2 entries
net: dsa: seville: fix some key offsets for IP4_TCP_UDP VCAP IS2 entries
net: dsa: felix: fix some key offsets for IP4_TCP_UDP VCAP IS2 entries
inet_diag: validate INET_DIAG_REQ_PROTOCOL attribute
net: bridge: br_vlan_get_pvid_rcu() should dereference the VLAN group under RCU
net: Update MAINTAINERS for MediaTek switch driver
net/mlx5e: mlx5e_fec_in_caps() returns a boolean
net/mlx5e: kTLS, Avoid kzalloc(GFP_KERNEL) under spinlock
net/mlx5e: kTLS, Fix leak on resync error flow
net/mlx5e: kTLS, Add missing dma_unmap in RX resync
net/mlx5e: kTLS, Fix napi sync and possible use-after-free
net/mlx5e: TLS, Do not expose FPGA TLS counter if not supported
net/mlx5e: Fix using wrong stats_grps in mlx5e_update_ndo_stats()
net/mlx5e: Fix multicast counter not up-to-date in "ip -s"
net/mlx5e: Fix endianness when calculating pedit mask first bit
net/mlx5e: Enable adding peer miss rules only if merged eswitch is supported
net/mlx5e: CT: Fix freeing ct_label mapping
net/mlx5e: Fix memory leak of tunnel info when rule under multipath not ready
net/mlx5e: Use synchronize_rcu to sync with NAPI
net/mlx5e: Use RCU to protect rq->xdp_prog
...
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Add a Device Tree for the RoseapplePi SBC.
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Peter Korsgaard <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
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The PPI interrupts for cortex-a9 were incorrectly specified, fix them.
Fixes: fdfe7f4f9d85 ("ARM: dts: Add Actions Semi S500 and LeMaker Guitar")
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Peter Korsgaard <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
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Add Device Trees for Caninos Loucos Labrador CoM Core v2 and base board
M v1. Based on the work of Andreas Färber on Lemaker Guitar device tree.
Signed-off-by: Matheus Castello <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Andreas Färber <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
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GPIO_ACTIVE_x flags are not correct in the context of interrupt flags.
These are simple defines so they could be used in DTS but they will not
have the same meaning:
1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE
2. GPIO_ACTIVE_LOW = 1 = IRQ_TYPE_EDGE_RISING
Correct the interrupt flags, assuming the author of the code wanted same
logical behavior behind the name "ACTIVE_xxx", this is:
ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Acked-By: Tim Harvey <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Most of the definitions for peripheral base addresses, interrupt and
DMA information is no longer used, so get rid of them.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Now that imx35 has been converted to a devicetree-only platform,
retrieve the IIM base address from devicetree.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Now that imx31 and imx35 has been converted to a devicetree-only platform,
retrieve the AVIC base address from devicetree.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Now that imx31 and imx35 has been converted to a devicetree-only platform,
retrieve the CCM base address from devicetree.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Now that imx31 has been converted to a devicetree-only platform,
retrieve the IIM base address from devicetree.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Now that imx27 has been converted to a devicetree-only platform,
retrieve the CCM base address from devicetree.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Now that imx27 has been converted to a devicetree-only platform,
retrieve the SYSCTRL base address from devicetree.
To keep devicetree compatibilty the SYSCTRL base address will be
retrieved from the CCM base address plus an 0x800 offset.
This is not a problem as the imx27.dtsi describes the CCM register
range as 0x1000.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Using the native SPI chipselect on i.MX6 is known to be problematic.
Doing it on a imx6q-sabresd causes the SPI NOR probe to fail:
[ 5.388704] spi-nor spi0.0: unrecognized JEDEC id bytes: 00 00 00 00 00 00
Use the GPIO chipselect to avoid such problem.
Signed-off-by: Fabio Estevam <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Add an entry for imx6q-logicpd.dtb so that it can be built by default.
Signed-off-by: Fabio Estevam <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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It is standard practice to have a specific board compatible string, so
pass "logicpd,imx6q-logicpd".
Signed-off-by: Fabio Estevam <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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dtschema for pca95xx expects GPIO hogs to end with 'hog' prefix. While
touching the hogs, fix indentation (spaces -> tabs).
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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port6 of mt7530 switch (= cpu port 0) on bananapi-r2 misses pause option
which causes rx drops on running iperf.
Fixes: f4ff257cd160 ("arm: dts: mt7623: add support for Bananapi R2 (BPI-R2) board")
Signed-off-by: Frank Wunderlich <[email protected]>
Cc: [email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Matthias Brugger <[email protected]>
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The msi_ctrl, io_optional and align_resource fields in struct hw_pci are
currently unused by arm/mach PCI host controller drivers and we won't
be adding any new users.
Remove them and related code.
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Russell King <[email protected]>
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arch_scale_freq_invariant() is used by schedutil to determine whether
the scheduler's load-tracking signals are frequency invariant. Its
definition is overridable, though by default it is hardcoded to 'true'
if arch_scale_freq_capacity() is defined ('false' otherwise).
This behaviour is not overridden on arm, arm64 and other users of the
generic arch topology driver, which is somewhat precarious:
arch_scale_freq_capacity() will always be defined, yet not all cpufreq
drivers are guaranteed to drive the frequency invariance scale factor
setting. In other words, the load-tracking signals may very well *not*
be frequency invariant.
Now that cpufreq can be queried on whether the current driver is driving
the Frequency Invariance (FI) scale setting, the current situation can
be improved. This combines the query of whether cpufreq supports the
setting of the frequency scale factor, with whether all online CPUs are
counter-based FI enabled.
While cpufreq FI enablement applies at system level, for all CPUs,
counter-based FI support could also be used for only a subset of CPUs to
set the invariance scale factor. Therefore, if cpufreq-based FI support
is present, we consider the system to be invariant. If missing, we
require all online CPUs to be counter-based FI enabled in order for the
full system to be considered invariant.
If the system ends up not being invariant, a new condition is needed in
the counter initialization code that disables all scale factor setting
based on counters.
Precedence of counters over cpufreq use is not important here. The
invariant status is only given to the system if all CPUs have at least
one method of setting the frequency scale factor.
Signed-off-by: Valentin Schneider <[email protected]>
Signed-off-by: Ionela Voinescu <[email protected]>
Acked-by: Catalin Marinas <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
Reviewed-by: Sudeep Holla <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>
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ipi_teardown() is only used when CONFIG_HOTPLUG_CPU is enabled.
Move the function to a location guarded by this config option.
Signed-off-by: Marc Zyngier <[email protected]>
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The new field 'dma_range_map' in struct device is used to facilitate the
use of single or multiple offsets between mapping regions of cpu addrs and
dma addrs. It subsumes the role of "dev->dma_pfn_offset" which was only
capable of holding a single uniform offset and had no region bounds
checking.
The function of_dma_get_range() has been modified so that it takes a single
argument -- the device node -- and returns a map, NULL, or an error code.
The map is an array that holds the information regarding the DMA regions.
Each range entry contains the address offset, the cpu_start address, the
dma_start address, and the size of the region.
of_dma_configure() is the typical manner to set range offsets but there are
a number of ad hoc assignments to "dev->dma_pfn_offset" in the kernel
driver code. These cases now invoke the function
dma_direct_set_offset(dev, cpu_addr, dma_addr, size).
Signed-off-by: Jim Quinlan <[email protected]>
[hch: various interface cleanups]
Signed-off-by: Christoph Hellwig <[email protected]>
Reviewed-by: Mathieu Poirier <[email protected]>
Tested-by: Mathieu Poirier <[email protected]>
Tested-by: Nathan Chancellor <[email protected]>
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The DMA offset notifier can only be used if PHYS_OFFSET is at least
KEYSTONE_HIGH_PHYS_START, which can't be represented by a 32-bit
phys_addr_t. Currently the code compiles fine despite that, a pending
change to the DMA offset handling would create a compiler warning for
this case. Add an ifdef to not compile the code except for LPAE
configs.
Signed-off-by: Christoph Hellwig <[email protected]>
Reviewed-by: Robin Murphy <[email protected]>
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Move the helpers to translate to and from direct mapping DMA addresses
to dma-direct.h. This not only is the most logical place, but the new
placement also avoids dependency loops with pending commits.
Signed-off-by: Christoph Hellwig <[email protected]>
Reviewed-by: Robin Murphy <[email protected]>
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dma_to_virt is entirely unused, remove it.
Signed-off-by: Christoph Hellwig <[email protected]>
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The __arch_page_to_dma hook is long gone.
Signed-off-by: Christoph Hellwig <[email protected]>
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V3s contains crypto engine that is compatible with A33.
Add device tree node.
Signed-off-by: Martin Cerveny <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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