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2016-03-10Merge tag 'arm64-fixes' of ↵Linus Torvalds2-16/+3
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fixes from Will Deacon: "I thought we were done for 4.5, but then the 64k-page chaps came crawling out of the woodwork. *sigh* The vmemmap fix I sent for -rc7 caused a regression with 64k pages and sparsemem and at some point during the release cycle the new hugetlb code using contiguous ptes started failing the libhugetlbfs tests with 64k pages enabled. So here are a couple of patches that fix the vmemmap alignment and disable the new hugetlb page sizes whilst a proper fix is being developed: - Temporarily disable huge pages built using contiguous ptes - Ensure vmemmap region is sufficiently aligned for sparsemem sections" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: hugetlb: partial revert of 66b3923a1a0f arm64: account for sparsemem section alignment when choosing vmemmap offset
2016-03-09arm64: kasan: clear stale stack poisonMark Rutland1-0/+4
Functions which the compiler has instrumented for KASAN place poison on the stack shadow upon entry and remove this poison prior to returning. In the case of cpuidle, CPUs exit the kernel a number of levels deep in C code. Any instrumented functions on this critical path will leave portions of the stack shadow poisoned. If CPUs lose context and return to the kernel via a cold path, we restore a prior context saved in __cpu_suspend_enter are forgotten, and we never remove the poison they placed in the stack shadow area by functions calls between this and the actual exit of the kernel. Thus, (depending on stackframe layout) subsequent calls to instrumented functions may hit this stale poison, resulting in (spurious) KASAN splats to the console. To avoid this, clear any stale poison from the idle thread for a CPU prior to bringing a CPU online. Signed-off-by: Mark Rutland <[email protected]> Acked-by: Catalin Marinas <[email protected]> Reviewed-by: Andrey Ryabinin <[email protected]> Reviewed-by: Lorenzo Pieralisi <[email protected]> Cc: Alexander Potapenko <[email protected]> Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Cc: Ingo Molnar <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2016-03-09arm64: hugetlb: partial revert of 66b3923a1a0fWill Deacon1-14/+0
Commit 66b3923a1a0f ("arm64: hugetlb: add support for PTE contiguous bit") introduced support for huge pages using the contiguous bit in the PTE as opposed to block mappings, which may be slightly unwieldy (512M) in 64k page configurations. Unfortunately, this support has resulted in some late regressions when running the libhugetlbfs test suite with 64k pages and CONFIG_DEBUG_VM as a result of a BUG: | readback (2M: 64): ------------[ cut here ]------------ | kernel BUG at fs/hugetlbfs/inode.c:446! | Internal error: Oops - BUG: 0 [#1] SMP | Modules linked in: | CPU: 7 PID: 1448 Comm: readback Not tainted 4.5.0-rc7 #148 | Hardware name: linux,dummy-virt (DT) | task: fffffe0040964b00 ti: fffffe00c2668000 task.ti: fffffe00c2668000 | PC is at remove_inode_hugepages+0x44c/0x480 | LR is at remove_inode_hugepages+0x264/0x480 Rather than revert the entire patch, simply avoid advertising the contiguous huge page sizes for now while people are actively working on a fix. This patch can then be reverted once things have been sorted out. Cc: David Woods <[email protected]> Reported-by: Steve Capper <[email protected]> Signed-off-by: Will Deacon <[email protected]>
2016-03-09arm64: account for sparsemem section alignment when choosing vmemmap offsetArd Biesheuvel1-2/+3
Commit dfd55ad85e4a ("arm64: vmemmap: use virtual projection of linear region") fixed an issue where the struct page array would overflow into the adjacent virtual memory region if system RAM was placed so high up in physical memory that its addresses were not representable in the build time configured virtual address size. However, the fix failed to take into account that the vmemmap region needs to be relatively aligned with respect to the sparsemem section size, so that a sequence of page structs corresponding with a sparsemem section in the linear region appears naturally aligned in the vmemmap region. So round up vmemmap to sparsemem section size. Since this essentially moves the projection of the linear region up in memory, also revert the reduction of the size of the vmemmap region. Cc: <[email protected]> Fixes: dfd55ad85e4a ("arm64: vmemmap: use virtual projection of linear region") Tested-by: Mark Langsdorf <[email protected]> Tested-by: David Daney <[email protected]> Tested-by: Robert Richter <[email protected]> Acked-by: Catalin Marinas <[email protected]> Signed-off-by: Ard Biesheuvel <[email protected]> Signed-off-by: Will Deacon <[email protected]>
2016-03-09arm64: KVM: vgic-v3: Only wipe LRs on vcpu exitMarc Zyngier1-5/+4
So far, we're always writing all possible LRs, setting the empty ones with a zero value. This is obvious doing a low of work for nothing, and we're better off clearing those we've actually dirtied on the exit path (it is very rare to inject more than one interrupt at a time anyway). Reviewed-by: Christoffer Dall <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2016-03-09arm64: KVM: vgic-v3: Reset LRs at boot timeMarc Zyngier2-0/+10
In order to let the GICv3 code be more lazy in the way it accesses the LRs, it is necessary to start with a clean slate. Let's reset the LRs on each CPU when the vgic is probed (which includes a round trip to EL2...). Reviewed-by: Christoffer Dall <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2016-03-09arm64: KVM: vgic-v3: Do not save an LR known to be emptyMarc Zyngier1-2/+9
On exit, any empty LR will be signaled in ICH_ELRSR_EL2. Which means that we do not have to save it, and we can just clear its state in the in-memory copy. Reviewed-by: Christoffer Dall <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2016-03-09arm64: KVM: vgic-v3: Save maintenance interrupt state only if requiredMarc Zyngier1-2/+31
Next on our list of useless accesses is the maintenance interrupt status registers (ICH_MISR_EL2, ICH_EISR_EL2). It is pointless to save them if we haven't asked for a maintenance interrupt the first place, which can only happen for two reasons: - Underflow: ICH_HCR_UIE will be set, - EOI: ICH_LR_EOI will be set. These conditions can be checked on the in-memory copies of the regs. Should any of these two condition be valid, we must read GICH_MISR. We can then check for ICH_MISR_EOI, and only when set read ICH_EISR_EL2. This means that in most case, we don't have to save them at all. Reviewed-by: Christoffer Dall <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2016-03-09arm64: KVM: vgic-v3: Avoid accessing ICH registersMarc Zyngier1-113/+180
Just like on GICv2, we're a bit hammer-happy with GICv3, and access them more often than we should. Adopt a policy similar to what we do for GICv2, only save/restoring the minimal set of registers. As we don't access the registers linearly anymore (we may skip some), the convoluted accessors become slightly simpler, and we can drop the ugly indexing macro that tended to confuse the reviewers. Reviewed-by: Christoffer Dall <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2016-03-08PCI: Include pci/hotplug Kconfig directly from pci/KconfigBjorn Helgaas1-1/+0
Include pci/hotplug/Kconfig directly from pci/Kconfig, so arches don't have to source both pci/Kconfig and pci/hotplug/Kconfig. Note that this effectively adds pci/hotplug/Kconfig to the following arches, because they already sourced drivers/pci/Kconfig but they previously did not source drivers/pci/hotplug/Kconfig: alpha arm avr32 frv m68k microblaze mn10300 sparc unicore32 Inspired-by-patch-from: Bogicevic Sasa <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2016-03-08PCI: Include pci/pcie/Kconfig directly from pci/KconfigBogicevic Sasa1-1/+0
Include pci/pcie/Kconfig directly from pci/Kconfig, so arches don't have to source both pci/Kconfig and pci/pcie/Kconfig. Note that this effectively adds pci/pcie/Kconfig to the following arches, because they already sourced drivers/pci/Kconfig but they previously did not source drivers/pci/pcie/Kconfig: alpha avr32 blackfin frv m32r m68k microblaze mn10300 parisc sparc unicore32 xtensa [bhelgaas: changelog, source pci/pcie/Kconfig at top of pci/Kconfig, whitespace] Signed-off-by: Sasa Bogicevic <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2016-03-08Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller5-18/+19
Several cases of overlapping changes, as well as one instance (vxlan) of a bug fix in 'net' overlapping with code movement in 'net-next'. Signed-off-by: David S. Miller <[email protected]>
2016-03-08arm64: dts: juno/vexpress: fix node name unit-address presence warningsSudeep Holla6-36/+36
Commit fa38a82096a1 ("scripts/dtc: Update to upstream version 53bf130b1cdd") added warnings on node name unit-address presence/absence mismatch in device trees. This patch fixes those warning on all the juno/vexpress platforms where unit-address is present in node name while the reg/ranges property is not present. It also adds unit-address to all smb bus node. Signed-off-by: Sudeep Holla <[email protected]>
2016-03-08arm64: dts: foundation-v8: add SBSA Generic Watchdog device nodeFu Wei1-0/+8
This can be a example of adding SBSA Generic Watchdog device node into some dts files for the Soc which contains SBSA Generic Watchdog. Acked-by: Arnd Bergmann <[email protected]> Signed-off-by: Fu Wei <[email protected]> [edited subject and moved change to dtsi file] Signed-off-by: Sudeep Holla <[email protected]>
2016-03-07PCI: Move pci_dma_* helpers to common codeChristoph Hellwig1-1/+0
For a long time all architectures implement the pci_dma_* functions using the generic DMA API, and they all use the same header to do so. Move this header, pci-dma-compat.h, to include/linux and include it from the generic pci.h instead of having each arch duplicate this include. Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2016-03-07ARM64: dts: amlogic: Add Tronsmart Vega S95 configsAndreas Färber5-0/+224
Add Device Trees for Tronsmart Vega S95 Pro, Meta and Telos TV boxes. Signed-off-by: Andreas Färber <[email protected]> Signed-off-by: Carlo Caione <[email protected]>
2016-03-07ARM64: dts: Prepare configs for Amlogic Meson GXBabyAndreas Färber3-0/+187
Signed-off-by: Andreas Färber <[email protected]> Signed-off-by: Carlo Caione <[email protected]>
2016-03-07ARM64: Enable Amlogic Meson GXBaby platformAndreas Färber1-0/+5
Provide the ARCH_MESON Kconfig symbol to allow enabling existing serial and i2c drivers. Signed-off-by: Andreas Färber <[email protected]> Signed-off-by: Carlo Caione <[email protected]>
2016-03-04Merge tag 'arm64-fixes' of ↵Linus Torvalds2-5/+6
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fix from Will Deacon: "Arm64 fix for -rc7. Without it, our struct page array can overflow the vmemmap region on systems with a large PHYS_OFFSET. Nothing else on the radar at the moment, so hopefully that's it for 4.5 from us. Summary: Ensure struct page array fits within vmemmap area" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: vmemmap: use virtual projection of linear region
2016-03-04Merge branches 'amba', 'fixes', 'misc' and 'tauros2' into for-nextRussell King1-97/+2
2016-03-04arm64: Fix misspellings in comments.Adam Buchbinder9-11/+11
Signed-off-by: Adam Buchbinder <[email protected]> Signed-off-by: Catalin Marinas <[email protected]>
2016-03-04arm64: efi: add missing frame pointer assignmentArd Biesheuvel1-0/+1
The prologue of the EFI entry point pushes x29 and x30 onto the stack but fails to create the stack frame correctly by omitting the assignment of x29 to the new value of the stack pointer. So fix that. Signed-off-by: Ard Biesheuvel <[email protected]> Signed-off-by: Catalin Marinas <[email protected]>
2016-03-04arm64: make mrs_s prefixing implicit in read_cpuidMark Rutland5-64/+64
Commit 0f54b14e76f5302a ("arm64: cpufeature: Change read_cpuid() to use sysreg's mrs_s macro") changed read_cpuid to require a SYS_ prefix on register names, to allow manual assembly of registers unknown by the toolchain, using tables in sysreg.h. This interacts poorly with commit 42b55734030c1f72 ("efi/arm64: Check for h/w support before booting a >4 KB granular kernel"), which is curretly queued via the tip tree, and uses read_cpuid without a SYS_ prefix. Due to this, a build of next-20160304 fails if EFI and 64K pages are selected. To avoid this issue when trees are merged, move the required SYS_ prefixing into read_cpuid, and revert all of the updated callsites to pass plain register names. This effectively reverts the bulk of commit 0f54b14e76f5302a. Signed-off-by: Mark Rutland <[email protected]> Cc: James Morse <[email protected]> Signed-off-by: Catalin Marinas <[email protected]>
2016-03-04Merge tag 'v4.5-rc6' into core/resources, to resolve conflictIngo Molnar26-88/+179
Signed-off-by: Ingo Molnar <[email protected]>
2016-03-03Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds1-1/+1
Pull KVM fixes from Paolo Bonzini: - ARM/MIPS: Fixes for ioctls when copy_from_user returns nonzero - x86: Small fix for Skylake TSC scaling - x86: Improved fix for last week's missed hardware breakpoint bug * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: kvm: x86: Update tsc multiplier on change. mips/kvm: fix ioctl error handling arm/arm64: KVM: Fix ioctl error handling KVM: x86: fix root cause for missed hardware breakpoints
2016-03-03arm64: enable CONFIG_DEBUG_RODATA by defaultArd Biesheuvel1-3/+3
In spite of its name, CONFIG_DEBUG_RODATA is an important hardening feature for production kernels, and distros all enable it by default in their kernel configs. However, since enabling it used to result in more granular, and thus less efficient kernel mappings, it is not enabled by default for performance reasons. However, since commit 2f39b5f91eb4 ("arm64: mm: Mark .rodata as RO"), the various kernel segments (.text, .rodata, .init and .data) are already mapped individually, and the only effect of setting CONFIG_DEBUG_RODATA is that the existing .text and .rodata mappings are updated late in the boot sequence to have their read-only attributes set, which means that any performance concerns related to enabling CONFIG_DEBUG_RODATA are no longer valid. So from now on, make CONFIG_DEBUG_RODATA default to 'y' Signed-off-by: Ard Biesheuvel <[email protected]> Acked-by: Mark Rutland <[email protected]> Acked-by: Kees Cook <[email protected]> Signed-off-by: Catalin Marinas <[email protected]>
2016-03-02Merge tag 'samsung-defconfig-4.6-2' of ↵Arnd Bergmann1-0/+6
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/arm64 Merge "ARM64 defconfig changes for Exynos based boards for v4.6" from Krzysztof Kozlowski: 1. We want thermal for Exynos7 TMU unit to monitor the temperature. 2. Enable the drivers for PMIC used on Exynos7-based Espresso board. * tag 'samsung-defconfig-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: defconfig: Enable Samsung MFD and related configs arm64: defconfig: Enable exynos thermal config ARM: multi_v7_defconfig: Remove MAX77802 RTC Kconfig symbol ARM: exynos_defconfig: Remove MAX77802 RTC Kconfig symbol rtc: max77686: Cleanup and reduce dmesg output rtc: Remove Maxim 77802 driver rtc: max77686: Properly handle regmap_irq_get_virq() error code rtc: max77686: Fix unsupported year message rtc: max77686: Add max77802 support rtc: max77686: Add an indirection level to access RTC registers rtc: max77686: Use a driver data struct instead hard-coded values rtc: max77686: Use usleep_range() instead of msleep() rtc: max77686: Use ARRAY_SIZE() instead of current array length rtc: max77686: Fix max77686_rtc_read_alarm() return value ARM: exynos_defconfig: Enable s5p-secss driver ARM: exynos_defconfig: Enable NEON, accelerated crypto and cpufreq stats Signed-off-by: Arnd Bergmann <[email protected]>
2016-03-02Merge tag 'imx-dt64-4.6' of ↵Arnd Bergmann2-0/+5
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64 Merge "NXP/Freescale arm64 dts update for 4.6" from Shawn Guo: - Add "snps,quirk-frame-length-adjustment" property to USB3 node for erratum A009116, which affects NXP/Freescale arm64 SoCs LS1043A and LS2080A. * tag 'imx-dt64-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: ls1043a: Add quirk for Erratum A009116 arm64: dts: ls2080a: Add quirk for Erratum A009116
2016-03-02Merge tag 'qcom-arm64-for-4.6' of ↵Arnd Bergmann13-23/+880
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64 Merge "Qualcomm ARM64 Updates for v4.6" from Andy Gross: * Add MSM8996 support * Cleanups for MSM8916 * Updates for APQ8016 SBC * Fixup pmic reg properties * Add RPMCC node for 8916 * Add LPASS audio nodes * Add USB support on MSM8916 * tag 'qcom-arm64-for-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: (24 commits) arm64: dts: qcom: Fix MPP's function used for LED control arm64: dts: qcom: fix usb digital voltage levels arm64: dts: qcom: apq8016-sbc: enable lpass on DB410c arm64: dts: qcom: add lpass node arm64: dts: qcom: add audio pinctrls arm64: dts: qcom: apq8016-sbc: add usb support arm64: dts: qcom: add manual pullup setting to otg. arm64: dts: qcom: msm8916: Add RPMCC DT node ARM64: dts: qcom: Remove size elements from pmic reg properties arm64: dts: msm8996: Add #power-domain-cells property arm64: dts: apq8016-sbc: Add real regulators and pinctrl for sdhc arm64: dts: apq8016-sbc: move sdhci node under soc node arm64: dts: apq8016-sbc: make 1.8v available on LS expansion arm64: dts: apq8016-sbc: add regulators support arm64: dts: qcom: add lable for smd rpm regulators arm64: dts: remove s2 regulator from smd regulators. arm64: dts: qcom: add correct drive strenght on cs pins arm64: dts: qcom: remove redundant spi cs pins from pinconf arm64: dts: apq8016-sbc: Add aliases to spi device. arm64: dts: Add L2 cache node to msm8916 ...
2016-03-02arm64: Rework valid_user_regsMark Rutland4-34/+85
We validate pstate using PSR_MODE32_BIT, which is part of the user-provided pstate (and cannot be trusted). Also, we conflate validation of AArch32 and AArch64 pstate values, making the code difficult to reason about. Instead, validate the pstate value based on the associated task. The task may or may not be current (e.g. when using ptrace), so this must be passed explicitly by callers. To avoid circular header dependencies via sched.h, is_compat_task is pulled out of asm/ptrace.h. To make the code possible to reason about, the AArch64 and AArch32 validation is split into separate functions. Software must respect the RES0 policy for SPSR bits, and thus the kernel mirrors the hardware policy (RAZ/WI) for bits as-yet unallocated. When these acquire an architected meaning writes may be permitted (potentially with additional validation). Signed-off-by: Mark Rutland <[email protected]> Acked-by: Will Deacon <[email protected]> Cc: Dave Martin <[email protected]> Cc: James Morse <[email protected]> Cc: Peter Maydell <[email protected]> Signed-off-by: Catalin Marinas <[email protected]>
2016-03-02arm64: mm: check at build time that PAGE_OFFSET divides the VA space evenlyArd Biesheuvel1-0/+7
Commit 8439e62a1561 ("arm64: mm: use bit ops rather than arithmetic in pa/va translations") changed the boundary check against PAGE_OFFSET from an arithmetic comparison to a bit test. This means we now silently assume that PAGE_OFFSET is a power of 2 that divides the kernel virtual address space into two equal halves. So make that assumption explicit. Signed-off-by: Ard Biesheuvel <[email protected]> Signed-off-by: Catalin Marinas <[email protected]>
2016-03-02Merge tag 'kvm-arm-for-4.5-rc7' of ↵Paolo Bonzini1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into kvm-master KVM/ARM fixes for 4.5-rc7 - Fix ioctl error handling on the timer path
2016-03-01arch/hotplug: Call into idle with a proper stateThomas Gleixner1-1/+1
Let the non boot cpus call into idle with the corresponding hotplug state, so the hotplug core can handle the further bringup. That's a first step to convert the boot side of the hotplugged cpus to do all the synchronization with the other side through the state machine. For now it'll only start the hotplug thread and kick the full bringup of the cpu. Signed-off-by: Thomas Gleixner <[email protected]> Cc: [email protected] Cc: Rik van Riel <[email protected]> Cc: Rafael Wysocki <[email protected]> Cc: "Srivatsa S. Bhat" <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Arjan van de Ven <[email protected]> Cc: Sebastian Siewior <[email protected]> Cc: Rusty Russell <[email protected]> Cc: Steven Rostedt <[email protected]> Cc: Oleg Nesterov <[email protected]> Cc: Tejun Heo <[email protected]> Cc: Andrew Morton <[email protected]> Cc: Paul McKenney <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Paul Turner <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2016-03-01arm64: KVM: Move kvm_call_hyp back to its original localtionMarc Zyngier1-2/+2
In order to reduce the risk of a bad merge, let's move the new kvm_call_hyp back to its original location in the file. This has zero impact from a code point of view. Signed-off-by: Marc Zyngier <[email protected]> Acked-by: Ard Biesheuvel <[email protected]> Signed-off-by: Catalin Marinas <[email protected]>
2016-03-01arm64: defconfig: Enable Samsung MFD and related configsAlim Akhtar1-0/+3
Exynos7 based espresso board uses S2MPS15, a multifunction device. This patch enables S2MPS1X regulator, pmic-clk and rtc drivers utilized by the same. Signed-off-by: Alim Akhtar <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]>
2016-03-01Merge tag 'xgene-dts-for-v4.6-part2' of ↵Arnd Bergmann2-0/+38
https://github.com/AppliedMicro/xgene-next into next/dt64 Merge "Second part of X-Gene DT changes queued for v4.6" from Duc Dang: This patch set includes: + X-Gene v2 Mailbox DT node + X-Gene v1 and X-Gene v2 SLIMpro Mailbox I2C driver DT nodes * tag 'xgene-dts-for-v4.6-part2' of https://github.com/AppliedMicro/xgene-next: arm64: dts: apm: Add DT node for X-Gene v2 SLIMpro Mailbox I2C Driver arm64: dts: apm: Mailbox device tree node for APM X-Gene v2 platform. arm64: dts: apm: Add DT node for X-Gene v1 SLIMpro Mailbox I2C Driver arm64: dts: apm: mailbox device tree node for APM X-Gene platform.
2016-03-01Merge tag 'xgene-dts-for-v4.6-part1' of ↵Arnd Bergmann4-3/+14
https://github.com/AppliedMicro/xgene-next into next/dt64 Merge "First part of X-Gene DT changes queued for v4.6" from Duc Dang: This patch set includes: + A change in compatible string of X-Gene v2 SoC PLL DT node to reflect the v2 hardware + Update DT fields for X-Gene v1 and v2 standby GPIO controllers + Update declaration of power button GPIO for X-Gene v1 and X-Gene v2 platforms * tag 'xgene-dts-for-v4.6-part1' of https://github.com/AppliedMicro/xgene-next: arm64: dts: apm: Update GPIO to control power-off on X-Gene v2 platforms arm64: dts: apm: Update GPIO standby controller DT node for X-Gene v2 platforms arm64: dts: apm: Update GPIO to control power-off on X-Gene v1 platforms arm64: dts: apm: Update X-Gene standby GPIO controller DTS entries arm64: dts: apm: Update Merlin DT PCP PLL clock node for v2 hardware
2016-03-01Merge tag 'hip05-config-for-4.6' of git://github.com/hisilicon/linux-hisi ↵Arnd Bergmann1-0/+1
into next/arm64 ARM64: Hip05: configure updates for 4.6 - Enable DesignWare APB GPIO controller * tag 'hip05-config-for-4.6' of git://github.com/hisilicon/linux-hisi: arm64: defconfig: Enable DesignWare APB GPIO controller
2016-02-29arm64: perf: Extend ARMV8_EVTYPE_MASK to include PMCR.LCWill Deacon1-1/+1
Commit 7175f0591eb9 ("arm64: perf: Enable PMCR long cycle counter bit") added initial support for a 64-bit cycle counter enabled using PMCR.LC. Unfortunately, that patch doesn't extend ARMV8_EVTYPE_MASK, so any attempts to set the enable bit are ignored by armv8pmu_pmcr_write. This patch extends the mask to include the new bit. Signed-off-by: Will Deacon <[email protected]>
2016-03-01Merge tag 'hip05-dt-for-4.6' of git://github.com/hisilicon/linux-hisi into ↵Arnd Bergmann2-2/+108
next/dt64 Merge "ARM64: DT: Hisilicon Hip05 soc and D02 board updates for 4.6" from Wei Xu: - Add L2 cache topology - Use Cortex specific device node for pmu - Append all gicv3 ITS entries - Append gpio nodes - Append power button node for D02 board * tag 'hip05-dt-for-4.6' of git://github.com/hisilicon/linux-hisi: arm64: dts: hip05: Append power button node for D02 board arm64: dts: hip05: Append gpio nodes arm64: dts: hip05: Append all gicv3 ITS entries arm64: dts: hip05: Use Cortex specific device node for pmu arm64: dts: hip05: Add L2 cache topology
2016-03-01Merge tag 'sunxi-config64-for-4.6' of ↵Arnd Bergmann2-0/+13
https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/arm64 Merge "Allwinner configuration changes for ARM64, 4.6 edition" from Maxime Ripard: Not a lot of changes for this kernel release, just a new Kconfig option and some changes to the arm64 defconfig to add Allwinner drivers * tag 'sunxi-config64-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: arm64: add defconfig options for Allwinner SoCs arm64: Introduce Allwinner SoC config option
2016-03-01Merge tag 'mvebu-arm64-4.6-2' of git://git.infradead.org/linux-mvebu into ↵Arnd Bergmann1-3/+8
next/arm64 Merge "mvebu arm64 for 4.6 (part 2)" from Gregory CLEMENT: Add initial support for Armada 7K/8K Update Marvell documentation * tag 'mvebu-arm64-4.6-2' of git://git.infradead.org/linux-mvebu: arm64: update ARCH_MVEBU for Marvell Armada 7K/8K support Documentation: arm: add Marvell Armada 7K and 8K families Documentation: arm: add link to Armada 38x Functional Spec Documentation: arm: improve Armada 37xx description Documentation: arm: update Marvell product listing
2016-02-29arm64: dts: qcom: Fix MPP's function used for LED controlIvan T. Ivanov1-1/+1
The qcom-spmi-mpp driver is now using string "digital" to denote old "normal" functionality. Update DTS file. Also update the powersource. Signed-off-by: Ivan T. Ivanov <[email protected]>
2016-02-29arm64: KVM: Switch the sys_reg search to be a binary searchMarc Zyngier1-18/+22
Our 64bit sys_reg table is about 90 entries long (so far, and the PMU support is likely to increase this). This means that on average, it takes 45 comparaisons to find the right entry (and actually the full 90 if we have to search the invariant table). Not the most efficient thing. Specially when you think that this table is already sorted. Switching to a binary search effectively reduces the search to about 7 comparaisons. Slightly better! As an added bonus, the comparison is done by comparing all the fields at once, instead of one at a time. Reviewed-by: Christoffer Dall <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2016-02-29arm64: KVM: Add a new vcpu device control group for PMUv3Shannon Zhao3-0/+62
To configure the virtual PMUv3 overflow interrupt number, we use the vcpu kvm_device ioctl, encapsulating the KVM_ARM_VCPU_PMU_V3_IRQ attribute within the KVM_ARM_VCPU_PMU_V3_CTRL group. After configuring the PMUv3, call the vcpu ioctl with attribute KVM_ARM_VCPU_PMU_V3_INIT to initialize the PMUv3. Signed-off-by: Shannon Zhao <[email protected]> Acked-by: Peter Maydell <[email protected]> Reviewed-by: Andrew Jones <[email protected]> Reviewed-by: Christoffer Dall <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2016-02-29arm64: KVM: Introduce per-vcpu kvm device controlsShannon Zhao1-0/+1
In some cases it needs to get/set attributes specific to a vcpu and so needs something else than ONE_REG. Let's copy the KVM_DEVICE approach, and define the respective ioctls for the vcpu file descriptor. Signed-off-by: Shannon Zhao <[email protected]> Reviewed-by: Andrew Jones <[email protected]> Acked-by: Peter Maydell <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2016-02-29arm64: KVM: Add a new feature bit for PMUv3Shannon Zhao3-1/+5
To support guest PMUv3, use one bit of the VCPU INIT feature array. Initialize the PMU when initialzing the vcpu with that bit and PMU overflow interrupt set. Signed-off-by: Shannon Zhao <[email protected]> Acked-by: Peter Maydell <[email protected]> Reviewed-by: Andrew Jones <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2016-02-29arm64: KVM: Reset PMU state when resetting vcpuShannon Zhao1-0/+3
When resetting vcpu, it needs to reset the PMU state to initial status. Signed-off-by: Shannon Zhao <[email protected]> Reviewed-by: Marc Zyngier <[email protected]> Reviewed-by: Andrew Jones <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2016-02-29arm64: KVM: Add access handler for PMUSERENR registerShannon Zhao5-5/+110
This register resets as unknown in 64bit mode while it resets as zero in 32bit mode. Here we choose to reset it as zero for consistency. PMUSERENR_EL0 holds some bits which decide whether PMU registers can be accessed from EL0. Add some check helpers to handle the access from EL0. When these bits are zero, only reading PMUSERENR will trap to EL2 and writing PMUSERENR or reading/writing other PMU registers will trap to EL1 other than EL2 when HCR.TGE==0. To current KVM configuration (HCR.TGE==0) there is no way to get these traps. Here we write 0xf to physical PMUSERENR register on VM entry, so that it will trap PMU access from EL0 to EL2. Within the register access handler we check the real value of guest PMUSERENR register to decide whether this access is allowed. If not allowed, return false to inject UND to guest. Signed-off-by: Shannon Zhao <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2016-02-29arm64: KVM: Add helper to handle PMCR register bitsShannon Zhao2-1/+4
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are disabled. When writing 1 to PMCR.P, reset all event counters, not including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to zero. Signed-off-by: Shannon Zhao <[email protected]> Reviewed-by: Marc Zyngier <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
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