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2020-11-27KVM: arm64: Refuse illegal KVM_ARM_VCPU_PMU_V3 at reset timeMarc Zyngier2-2/+6
We accept to configure a PMU when a vcpu is created, even if the HW (or the host) doesn't support it. This results in failures when attributes get set, which is a bit odd as we should have failed the vcpu creation the first place. Move the check to the point where we check the vcpu feature set, and fail early if we cannot support a PMU. This further simplifies the attribute handling. Reviewed-by: Alexandru Elisei <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2020-11-27KVM: arm64: Set ID_AA64DFR0_EL1.PMUVer to 0 when no PMU supportMarc Zyngier1-1/+6
We always expose the HW view of PMU in ID_AA64FDR0_EL1.PMUver, even when the PMU feature is disabled, while the architecture says that FEAT_PMUv3 not being implemented should result in this field being zero. Let's follow the architecture's guidance. Reviewed-by: Alexandru Elisei <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2020-11-27KVM: arm64: Refuse to run VCPU if PMU is not initializedAlexandru Elisei1-4/+4
When enabling the PMU in kvm_arm_pmu_v3_enable(), KVM returns early if the PMU flag created is false and skips any other checks. Because PMU emulation is gated only on the VCPU feature being set, this makes it possible for userspace to get away with setting the VCPU feature but not doing any initialization for the PMU. Fix it by returning an error when trying to run the VCPU if the PMU hasn't been initialized correctly. The PMU is marked as created only if the interrupt ID has been set when using an in-kernel irqchip. This means the same check in kvm_arm_pmu_v3_enable() is redundant, remove it. Signed-off-by: Alexandru Elisei <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-11-27KVM: arm64: Add kvm_vcpu_has_pmu() helperMarc Zyngier2-5/+6
There are a number of places where we check for the KVM_ARM_VCPU_PMU_V3 feature. Wrap this check into a new kvm_vcpu_has_pmu(), and use it at the existing locations. No functional change. Reviewed-by: Alexandru Elisei <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2020-11-27Merge branch 'kvm-arm64/host-hvc-table' into kvmarm-master/nextMarc Zyngier8-117/+241
Signed-off-by: Marc Zyngier <[email protected]>
2020-11-27Merge branch 'kvm-arm64/copro-no-more' into kvmarm-master/nextMarc Zyngier10-274/+151
Signed-off-by: Marc Zyngier <[email protected]>
2020-11-27Merge branch 'kvm-arm64/el2-pc' into kvmarm-master/nextMarc Zyngier21-737/+666
Signed-off-by: Marc Zyngier <[email protected]>
2020-11-27KVM: arm64: Avoid repetitive stack access on host EL1 to EL2 exceptionMarc Zyngier1-3/+3
Registers x0/x1 get repeateadly pushed and poped during a host HVC call. Instead, leave the registers on the stack, trading a store instruction on the fast path for an add on the slow path. Reviewed-by: Alexandru Elisei <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2020-11-27KVM: arm64: Simplify __kvm_enable_ssbs()Marc Zyngier4-14/+6
Move the setting of SSBS directly into the HVC handler, using the C helpers rather than the inline asssembly code. Reviewed-by: Alexandru Elisei <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2020-11-27KVM: arm64: Patch kimage_voffset instead of loading the EL1 valueMarc Zyngier4-7/+30
Directly using the kimage_voffset variable is fine for now, but will become more problematic as we start distrusting EL1. Instead, patch the kimage_voffset into the HYP text, ensuring we don't have to load an untrusted value later on. Signed-off-by: Marc Zyngier <[email protected]>
2020-11-27arm64: dts: mt8183: Add display nodes for MT8183Enric Balletbo i Serra1-0/+114
Add display subsystem device nodes to allow video output. Signed-off-by: Enric Balletbo i Serra <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2020-11-27arm64: dts: mt8183: Add iommu and larb nodesEnric Balletbo i Serra1-0/+79
Add iommu and larb nodes to the MT8183. Signed-off-by: Enric Balletbo i Serra <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2020-11-27arm64: dts: mt8183: Add dsi nodeJitao Shi1-0/+31
Add dsi and mipitx nodes to the MT8183. Signed-off-by: Jitao Shi <[email protected]> Signed-off-by: Enric Balletbo i Serra <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2020-11-27arm64: dts: mt8183: Add pwm and backlight nodeHsin-Yi Wang2-0/+38
Add pwm to mt8183 and backlight to mt8183-kukui. Signed-off-by: Hsin-Yi Wang <[email protected]> Tested-by: Enric Balletbo i Serra <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2020-11-27arm64: dts: mediatek: Add mt8183 power domains controllerMatthias Brugger1-0/+162
Add power domains controller node for SoC mt8183 Signed-off-by: Matthias Brugger <[email protected]> Signed-off-by: Enric Balletbo i Serra <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2020-11-27arm64: dts: mediatek: Add smi_common node for MT8183Enric Balletbo i Serra1-0/+10
The SMI (Smart Multimedia Interface) Common is a bridge between the m4u (Multimedia Memory Management Unit) and the Multimedia HW. This block is needed to support different multimedia features, like display, video decode, and camera. Also is needed to control the power domains of such HW blocks. Signed-off-by: Enric Balletbo i Serra <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2020-11-27arm64: dts: mediatek: Add mt8173 power domain controllerEnric Balletbo i Serra1-49/+115
Add power domain controller node for SoC mt8173. Signed-off-by: Enric Balletbo i Serra <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2020-11-27Merge branch 'linus' into sched/core, to resolve semantic conflictIngo Molnar81-325/+531
Signed-off-by: Ingo Molnar <[email protected]>
2020-11-27arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and MakefileSeiya Wang3-0/+542
Add basic chip support for Mediatek MT8192 Signed-off-by: Seiya Wang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2020-11-27arm64: dts: mediatek: add MT8167 pumpkin board dtsFabien Parent2-0/+21
The pumpkin board is made by Gossamer Engineering and is using a MediaTek SoC. The board currently comes in two available version: MT8516 SoC and MT8167 SoC. The board provides the following IOs: eMMC, NAND, SD card, USB type-A, Ethernet, Wi-Fi, Bluetooth, Audio (jack out, 2 PDM port, 1 analog in), serial over USB, HDMI, DSI, CSI, and an expansion header. The board can be powered by battery and/or via a USB Type-C port and is using a PMIC MT6392. The eMMC and NAND are sharing pins and cannot be used together. This commit is adding the basic boot support for the Pumpkin MT8167 board. Signed-off-by: Fabien Parent <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2020-11-27arm64: dts: mediatek: add dtsi for MT8167Fabien Parent2-0/+805
The MT8167 SoC provides the following peripherals: GPIO, UART, USB2, SPI, eMMC, SDIO, NAND, Flash, ADC, I2C, PWM, TImers, IR, Ethernet, Audio (I2S, SPDIF, TDM, HDMI), HDMI, DSI, CSI, MDP (Multimedia Data Path), Video encoding (H.264), Video Decoding (H.264, VP8). The MT8167 is compatible with MT8516 but provides multimedia IPs to it. This commit is just adding the basic dtsi file with the support of the following IOs: GPIO, Clocks. Signed-off-by: Fabien Parent <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2020-11-27arm64: dts: mediatek: mt8516: add efuse nodeFabien Parent1-0/+7
Add node to support e-fuses on MT8516 Signed-off-by: Fabien Parent <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
2020-11-27arm64: dts: renesas: r8a77951: Add PCIe EP nodesYuya Hamamachi1-0/+38
Add PCIe EP nodes for R8A77951 SoC dtsi. Signed-off-by: Yuya Hamamachi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-11-27crypto: hisilicon/trng - add HiSilicon TRNG driver supportWeili Qian1-0/+1
Move existing char/hw_random/hisi-trng-v2.c to crypto/hisilicon/trng.c. Signed-off-by: Weili Qian <[email protected]> Reviewed-by: Zaibo Xu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2020-11-26Merge tag 'hisi-arm64-dt-for-5.11' of git://github.com/hisilicon/linux-hisi ↵Arnd Bergmann7-133/+132
into arm/dt ARM64: DT: Hisilicon ARM64 DT updates for 5.11 - Cleanups of the hisilicon DTS to align with the dtschema. All of them do not have any functional effect except passing dtschema checks or dtc W=2 builds. * tag 'hisi-arm64-dt-for-5.11' of git://github.com/hisilicon/linux-hisi: arm64: dts: hisilicon: Use generic "ngpios" rather than "snps,nr-gpios" arm64: dts: hi3660: Harmonize DWC USB3 DT nodes name arm64: dts: hisilicon: list all clocks required by snps-dw-apb-uart.yaml arm64: dts: hisilicon: list all clocks required by pl011.yaml arm64: dts: hisilicon: list all clocks required by spi-pl022.yaml arm64: dts: hisilicon: normalize the node name of the UART devices arm64: dts: hisilicon: normalize the node name of the usb devices arm64: dts: hisilicon: normalize the node name of the SMMU devices arm64: dts: hisilicon: place clock-names "biu" before "ciu" arm64: dts: hisilicon: remove unused property pinctrl-names arm64: dts: hisilicon: write the values of property-units into a uint32 array arm64: dts: hisilicon: separate each group of data in the property "reg" arm64: dts: hisilicon: normalize the node name of the ITS devices Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2020-11-26Merge tag 'tegra-for-5.10-arm64-dt-fixes' of ↵Arnd Bergmann5-27/+15
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/fixes arm64: tegra: Device tree fixes for v5.10-rc6 This contains a couple of fixes to device trees. Among other things, this restores suspend/resume on Jetson TX2 and makes USB OTG work on Jetson TX1. * tag 'tegra-for-5.10-arm64-dt-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Fix Tegra234 VDK node names arm64: tegra: Wrong AON HSP reg property size arm64: tegra: Fix USB_VBUS_EN0 regulator on Jetson TX1 arm64: tegra: Correct the UART for Jetson Xavier NX arm64: tegra: Disable the ACONNECT for Jetson TX2 Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2020-11-26Merge tag 'zynqmp-soc-fixes-for-v5.10-rc6' of ↵Arnd Bergmann18-123/+153
https://github.com/Xilinx/linux-xlnx into arm/fixes arm64: soc: ZynqMP SoC fixes for v5.10-rc6 - Fix SD dll reset issue by using proper macro - Fix PM feature checking for Xilinx Versal SoC * tag 'zynqmp-soc-fixes-for-v5.10-rc6' of https://github.com/Xilinx/linux-xlnx: (337 commits) firmware: xilinx: Use hash-table for api feature check firmware: xilinx: Fix SD DLL node reset issue Linux 5.10-rc4 kvm: mmu: fix is_tdp_mmu_check when the TDP MMU is not in use afs: Fix afs_write_end() when called with copied == 0 [ver #3] ocfs2: initialize ip_next_orphan panic: don't dump stack twice on warn hugetlbfs: fix anon huge page migration race mm: memcontrol: fix missing wakeup polling thread kernel/watchdog: fix watchdog_allowed_mask not used warning reboot: fix overflow parsing reboot cpu number Revert "kernel/reboot.c: convert simple_strtoul to kstrtoint" compiler.h: fix barrier_data() on clang mm/gup: use unpin_user_pages() in __gup_longterm_locked() mm/slub: fix panic in slab_alloc_node() mailmap: fix entry for Dmitry Baryshkov/Eremin-Solenikov mm/vmscan: fix NR_ISOLATED_FILE corruption on 64-bit mm/compaction: stop isolation if too many pages are isolated and we have pages to migrate mm/compaction: count pages and stop correctly during page isolation drm/nouveau/kms/nv50-: Use atomic encoder callbacks everywhere ... Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2020-11-26arm64: dts: qcom: sdm845: use GIC_SPI for IPA interruptsAlex Elder1-2/+2
Use GIC_SPI rather than 0 in the specifiers for the two ARM GIC interrupts used by IPA. Signed-off-by: Alex Elder <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-11-26arm64: dts: qcom: sc7180: use GIC_SPI for IPA interruptsAlex Elder1-2/+2
Use GIC_SPI rather than 0 in the specifiers for the two ARM GIC interrupts used by IPA. Signed-off-by: Alex Elder <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-11-26arm64: dts: qcom: sc7180: limit IPA iommu streamsAlex Elder1-1/+2
Recently we learned that Android and Windows firmware don't seem to like using 3 as an iommu mask value for IPA. A simple fix was to specify exactly the streams needed explicitly, rather than implying a range with the mask. Make the same change for the SC7180 platform. See also: https://lore.kernel.org/linux-arm-msm/[email protected]/ Fixes: d82fade846aa8 ("arm64: dts: qcom: sc7180: add IPA information") Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Alex Elder <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-11-26arm64: dts: qcom: sm8150: Add Coresight supportSai Prakash Ranjan1-0/+591
Add coresight components found on Qualcomm Technologies, Inc. SM8150 SoC. Signed-off-by: Sai Prakash Ranjan <[email protected]> Reviewed-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-11-26arm64: tegra: Fix Tegra194 HDA {clock,reset}-names orderingSameer Pujar1-6/+6
As per the HDA binding doc reorder {clock,reset}-names entries for Tegra194. This also serves as a preparation for converting existing binding doc to json-schema. Signed-off-by: Sameer Pujar <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-11-26arm64: tegra: Enable AHCI on Jetson TX2Sowjanya Komatineni2-0/+32
This patch enables AHCI on Jetson TX2. Signed-off-by: Sowjanya Komatineni <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-11-26arm64: tegra: Change order of SATA resets for Tegra132 and Tegra210Sowjanya Komatineni2-6/+6
Tegra AHCI dt-binding doc is converted from text based to yaml based. dtbs_check valdiation strictly follows reset-names order specified in yaml dt-binding. Tegra124 thru Tegra210 has 3 resets sata, sata-oob and sata-cold. Tegra186 has 2 resets sata and sata-cold. This patch changes order of SATA resets to maintain proper resets order for commonly available resets across Tegra124 thru Tegra186 for dtbs_check to pass. Signed-off-by: Sowjanya Komatineni <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-11-26arm64: tegra: Add XUSB pad controller interruptJC Kuo3-0/+3
This commit adds "interrupts" property to Tegra210/Tegra186/Tegra194 XUSB PADCTL node. XUSB PADCTL interrupt will be raised when USB wake event happens. This is required for supporting XUSB host controller ELPG. Signed-off-by: JC Kuo <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-11-25arm64: dts: qcom: sc7180-trogdor: Make pp3300_a the default supply for ↵Matthias Kaehlcke4-3/+64
pp3300_hub The trogdor design has two options for supplying the 'pp3300_hub' power rail, it can be supplied by 'pp3300_l7c' or 'pp3300_a'. The 'pp3300_a' path includes a load switch that can be controlled through GPIO84. Initially trogdor boards used 'pp3300_l7c' to power the USB hub, newer revisions (will) use 'pp3300_a' as supply for 'pp3300_hub'. Add a DT node for the 'pp3300_a' path and a pinctrl entry for the GPIO. Make this path the default and keep trogdor rev1, lazor rev0 and rev1 on 'pp3300_l7c'. These earlier revisions also allocated the GPIO to the purpose of controlling the power switch, so there is no need to limit the pinctrl config to newer revisions. Remove the platform-wide 'always/boot-on' properties from 'pp3300_l7c' and add them to the boards that use this supply. Also delete the 'always/boot-on' properties of 'pp3300_hub' for these boards. Signed-off-by: Matthias Kaehlcke <[email protected]> Reviewed-by: Douglas Anderson <[email protected]> Link: https://lore.kernel.org/r/20201124164714.v4.1.I0ed4abdd2b2916fbedf76be254bc3457fb8b9655@changeid Signed-off-by: Bjorn Andersson <[email protected]>
2020-11-25arm64: add config for Broadcom BCM4908 SoCsRafał Miłecki2-0/+9
Add ARCH_BCM4908 config that can be used for compiling DTS files. Signed-off-by: Rafał Miłecki <[email protected]> Signed-off-by: Florian Fainelli <[email protected]>
2020-11-25arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS filesRafał Miłecki4-0/+256
They don't descibe hardware fully yet but it's enough to boot a system. Some missing blocks: 1. PMC (Power Management Controller?) 2. Ethernet 3. Crypto 4. Thermal Asus DTS is missing defining full NAND partitions layout and buttons. Further changes will fill those gaps as soon as required bindings will be found / tested / added. Signed-off-by: Rafał Miłecki <[email protected]> Signed-off-by: Florian Fainelli <[email protected]>
2020-11-25kasan: arm64: set TCR_EL1.TBID1 when enabledPeter Collingbourne2-1/+2
On hardware supporting pointer authentication, we previously ended up enabling TBI on instruction accesses when tag-based ASAN was enabled, but this was costing us 8 bits of PAC entropy, which was unnecessary since tag-based ASAN does not require TBI on instruction accesses. Get them back by setting TCR_EL1.TBID1. Signed-off-by: Peter Collingbourne <[email protected]> Reviewed-by: Andrey Konovalov <[email protected]> Link: https://linux-review.googlesource.com/id/I3dded7824be2e70ea64df0aabab9598d5aebfcc4 Link: https://lore.kernel.org/r/20f64e26fc8a1309caa446fffcb1b4e2fe9e229f.1605952129.git.pcc@google.com Signed-off-by: Catalin Marinas <[email protected]>
2020-11-25arm64: Enable perf events based hard lockup detectorSumit Garg2-2/+41
With the recent feature added to enable perf events to use pseudo NMIs as interrupts on platforms which support GICv3 or later, its now been possible to enable hard lockup detector (or NMI watchdog) on arm64 platforms. So enable corresponding support. One thing to note here is that normally lockup detector is initialized just after the early initcalls but PMU on arm64 comes up much later as device_initcall(). So we need to re-initialize lockup detection once PMU has been initialized. Signed-off-by: Sumit Garg <[email protected]> Acked-by: Alexandru Elisei <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Will Deacon <[email protected]>
2020-11-25arm64: tegra: Rename ADMA device nodes for Tegra210Sameer Pujar4-4/+4
DMA device nodes should follow regex pattern of "^dma-controller(@.*)?$". This is a preparatory patch to use YAML doc format for ADMA. Signed-off-by: Sameer Pujar <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-11-25arm64: tegra: Hook up edp interrupt on Tegra132 SOCTHERMThierry Reding1-1/+3
For some reason this was never hooked up. Do it now so that over-current interrupts can be logged. Reported-by: Nicolas Chauvet <[email protected]> Suggested-by: Jon Hunter <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-11-25arm64: tegra: Add missing hot temperatures to Tegra210 thermal-zonesNicolas Chauvet1-0/+12
According to dmesg, thermal-zones for mem and cpu are missing hot temperatures properties. throttrip: pll: missing hot temperature ... throttrip: mem: missing hot temperature ... Adding them will clear the messages. Signed-off-by: Nicolas Chauvet <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-11-25arm64: tegra: Add missing gpu-throt-level to Tegra210 socthermNicolas Chauvet1-0/+1
On Jetson TX1 the following message can be seen: tegra_soctherm 700e2000.thermal-sensor: throttle-cfg: heavy: no throt prop or invalid prop This patch will fix the invalid prop issue according to the binding. Signed-off-by: Nicolas Chauvet <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-11-25arm64: tegra: Add missing hot temperatures to Tegra132 thermal-zonesNicolas Chauvet1-0/+10
According to dmesg, thermal-zones for mem and cpu are missing hot temperatures properties. throttrip: pll: missing hot temperature ... throttrip: mem: missing hot temperature ... Adding them will clear the messages. Signed-off-by: Nicolas Chauvet <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-11-25arm64: tegra: Fix DT binding for IO High Voltage entryVidya Sagar1-2/+2
Fix the device-tree entry that represents I/O High Voltage property by replacing 'nvidia,io-high-voltage' with 'nvidia,io-hv' as the former entry is deprecated. Fixes: dbb72e2c305b ("arm64: tegra: Add configuration for PCIe C5 sideband signals") Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-11-25arm64: tegra: Fix GIC400 missing GICH/GICV register regionsMarc Zyngier1-1/+3
GIC400 has full support for virtualization, and yet the tegra186 DT doesn't expose the GICH/GICV regions (despite exposing the maintenance interrupt that only makes sense for virtualization). Add the missing regions, based on the hunch that the HW doesn't use the CPU build-in interfaces, but instead the external ones provided by the GIC. KVM's virtual GIC now works with this change. Signed-off-by: Marc Zyngier <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-11-25arm64: tegra: Add missing CPU PMUs on Tegra186Marc Zyngier1-6/+22
Add the description of CPU PMUs for both the Denver and A57 clusters, which enables the perf subsystem. Signed-off-by: Marc Zyngier <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-11-25arm64: tegra: Fix Tegra234 VDK node namesJon Hunter1-3/+3
When the device-tree board file was added for the Tegra234 VDK simulator it incorrectly used the names 'cbb' and 'sdhci' instead of 'bus' and 'mmc', respectively. The names 'bus' and 'mmc' are required by the device-tree json-schema validation tools. Therefore, fix this by renaming these nodes accordingly. Fixes: 639448912ba1 ("arm64: tegra: Initial Tegra234 VDK support") Reported-by: Ashish Singhal <[email protected]> Signed-off-by: Jon Hunter <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-11-25arm64: tegra: Wrong AON HSP reg property sizeDipen Patel1-1/+1
The AON HSP node's "reg" property size 0xa0000 will overlap with other resources. This patch fixes that wrong value with correct size 0x90000. Reviewed-by: Mikko Perttunen <[email protected]> Signed-off-by: Dipen Patel <[email protected]> Fixes: a38570c22e9d ("arm64: tegra: Add nodes for TCU on Tegra194") Signed-off-by: Thierry Reding <[email protected]>
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