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2022-07-05arm64: errata: Add Cortex-A510 to the repeat tlbi listJames Morse1-1/+7
2022-07-05arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 definition namesMark Brown2-19/+19
2022-07-05arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition namesMark Brown2-49/+49
2022-07-05arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fieldsMark Brown1-19/+19
2022-07-05arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enumsMark Brown1-16/+16
2022-07-05arm64/sysreg: Standardise naming for WFxT definesMark Brown1-4/+4
2022-07-05arm64/sysreg: Make BHB clear feature defines match the architectureMark Brown1-1/+1
2022-07-05arm64/sysreg: Align pointer auth enumeration defines with architectureMark Brown1-12/+12
2022-07-05arm64/mte: Standardise GMID field name definitionsMark Brown1-1/+1
2022-07-05arm64/sysreg: Standardise naming for DCZID_EL0 field namesMark Brown1-2/+2
2022-07-05arm64/sysreg: Standardise naming for CTR_EL0 fieldsMark Brown5-21/+21
2022-07-05arm64/idreg: Fix tab/space damageMark Brown1-7/+7
2022-07-05arm64/cpuinfo: Remove references to reserved cache typeMark Brown1-8/+15
2022-07-04arm64: topology: Remove redundant setting of llc_id in CPU topologySudeep Holla1-14/+0
2022-07-04arm64: fix oops in concurrently setting insn_emulation sysctlshaibinzhang (张海斌)1-4/+5
2022-07-01arm64: Add an override for ID_AA64SMFR0_EL1.FA64Marc Zyngier2-7/+19
2022-07-01arm64: Add the arm64.nosve command line optionMarc Zyngier3-2/+43
2022-07-01arm64: Add the arm64.nosme command line optionMarc Zyngier3-1/+61
2022-07-01arm64: Expose a __check_override primitive for oddball featuresMarc Zyngier1-6/+11
2022-07-01arm64: Allow the idreg override to deal with variable field widthMarc Zyngier1-12/+16
2022-07-01arm64: Factor out checking of a feature against the override into a macroMarc Zyngier1-14/+20
2022-07-01arm64: Allow sticky E2H when entering EL1Marc Zyngier1-24/+10
2022-07-01arm64: Save state of HCR_EL2.E2H before switch to EL1Marc Zyngier2-5/+13
2022-07-01arm64: Rename the VHE switch to "finalise_el2"Marc Zyngier3-15/+14
2022-07-01arm64: mm: fix booting with 52-bit address spaceArd Biesheuvel1-0/+18
2022-07-01arm64: vdso32: Add DWARF_DEBUGNathan Chancellor1-0/+1
2022-07-01arm64: vdso32: Shuffle .ARM.exidx section above ELF_DETAILSNathan Chancellor1-1/+1
2022-07-01arm64: compat: Move sigreturn32.S to .rodata sectionChen Zhongjin1-0/+1
2022-06-29arm64/fpsimd: Remove duplicate SYS_SVCR readSchspa Shi1-1/+0
2022-06-29arm64: head: remove __PHYS_OFFSETMark Rutland1-8/+3
2022-06-29arm64: lds: use PROVIDE instead of conditional definitionsArd Biesheuvel1-32/+31
2022-06-28arm64: vdso*: place got/plt sections in .rodataJoey Gouly2-20/+15
2022-06-28arm64: vdso32: add ARM.exidx* sectionsJoey Gouly1-0/+1
2022-06-27arm64: mm: Convert to GENERIC_IOREMAPKefeng Wang1-1/+1
2022-06-27arm64: Copy the task argument to unwind_stateMadhavan T. Venkataraman1-13/+20
2022-06-27arm64: Split unwind_init()Madhavan T. Venkataraman1-11/+55
2022-06-27arm64/signal: Clean up SVE/SME feature checking inconsistencyMark Brown1-8/+12
2022-06-24arm64: setup: drop early FDT pointer helpersArd Biesheuvel2-17/+0
2022-06-24arm64: head: avoid relocating the kernel twice for KASLRArd Biesheuvel6-140/+171
2022-06-24arm64: kaslr: defer initialization to initcall where permittedArd Biesheuvel1-55/+40
2022-06-24arm64: head: record CPU boot mode after enabling the MMUArd Biesheuvel2-39/+15
2022-06-24arm64: head: populate kernel page tables with MMU and caches onArd Biesheuvel1-46/+16
2022-06-24arm64: head: factor out TTBR1 assignment into a macroArd Biesheuvel1-4/+1
2022-06-24arm64: idreg-override: use early FDT mapping in ID mapArd Biesheuvel2-11/+7
2022-06-24arm64: head: create a temporary FDT mapping in the initial ID mapArd Biesheuvel1-1/+13
2022-06-24arm64: head: use relative references to the RELA and RELR tablesArd Biesheuvel2-17/+8
2022-06-24arm64: head: cover entire kernel image in initial ID mapArd Biesheuvel2-12/+26
2022-06-24arm64: head: add helper function to remap regions in early page tablesArd Biesheuvel1-0/+33
2022-06-24arm64: mm: provide idmap pointer to cpu_replace_ttbr1()Ard Biesheuvel2-2/+2
2022-06-24arm64: head: pass ID map root table address to __enable_mmu()Ard Biesheuvel2-6/+9
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