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Use descriptive definitions for the Tauros2 register bits, and while
we're here, clean up the "Tauros2: %s line fill burt8." message.
Signed-off-by: Russell King <[email protected]>
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Signed-off-by: Russell King <[email protected]>
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Convert many (but not all) printk(KERN_* to pr_* to simplify the code.
We take the opportunity to join some printk lines together so we don't
split the message across several lines, and we also add a few levels
to some messages which were previously missing them.
Tested-by: Andrew Lunn <[email protected]>
Tested-by: Felipe Balbi <[email protected]>
Signed-off-by: Russell King <[email protected]>
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When building a kernel with support for both ARMv6 and ARMv7 but
no MMU, the call from tauros2_internal_init to adjust_cr causes
a link error. While that could probably be resolved, we don't
actually support cache-tauros2 on ARMv6 any more. All PJ4 CPU
implementations support both ARMv6 and ARMv7 and we already assume
that we are using them only in ARMv7 mode.
Removing the ARMv6 code path reduces the code size and avoids
the linker error.
Signed-off-by: Arnd Bergmann <[email protected]>
Acked-by: Haojian Zhuang <[email protected]>
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Signed-off-by: Chao Xie <[email protected]>
Signed-off-by: Haojian Zhuang <[email protected]>
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The extra feature may be used by SOCs are prefetch, burst8,
write buffer coalesce
Signed-off-by: Chao Xie <[email protected]>
Signed-off-by: Haojian Zhuang <[email protected]>
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Signed-off-by: Chao Xie <[email protected]>
Signed-off-by: Haojian Zhuang <[email protected]>
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init the variable "mode" to NULL to ensure the later NULL checking is
taking effect.
Signed-off-by: Chao Xie <[email protected]>
Signed-off-by: Haojian Zhuang <[email protected]>
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For the SOC chips using tauros2 cache, will need disable
and resume tauros2 cache for SOC suspend/resume.
Signed-off-by: Chao Xie <[email protected]>
Signed-off-by: Haojian Zhuang <[email protected]>
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Avoid namespace conflicts with drivers over the CP15 definitions by
moving CP15 related prototypes and definitions to a private header
file.
Acked-by: Stephen Warren <[email protected]>
Tested-by: Stephen Warren <[email protected]> [Tegra]
Acked-by: H Hartley Sweeten <[email protected]>
Tested-by: H Hartley Sweeten <[email protected]> [EP93xx]
Acked-by: Nicolas Pitre <[email protected]>
Acked-by: Kukjin Kim <[email protected]>
Signed-off-by: Russell King <[email protected]>
Signed-off-by: David Howells <[email protected]>
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Support for the Tauros2 L2 cache controller as used with the PJ1
and PJ4 CPUs.
Signed-off-by: Lennert Buytenhek <[email protected]>
Signed-off-by: Saeed Bishara <[email protected]>
Signed-off-by: Nicolas Pitre <[email protected]>
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