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In 5388a6b266 ("ARM: SMP: Always enable clock event broadcast support")
Russell noted that "the TWD local timers are unable to wake up the CPU
when it is placed into a low power mode".
However, some platforms do not stop the TWD block in low-power mode,
and can thus use the TWD timer in one-shot mode, without setting up
a broadcast device.
Make the driver check for the "always-on" boolean property, and set
the CLOCK_EVT_FEAT_C3STOP flag accordingly.
Acked-by: Mark Rutland <[email protected]>
Signed-off-by: Marc Gonzalez <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Currently on ARM when <SysRq-L> is triggered from an interrupt handler
(e.g. a SysRq issued using UART or kbd) the main CPU will wedge for ten
seconds with interrupts masked before issuing a backtrace for every CPU
except itself.
The new backtrace code introduced by commit 96f0e00378d4 ("ARM: add
basic support for on-demand backtrace of other CPUs") does not work
correctly when run from an interrupt handler because IPI_CPU_BACKTRACE
is used to generate the backtrace on all CPUs but cannot preempt the
current calling context.
This can be fixed by detecting that the calling context cannot be
preempted and issuing the backtrace directly in this case. Issuing
directly leaves us without any pt_regs to pass to nmi_cpu_backtrace()
so we also modify the generic code to call dump_stack() when its
argument is NULL.
Acked-by: Hillf Danton <[email protected]>
Acked-by: Thomas Gleixner <[email protected]>
Signed-off-by: Daniel Thompson <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Dumping registers from other sleeping tasks in KGDB was totally
failing for me. All registers were reported as 0 in many cases.
The code was using task_pt_regs(task) to try to get other thread
registers. This doesn't appear to be the right place to look. From
my tests, I saw non-zero values in this structure when we were looking
at a kernel thread that had a userspace task associated with it, but
it contained the register values from the userspace task. So even in
the cases where registers weren't reported as 0 we were still not
showing the right thing.
Instead of using task_pt_regs(task) let's use task_thread_info(task).
This is the same place that is referred to when doing a dump of all
sleeping task stacks (kdb_show_stack() -> show_stack() ->
dump_backtrace() -> unwind_backtrace() -> thread_saved_sp()).
As further evidence that this is the right thing to do, you can find
the following comment in "gdbstub.c" right before it calls
sleeping_thread_to_gdb_regs():
Pull stuff saved during switch_to; nothing else is accessible (or
even particularly relevant). This should be enough for a stack
trace.
...and if you look at switch_to() it only saves r4-r11, sp and lr.
Those are the same registers that I'm getting out of the
task_thread_info().
With this change you can use "info thread" to see all tasks in the
kernel and you can switch to other tasks and examine them in gdb.
Signed-off-by: Doug Anderson <[email protected]>
Tested-by: Stephen Boyd <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Mark Brand reports that a NEEDS_SYSCALL_FOR_CMPXCHG enabled kernel would
open a security hole in the ghost syscall used to implement cmpxchg, as
it fails to validate the user pointer.
However, in order for this option to be enabled, you'd need to be
building a pre-ARMv6 kernel with SMP support. There is only one system
known which fits that, which is an early ARM SMP FPGA implementation
based on the ARM926T.
In any case, the Kconfig does not allow SMP to be enabled for pre-ARMv6
systems.
Moreover, even if NEEDS_SYSCALL_FOR_CMPXCHG were to be enabled, the
kernel would not build as __ARM_NR_cmpxchg64 is not defined.
The simple answer is to remove the buggy code.
Reported-by: Mark Brand <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Header <asm/kdebug.h> is not needed for arm/hw_breakpoint.c, so remove
the pointless #include.
Signed-off-by: Maninder Singh <[email protected]>
Reviewed-by: Vaneet Narang <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
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no-op for nosmp"
This reverts commit 904464b91eca8c665acea033489225af02eeb75a.
The problem pointed out by commit 904464b91eca ("ARM: 7655/1:
smp_twd: make twd_local_timer_of_register() no-op for nosmp")
doesn't exist anymore.
We can safely boot with nosmp and the warning won't show up.
The other side benefit of this patch is that TWD has a chance
to probe on single-core A9 systems such as AM437x which sport
TWD.
While at that, also drop SMP dependency from TWD's Kconfig entry.
Cc: Shawn Guo <[email protected]>
Cc: Dirk Behme <[email protected]>
Acked-by: Tony Lindgren <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Seeing the 'of' characters in a symbol that is being called from
ACPI seems to freak out people. So let's do a bit of pointless
renaming so that these folks do feel at home.
Signed-off-by: Marc Zyngier <[email protected]>
Acked-by: Catalin Marinas <[email protected]>
Reviewed-by: Hanjun Guo <[email protected]>
Acked-by: Thomas Gleixner <[email protected]>
Tested-by: Hanjun Guo <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>
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This function just copies '*ops' to 'smp_ops', so the given
structure '*ops' is not modified at all.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Russell King <[email protected]>
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This patch adds imprecise abort enable/disable macros and uses them to
enable imprecise aborts early when starting the kernel.
This helps in tracking down the real cause for such imprecise abort, as
they are handled as soon as they occur. Until now those aborts would
only be enabled when entering the userspace and as a consequence crash
the first userspace process if any abort had been raised during kernel
startup.
Signed-off-by: Fabrice Gasnier <[email protected]>
Signed-off-by: Lucas Stach <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Wire up the new userfaultfd and membarrier syscalls for ARM.
Signed-off-by: Russell King <[email protected]>
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Pull ARM fixes from Russell King:
"Three fixes and a resulting cleanup for -rc2:
- Andre Przywara reported that he was seeing a warning with the new
cast inside DMA_ERROR_CODE's definition, and fixed the incorrect
use.
- Doug Anderson noticed that kgdb causes a "scheduling while atomic"
bug.
- OMAP5 folk noticed that their Thumb-2 compiled X servers crashed
when enabling support to cover ARMv6 CPUs due to a kernel bug
leaking some conditional context into the signal handler"
* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: 8425/1: kgdb: Don't try to stop the machine when setting breakpoints
ARM: 8437/1: dma-mapping: fix build warning with new DMA_ERROR_CODE definition
ARM: get rid of needless #if in signal handling code
ARM: fix Thumb2 signal handling when ARMv6 is enabled
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner:
"This is a rather large update post rc1 due to the final steps of
cleanups and API changes which had to wait for the preparatory patches
to hit your tree.
- Regression fixes for ARM GIC irqchips
- Regression fixes and lockdep anotations for renesas irq chips
- The leftovers of the cleanup and preparatory patches which have
been ignored by maintainers
- Final conversions of the newly merged users of obsolete APIs
- Final removal of obsolete APIs
- Final removal of ARM artifacts which had been introduced during the
conversion of ARM to the generic interrupt code.
- Final split of the irq_data into chip specific and common data to
reflect the needs of hierarchical irq domains.
- Treewide removal of the first argument of interrupt flow handlers,
i.e. the irq number, which is not used by the majority of handlers
and simple to retrieve from the other argument the irq descriptor.
- A few comment updates and build warning fixes"
* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (40 commits)
arm64: Remove ununsed set_irq_flags
ARM: Remove ununsed set_irq_flags
sh: Kill off set_irq_flags usage
irqchip: Kill off set_irq_flags usage
gpu/drm: Kill off set_irq_flags usage
genirq: Remove irq argument from irq flow handlers
genirq: Move field 'msi_desc' from irq_data into irq_common_data
genirq: Move field 'affinity' from irq_data into irq_common_data
genirq: Move field 'handler_data' from irq_data into irq_common_data
genirq: Move field 'node' from irq_data into irq_common_data
irqchip/gic-v3: Use IRQD_FORWARDED_TO_VCPU flag
irqchip/gic: Use IRQD_FORWARDED_TO_VCPU flag
genirq: Provide IRQD_FORWARDED_TO_VCPU status flag
genirq: Simplify irq_data_to_desc()
genirq: Remove __irq_set_handler_locked()
pinctrl/pistachio: Use irq_set_handler_locked
gpio: vf610: Use irq_set_handler_locked
powerpc/mpc8xx: Use irq_set_handler_locked()
powerpc/ipic: Use irq_set_handler_locked()
powerpc/cpm2: Use irq_set_handler_locked()
...
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In (23a4e40 arm: kgdb: Handle read-only text / modules) we moved to
using patch_text() to set breakpoints so that we could handle the case
when we had CONFIG_DEBUG_RODATA. That patch used patch_text().
Unfortunately, patch_text() assumes that we're not in atomic context
when it runs since it needs to grab a mutex and also wait for other
CPUs to stop (which it does with a completion).
This would result in a stack crawl if you had
CONFIG_DEBUG_ATOMIC_SLEEP and tried to set a breakpoint in kgdb. The
crawl looked something like:
BUG: scheduling while atomic: swapper/0/0/0x00010007
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.2.0-rc7-00133-geb63b34 #1073
Hardware name: Rockchip (Device Tree)
(unwind_backtrace) from [<c00133d4>] (show_stack+0x20/0x24)
(show_stack) from [<c05400e8>] (dump_stack+0x84/0xb8)
(dump_stack) from [<c004913c>] (__schedule_bug+0x54/0x6c)
(__schedule_bug) from [<c054065c>] (__schedule+0x80/0x668)
(__schedule) from [<c0540cfc>] (schedule+0xb8/0xd4)
(schedule) from [<c0543a3c>] (schedule_timeout+0x2c/0x234)
(schedule_timeout) from [<c05417c0>] (wait_for_common+0xf4/0x188)
(wait_for_common) from [<c0541874>] (wait_for_completion+0x20/0x24)
(wait_for_completion) from [<c00a0104>] (__stop_cpus+0x58/0x70)
(__stop_cpus) from [<c00a0580>] (stop_cpus+0x3c/0x54)
(stop_cpus) from [<c00a06c4>] (__stop_machine+0xcc/0xe8)
(__stop_machine) from [<c00a0714>] (stop_machine+0x34/0x44)
(stop_machine) from [<c00173e8>] (patch_text+0x28/0x34)
(patch_text) from [<c001733c>] (kgdb_arch_set_breakpoint+0x40/0x4c)
(kgdb_arch_set_breakpoint) from [<c00a0d68>] (kgdb_validate_break_address+0x2c/0x60)
(kgdb_validate_break_address) from [<c00a0e90>] (dbg_set_sw_break+0x1c/0xdc)
(dbg_set_sw_break) from [<c00a2e88>] (gdb_serial_stub+0x9c4/0xba4)
(gdb_serial_stub) from [<c00a11cc>] (kgdb_cpu_enter+0x1f8/0x60c)
(kgdb_cpu_enter) from [<c00a18cc>] (kgdb_handle_exception+0x19c/0x1d0)
(kgdb_handle_exception) from [<c0016f7c>] (kgdb_compiled_brk_fn+0x30/0x3c)
(kgdb_compiled_brk_fn) from [<c00091a4>] (do_undefinstr+0x1a4/0x20c)
(do_undefinstr) from [<c001400c>] (__und_svc_finish+0x0/0x34)
It turns out that when we're in kgdb all the CPUs are stopped anyway
so there's no reason we should be calling patch_text(). We can
instead directly call __patch_text() which assumes that CPUs have
already been stopped.
Fixes: 23a4e4050ba9 ("arm: kgdb: Handle read-only text / modules")
Reported-by: Aapo Vienamo <[email protected]>
Signed-off-by: Douglas Anderson <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Acked-by: Kees Cook <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Remove the #if statement which caused trouble for kernels that support
both ARMv6 and ARMv7. Older architectures do not implement these bits,
so it should be safe to always clear them.
Signed-off-by: Russell King <[email protected]>
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Now that all users of set_irq_flags and custom flags are converted to
genirq functions, the ARM specific set_irq_flags can be removed.
Signed-off-by: Rob Herring <[email protected]>
Tested-by: Kevin Hilman <[email protected]>
Cc: [email protected]
Cc: Russell King <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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When a kernel is built covering ARMv6 to ARMv7, we omit to clear the
IT state when entering a signal handler. This can cause the first
few instructions to be conditionally executed depending on the parent
context.
In any case, the original test for >= ARMv7 is broken - ARMv6 can have
Thumb-2 support as well, and an ARMv6T2 specific build would omit this
code too.
Relax the test back to ARMv6 or greater. This results in us always
clearing the IT state bits in the PSR, even on CPUs where these bits
are reserved. However, they're reserved for the IT state, so this
should cause no harm.
Cc: <[email protected]>
Fixes: d71e1352e240 ("Clear the IT state when invoking a Thumb-2 signal handler")
Acked-by: Tony Lindgren <[email protected]>
Tested-by: H. Nikolaus Schaller <[email protected]>
Tested-by: Grazvydas Ignotas <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Pull ARM fixes from Russell King:
"A number of fixes for the merge window, fixing a number of cases
missed when testing the uaccess code, particularly cases which only
show up with certain compiler versions"
* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: 8431/1: fix alignement of __bug_table section entries
arm/xen: Enable user access to the kernel before issuing a privcmd call
ARM: domains: add memory dependencies to get_domain/set_domain
ARM: domains: thread_info.h no longer needs asm/domains.h
ARM: uaccess: fix undefined instruction on ARMv7M/noMMU
ARM: uaccess: remove unneeded uaccess_save_and_disable macro
ARM: swpan: fix nwfpe for uaccess changes
ARM: 8429/1: disable GCC SRA optimization
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The use of get_domain() in copy_thread() results in an oops on
ARMv7M/noMMU systems. The thread cpu_domain value is only used when
CONFIG_CPU_USE_DOMAINS is enabled, so there's no need to save the
value in copy_thread() except when this is enabled, and this option
will never be enabled on these platforms.
Unhandled exception: IPSR = 00000006 LR = fffffff1
CPU: 0 PID: 0 Comm: swapper Not tainted 4.2.0-next-20150909-00001-gb8ec5ad #41
Hardware name: NXP LPC18xx/43xx (Device Tree)
task: 2823fbe0 ti: 2823c000 task.ti: 2823c000
PC is at copy_thread+0x18/0x92
LR is at copy_thread+0x19/0x92
pc : [<2800a46e>] lr : [<2800a46f>] psr: 4100000b
sp : 2823df00 ip : 00000000 fp : 287c81c0
r10: 00000000 r9 : 00800300 r8 : 287c8000
r7 : 287c8000 r6 : 2818908d r5 : 00000000 r4 : 287ca000
r3 : 00000000 r2 : 00000000 r1 : fffffff0 r0 : 287ca048
xPSR: 4100000b
Reported-by: Ariel D'Alessandro <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Pull NMI backtrace update from Russell King:
"These changes convert the x86 NMI handling to be a library
implementation which other architectures can make use of. Thomas
Gleixner has reviewed and tested these changes, and wishes me to send
these rather than taking them through the tip tree.
The final patch in the set adds an initial implementation using this
infrastructure to ARM, even though it doesn't send the IPI at "NMI"
level. Patches are in progress to add the ARM equivalent of NMI, but
we still need the IRQ-level fallback for systems where the "NMI" isn't
available due to secure firmware denying access to it"
* 'nmi' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: add basic support for on-demand backtrace of other CPUs
nmi: x86: convert to generic nmi handler
nmi: create generic NMI backtrace implementation
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Pull ARM development updates from Russell King:
"Included in this update:
- moving PSCI code from ARM64/ARM to drivers/
- removal of some architecture internals from global kernel view
- addition of software based "privileged no access" support using the
old domains register to turn off the ability for kernel
loads/stores to access userspace. Only the proper accessors will
be usable.
- addition of early fixup support for early console
- re-addition (and reimplementation) of OMAP special interconnect
barrier
- removal of finish_arch_switch()
- only expose cpuX/online in sysfs if hotpluggable
- a number of code cleanups"
* 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (41 commits)
ARM: software-based priviledged-no-access support
ARM: entry: provide uaccess assembly macro hooks
ARM: entry: get rid of multiple macro definitions
ARM: 8421/1: smp: Collapse arch_cpu_idle_dead() into cpu_die()
ARM: uaccess: provide uaccess_save_and_enable() and uaccess_restore()
ARM: mm: improve do_ldrd_abort macro
ARM: entry: ensure that IRQs are enabled when calling syscall_trace_exit()
ARM: entry: efficiency cleanups
ARM: entry: get rid of asm_trace_hardirqs_on_cond
ARM: uaccess: simplify user access assembly
ARM: domains: remove DOMAIN_TABLE
ARM: domains: keep vectors in separate domain
ARM: domains: get rid of manager mode for user domain
ARM: domains: move initial domain setting value to asm/domains.h
ARM: domains: provide domain_mask()
ARM: domains: switch to keeping domain value in register
ARM: 8419/1: dma-mapping: harmonize definition of DMA_ERROR_CODE
ARM: 8417/1: refactor bitops functions with BIT_MASK() and BIT_WORD()
ARM: 8416/1: Feroceon: use of_iomap() to map register base
ARM: 8415/1: early fixmap support for earlycon
...
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull locking and atomic updates from Ingo Molnar:
"Main changes in this cycle are:
- Extend atomic primitives with coherent logic op primitives
(atomic_{or,and,xor}()) and deprecate the old partial APIs
(atomic_{set,clear}_mask())
The old ops were incoherent with incompatible signatures across
architectures and with incomplete support. Now every architecture
supports the primitives consistently (by Peter Zijlstra)
- Generic support for 'relaxed atomics':
- _acquire/release/relaxed() flavours of xchg(), cmpxchg() and {add,sub}_return()
- atomic_read_acquire()
- atomic_set_release()
This came out of porting qwrlock code to arm64 (by Will Deacon)
- Clean up the fragile static_key APIs that were causing repeat bugs,
by introducing a new one:
DEFINE_STATIC_KEY_TRUE(name);
DEFINE_STATIC_KEY_FALSE(name);
which define a key of different types with an initial true/false
value.
Then allow:
static_branch_likely()
static_branch_unlikely()
to take a key of either type and emit the right instruction for the
case. To be able to know the 'type' of the static key we encode it
in the jump entry (by Peter Zijlstra)
- Static key self-tests (by Jason Baron)
- qrwlock optimizations (by Waiman Long)
- small futex enhancements (by Davidlohr Bueso)
- ... and misc other changes"
* 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (63 commits)
jump_label/x86: Work around asm build bug on older/backported GCCs
locking, ARM, atomics: Define our SMP atomics in terms of _relaxed() operations
locking, include/llist: Use linux/atomic.h instead of asm/cmpxchg.h
locking/qrwlock: Make use of _{acquire|release|relaxed}() atomics
locking/qrwlock: Implement queue_write_unlock() using smp_store_release()
locking/lockref: Remove homebrew cmpxchg64_relaxed() macro definition
locking, asm-generic: Add _{relaxed|acquire|release}() variants for 'atomic_long_t'
locking, asm-generic: Rework atomic-long.h to avoid bulk code duplication
locking/atomics: Add _{acquire|release|relaxed}() variants of some atomic operations
locking, compiler.h: Cast away attributes in the WRITE_ONCE() magic
locking/static_keys: Make verify_keys() static
jump label, locking/static_keys: Update docs
locking/static_keys: Provide a selftest
jump_label: Provide a self-test
s390/uaccess, locking/static_keys: employ static_branch_likely()
x86, tsc, locking/static_keys: Employ static_branch_likely()
locking/static_keys: Add selftest
locking/static_keys: Add a new static_key interface
locking/static_keys: Rework update logic
locking/static_keys: Add static_key_{en,dis}able() helpers
...
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Conflicts:
drivers/perf/arm_pmu.c
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for-linus
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Olof Johansson:
"A large cleanup branch this release, with a healthy 10k negative line
delta.
Most of this is removal of legacy (non-DT) support of shmobile
platforms. There is also removal of two non-DT platforms on OMAP, and
the plat-samsung directory is cleaned out by moving most of the
previously shared-location-but-not-actually-shared files from there to
the appropriate mach directories instead.
There are other sets of changes in here as well:
- Rob Herring removed use of set_irq_flags under all platforms and
moved to genirq alternatives
- a series of timer API conversions to set-state interface
- ep93xx, nomadik and ux500 cleanups from Linus Walleij
- __init annotation fixes from Nicolas Pitre
+ a bunch of other changes that all add up to a nice set of cleanups"
* tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (108 commits)
ARM/fb: ep93xx: switch framebuffer to use modedb only
ARM: gemini: Setup timer3 as free running timer
ARM: gemini: Use timer1 for clockevent
ARM: gemini: Add missing register definitions for gemini timer
ARM: ep93xx/timer: Migrate to new 'set-state' interface
ARM: nomadik: push accelerometer down to boards
ARM: nomadik: move l2x0 setup to device tree
ARM: nomadik: selectively enable UART0 on boards
ARM: nomadik: move hog code to use DT hogs
ARM: shmobile: Fix mismerges
ARM: ux500: simplify secondary CPU boot
ARM: SAMSUNG: remove keypad-core header in plat-samsung
ARM: SAMSUNG: local watchdog-reset header in mach-s3c64xx
ARM: SAMSUNG: local onenand-core header in mach-s3c64xx
ARM: SAMSUNG: local irq-uart header in mach-s3c64xx
ARM: SAMSUNG: local backlight header in mach-s3c64xx
ARM: SAMSUNG: local ata-core header in mach-s3c64xx
ARM: SAMSUNG: local regs-usb-hsotg-phy header in mach-s3c64xx
ARM: SAMSUNG: local spi-core header in mach-s3c24xx
ARM: SAMSUNG: local nand-core header in mach-s3c24xx
...
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git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas:
"PCI changes for the v4.3 merge window:
Enumeration:
- Allocate ATS struct during enumeration (Bjorn Helgaas)
- Embed ATS info directly into struct pci_dev (Bjorn Helgaas)
- Reduce size of ATS structure elements (Bjorn Helgaas)
- Stop caching ATS Invalidate Queue Depth (Bjorn Helgaas)
- iommu/vt-d: Cache PCI ATS state and Invalidate Queue Depth (Bjorn Helgaas)
- Move MPS configuration check to pci_configure_device() (Bjorn Helgaas)
- Set MPS to match upstream bridge (Keith Busch)
- ARM/PCI: Set MPS before pci_bus_add_devices() (Murali Karicheri)
- Add pci_scan_root_bus_msi() (Lorenzo Pieralisi)
- ARM/PCI, designware, xilinx: Use pci_scan_root_bus_msi() (Lorenzo Pieralisi)
Resource management:
- Call pci_read_bridge_bases() from core instead of arch code (Lorenzo Pieralisi)
PCI device hotplug:
- pciehp: Remove unused interrupt events (Bjorn Helgaas)
- pciehp: Remove ignored MRL sensor interrupt events (Bjorn Helgaas)
- pciehp: Handle invalid data when reading from non-existent devices (Jarod Wilson)
- pciehp: Simplify pcie_poll_cmd() (Yijing Wang)
- Use "slot" and "pci_slot" for struct hotplug_slot and struct pci_slot (Yijing Wang)
- Protect pci_bus->slots with pci_slot_mutex, not pci_bus_sem (Yijing Wang)
- Hold pci_slot_mutex while searching bus->slots list (Yijing Wang)
Power management:
- Disable async suspend/resume for JMicron multi-function SATA/AHCI (Zhang Rui)
Virtualization:
- Add ACS quirks for Intel I219-LM/V (Alex Williamson)
- Restore ACS configuration as part of pci_restore_state() (Alexander Duyck)
MSI:
- Add pcibios_alloc_irq() and pcibios_free_irq() (Jiang Liu)
- x86: Implement pcibios_alloc_irq() and pcibios_free_irq() (Jiang Liu)
- Add helpers to manage pci_dev->irq and pci_dev->irq_managed (Jiang Liu)
- Free legacy IRQ when enabling MSI/MSI-X (Jiang Liu)
- ARM/PCI: Remove msi_controller from struct pci_sys_data (Lorenzo Pieralisi)
- Remove unused pcibios_msi_controller() hook (Lorenzo Pieralisi)
Generic host bridge driver:
- Remove dependency on ARM-specific struct hw_pci (Jayachandran C)
- Build setup-irq.o for arm64 (Jayachandran C)
- Add arm64 support (Jayachandran C)
APM X-Gene host bridge driver:
- Add APM X-Gene PCIe 64-bit prefetchable window (Duc Dang)
- Add support for a 64-bit prefetchable memory window (Duc Dang)
- Drop owner assignment from platform_driver (Krzysztof Kozlowski)
Broadcom iProc host bridge driver:
- Allow BCMA bus driver to be built as module (Hauke Mehrtens)
- Delete unnecessary checks before phy calls (Markus Elfring)
- Add arm64 support (Ray Jui)
Synopsys DesignWare host bridge driver:
- Don't complain missing *config* reg space if va_cfg0 is set (Murali Karicheri)
TI DRA7xx host bridge driver:
- Disable pm_runtime on get_sync failure (Kishon Vijay Abraham I)
- Add PM support (Kishon Vijay Abraham I)
- Clear MSE bit during suspend so clocks will idle (Kishon Vijay Abraham I)
- Add support to make GPIO drive PERST# line (Kishon Vijay Abraham I)
Xilinx AXI host bridge driver:
- Check for MSI interrupt flag before handling as INTx (Russell Joyce)
Miscellaneous:
- Fix Intersil/Techwell TW686[4589] AV capture class code (Krzysztof Hałasa)
- Use PCI_CLASS_SERIAL_USB instead of bare number (Bjorn Helgaas)
- Fix generic NCR 53c810 class code quirk (Bjorn Helgaas)
- Fix TI816X class code quirk (Bjorn Helgaas)
- Remove unused "pci_probe" flags (Bjorn Helgaas)
- Host bridge driver code simplifications (Fabio Estevam)
- Add dev_flags bit to access VPD through function 0 (Mark Rustad)
- Add VPD function 0 quirk for Intel Ethernet devices (Mark Rustad)
- Kill off set_irq_flags() usage (Rob Herring)
- Remove Intel Cherrytrail D3 delays (Srinidhi Kasagar)
- Clean up pci_find_capability() (Wei Yang)"
* tag 'pci-v4.3-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (72 commits)
PCI: Disable async suspend/resume for JMicron multi-function SATA/AHCI
PCI: Set MPS to match upstream bridge
PCI: Move MPS configuration check to pci_configure_device()
PCI: Drop references acquired by of_parse_phandle()
PCI/MSI: Remove unused pcibios_msi_controller() hook
ARM/PCI: Remove msi_controller from struct pci_sys_data
ARM/PCI, designware, xilinx: Use pci_scan_root_bus_msi()
PCI: Add pci_scan_root_bus_msi()
ARM/PCI: Replace panic with WARN messages on failures
PCI: generic: Add arm64 support
PCI: Build setup-irq.o for arm64
PCI: generic: Remove dependency on ARM-specific struct hw_pci
PCI: imx6: Simplify a trivial if-return sequence
PCI: spear: Use BUG_ON() instead of condition followed by BUG()
PCI: dra7xx: Remove unneeded use of IS_ERR_VALUE()
PCI: Remove pci_ats_enabled()
PCI: Stop caching ATS Invalidate Queue Depth
PCI: Move ATS declarations to linux/pci.h so they're all together
PCI: Clean up ATS error handling
PCI: Use pci_physfn() rather than looking up physfn by hand
...
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Provide a software-based implementation of the priviledged no access
support found in ARMv8.1.
Userspace pages are mapped using a different domain number from the
kernel and IO mappings. If we switch the user domain to "no access"
when we enter the kernel, we can prevent the kernel from touching
userspace.
However, the kernel needs to be able to access userspace via the
various user accessor functions. With the wrapping in the previous
patch, we can temporarily enable access when the kernel needs user
access, and re-disable it afterwards.
This allows us to trap non-intended accesses to userspace, eg, caused
by an inadvertent dereference of the LIST_POISON* values, which, with
appropriate user mappings setup, can be made to succeed. This in turn
can allow use-after-free bugs to be further exploited than would
otherwise be possible.
Signed-off-by: Russell King <[email protected]>
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Provide hooks into the kernel entry and exit paths to permit control
of userspace visibility to the kernel. The intended use is:
- on entry to kernel from user, uaccess_disable will be called to
disable userspace visibility
- on exit from kernel to user, uaccess_enable will be called to
enable userspace visibility
- on entry from a kernel exception, uaccess_save_and_disable will be
called to save the current userspace visibility setting, and disable
access
- on exit from a kernel exception, uaccess_restore will be called to
restore the userspace visibility as it was before the exception
occurred.
These hooks allows us to keep userspace visibility disabled for the
vast majority of the kernel, except for localised regions where we
want to explicitly access userspace.
Signed-off-by: Russell King <[email protected]>
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The following structure is just asking for trouble:
#ifdef CONFIG_symbol
.macro foo
...
.endm
.macro bar
...
.endm
.macro baz
...
.endm
#else
.macro foo
...
.endm
.macro bar
...
.endm
#ifdef CONFIG_symbol2
.macro baz
...
.endm
#else
.macro baz
...
.endm
#endif
#endif
such as one defintion being updated, but the other definitions miss out.
Where the contents of a macro needs to be conditional, the hint is in
the first clause of this very sentence. "contents" "conditional". Not
multiple separate definitions, especially not when much of the macro
is the same between different configs.
This patch fixes this bad style, which had caused the Thumb2 code to
miss-out on the uaccess updates.
Signed-off-by: Russell King <[email protected]>
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The only caller of cpu_die() on ARM is arch_cpu_idle_dead(), so
let's simplify the code by renaming cpu_die() to
arch_cpu_idle_dead(). While were here, drop the __ref annotation
because __cpuinit is gone nowadays.
Signed-off-by: Stephen Boyd <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Provide uaccess_save_and_enable() and uaccess_restore() to permit
control of userspace visibility to the kernel, and hook these into
the appropriate places in the kernel where we need to access
userspace.
Signed-off-by: Russell King <[email protected]>
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The audit code looks like it's been written to cope with being called
with IRQs enabled. However, it's unclear whether IRQs should be
enabled or disabled when calling the syscall tracing infrastructure.
Right now, sometimes we call this with IRQs enabled, and other times
with IRQs disabled. Opt for IRQs being enabled for consistency.
Acked-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Make the "fast" syscall return path fast again. The addition of IRQ
tracing and context tracking has made this path grossly inefficient.
We can do much better if these options are enabled if we save the
syscall return code on the stack - we then don't need to save a bunch
of registers around every single callout to C code.
Acked-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Since we switched to early trap initialisation in 94e5a85b3be0
("ARM: earlier initialization of vectors page") we haven't been writing
directly to the vectors page, and so there's no need for this domain
to be in manager mode. Switch it to client mode.
Signed-off-by: Russell King <[email protected]>
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Signed-off-by: Russell King <[email protected]>
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Rather than modifying both the domain access control register and our
per-thread copy, modify only the domain access control register, and
use the per-thread copy to save and restore the register over context
switches. We can also avoid the explicit initialisation of the
init thread_info structure.
This allows us to avoid needing to gain access to the thread information
at the uaccess control sites.
Signed-off-by: Russell King <[email protected]>
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ARM now uses pci_bus->msi to store the msi_controller pointer, so we don't
need to save it in struct pci_sys_data, and we don't need to implement
pcibios_msi_controller() to get it out of pci_sys_data.
Remove msi_controller from struct pci_sys_data and
pcibios_msi_controller().
[bhelgaas: changelog, split into separate patch]
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Jingoo Han <[email protected]>
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ARM previously stored the msi_controller pointer in its sysdata, struct
pci_sys_data, and implemented pcibios_msi_controller() to retrieve it.
That made PCI host controller drivers specific to ARM because they had to
put the msi_controller pointer in the ARM-specific pci_sys_data.
There is now a generic mechanism, pci_scan_root_bus_msi(), for giving the
msi_controller pointer to the PCI core. Use this for all ARM systems and
for the DesignWare and Xilinx PCI host controller drivers.
This removes an ARM dependency from the DesignWare, DRA7xx, EXYNOS, i.MX6,
Keystone, Layerscape, SPEAr13xx, and Xilinx drivers.
[bhelgaas: changelog, split into separate patch]
Suggested-by: Russell King <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Jingoo Han <[email protected]>
CC: Pratyush Anand <[email protected]>
CC: Arnd Bergmann <[email protected]>
CC: Simon Horman <[email protected]>
CC: Russell King <[email protected]>
CC: Thomas Petazzoni <[email protected]>
CC: Thierry Reding <[email protected]>
CC: Michal Simek <[email protected]>
CC: Marc Zyngier <[email protected]>
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In the ARM PCI bios32 layer, failures to dynamically allocate pci_sys_data
for a PCI bus, or a PCI bus scan failure have to be considered serious
warnings but they should not trigger a system panic so that at least the
system is given a chance to be debugged.
This patch replaces the panic statements with WARN() messages to improve
error reporting in the ARM PCI bios32 layer.
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Jingoo Han <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
CC: Russell King <[email protected]>
CC: Marc Zyngier <[email protected]>
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Add early fixmap support, initially to support permanent, fixed
mapping support for early console. A temporary, early pte is
created which is migrated to a permanent mapping in paging_init.
This is also needed since the attributes may change as the memory
types are initialized. The 3MiB range of fixmap spans two pte
tables, but currently only one pte is created for early fixmap
support.
Re-add FIX_KMAP_BEGIN to the index calculation in highmem.c since
the index for kmap does not start at zero anymore. This reverts
4221e2e6b316 ("ARM: 8031/1: fixmap: remove FIX_KMAP_BEGIN and
FIX_KMAP_END") to some extent.
Cc: Mark Salter <[email protected]>
Cc: Kees Cook <[email protected]>
Cc: Laura Abbott <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Ard Biesheuvel <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Stefan Agner <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Since 906c55579a63 ("timekeeping: Copy the shadow-timekeeper over the
real timekeeper last") it has become possible on ARM to:
- Obtain a CLOCK_MONOTONIC_COARSE or CLOCK_REALTIME_COARSE timestamp
via syscall.
- Subsequently obtain a timestamp for the same clock ID via VDSO which
predates the first timestamp (by one jiffy).
This is because ARM's update_vsyscall is deriving the coarse time
using the __current_kernel_time interface, when it should really be
using the timekeeper object provided to it by the timekeeping core.
It happened to work before only because __current_kernel_time would
access the same timekeeper object which had been passed to
update_vsyscall. This is no longer the case.
Cc: [email protected]
Fixes: 906c55579a63 ("timekeeping: Copy the shadow-timekeeper over the real timekeeper last")
Signed-off-by: Nathan Lynch <[email protected]>
Acked-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux into devel-stable
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ret_fast_syscall runs when user space makes a syscall. However it
needs to be marked as such so the ELF information is correct. Before
it was:
101: 8000f300 0 NOTYPE LOCAL DEFAULT 2 ret_fast_syscall
But with this change it correctly shows as:
101: 8000f300 96 FUNC LOCAL DEFAULT 2 ret_fast_syscall
I see this function when using perf to unwind call stacks from kernel
space to user space. Without this change I would need to add some
special case logic when using the vmlinux ELF information.
Signed-off-by: Drew Richardson <[email protected]>
Acked-by: Nicolas Pitre <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Since the commit "b2c3e38a5471 ARM: redo TTBR setup code for LPAE",
the setup code had been reworked. As a result the secondary CPUs
failed to come online in Big Endian.
As explained by Russell, the new code expected the value in r4/r5 to
be the least significant 32bits in r4 and the most significant 32bits
in r5. However, in the secondary code, we load this using ldrd, which
on BE reverses that.
This patch swap r4/r5 after the ldrd. It is done using the xor
instructions in order to not use a temporary register.
Signed-off-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Russell King <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip into next/cleanup
Merge "ARM: Interrupt cleanups and API change preparation" from Thomas
Gleixner:
The following patch series contains the following changes:
- Consolidation of chained interrupt handler setup/removal
- Switch to functions which avoid a redundant interrupt
descriptor lookup
- Preparation of interrupt flow handlers for the 'irq' argument
removal
* 'queue/irq/arm' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
ARM/orion/gpio: Prepare gpio_irq_handler for irq argument removal
ARM/pxa: Prepare balloon3_irq_handler for irq argument removal
ARM/pxa: Prepare *_irq_handler for irq argument removal
ARM/dove: Prepare pmu_irq_handler for irq argument removal
ARM/sa1111: Prepare sa1111_irq_handler for irq argument removal
ARM/locomo: Prepare locomo_handler for irq argument removal
ARM, irq: Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc
ARM/LPC32xx: Use irq_set_handler_locked()
ARM/irq: Use access helper irq_data_get_affinity_mask()
ARM/locomo: Consolidate chained IRQ handler install/remove
ARM/orion: Consolidate chained IRQ handler install/remove
Signed-off-by: Olof Johansson <[email protected]>
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Now that the common PSCI client code has been factored out to
drivers/firmware, and made safe for 32-bit use, move the 32-bit ARM code
over to it. This results in a moderate reduction of duplicated lines,
and will prevent further duplication as the PSCI client code is updated
for PSCI 1.0 and beyond.
The two legacy platform users of the PSCI invocation code are updated to
account for interface changes. In both cases the power state parameter
(which is constant) is now generated using macros, so that the
pack/unpack logic can be killed in preparation for PSCI 1.0 power state
changes.
Signed-off-by: Mark Rutland <[email protected]>
Acked-by: Rob Herring <[email protected]>
Cc: Catalin Marinas <[email protected]>
Cc: Ashwin Chaugule <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Russell King <[email protected]>
Cc: Will Deacon <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
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On some PAE systems (e.g. TI Keystone), memory is above the 32-bit
addressable limit, and the interconnect provides an aliased view of
parts of physical memory in the 32-bit addressable space. This alias
is strictly for boot time usage, and is not otherwise usable because
of coherency limitations.
In this case, virt_to_phys(secondary_startup) would return the
physical address of the secondary CPU boot entry point, but on such
systems, this would be above the 4GB limit.
A separate function, virt_to_idmap(), has been provided to return a
usable physical address for functions in the identity mapping, and
this must be used in preference to virt_to_phys() or __pa() to find
the physical entry point for functions in the identity mapping range.
For other systems, virt_to_idmap() and virt_to_phys() return identical
physical addresses.
Acked-by: Santosh Shilimkar <[email protected]>
Acked-by: Nicolas Pitre <[email protected]>
Tested-by Vitaly Andrianov <[email protected]>
Signed-off-by: Grygorii Strashko <[email protected]>
[Mark: apply rmk's suggested rewording]
Signed-off-by: Mark Rutland <[email protected]>
Cc: Russell King <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
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Since we've already stepped away from ENABLE is a JMP and DISABLE is a
NOP with the branch_default bits, and are going to make it even worse,
rename it to make it all clearer.
This way we don't mix multiple levels of logic attributes, but have a
plain 'physical' name for what the current instruction patching status
of a jump label is.
This is a first step in removing the naming confusion that has led to
a stream of avoidable bugs such as:
a833581e372a ("x86, perf: Fix static_key bug in load_mm_cr4()")
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Cc: Andrew Morton <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Paul E. McKenney <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
[ Beefed up the changelog. ]
Signed-off-by: Ingo Molnar <[email protected]>
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Writes to /sys/.../cpuX/online fail if we determine the platform
doesn't support hotplug for that CPU. Furthermore, if the cpu_die
op isn't specified the system hangs when we try to offline a CPU
and it comes right back online unexpectedly. Let's figure this
stuff out before we make the sysfs nodes so that the online file
doesn't even exist if it isn't (at least sometimes) possible to
hotplug the CPU.
Add a new 'cpu_can_disable' op and repoint all 'cpu_disable'
implementations at it because all implementers use the op to
indicate if a CPU can be hotplugged or not in a static fashion.
With PSCI we may need to add a 'cpu_disable' op so that the
secure OS can be migrated off the CPU we're trying to hotplug.
In this case, the 'cpu_can_disable' op will indicate that all
CPUs are hotpluggable by returning true, but the 'cpu_disable' op
will make a PSCI migration call and occasionally fail, denying
the hotplug of a CPU. This shouldn't be any worse than x86 where
we may indicate that all CPUs are hotpluggable but occasionally
we can't offline a CPU due to check_irq_vectors_for_cpu_disable()
failing to find a CPU to move vectors to.
Cc: Mark Rutland <[email protected]>
Cc: Nicolas Pitre <[email protected]>
Cc: Dave Martin <[email protected]>
Acked-by: Simon Horman <[email protected]> [shmobile portion]
Tested-by: Simon Horman <[email protected]>
Cc: Magnus Damm <[email protected]>
Cc: <[email protected]>
Tested-by: Tyler Baker <[email protected]>
Cc: Geert Uytterhoeven <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Signed-off-by: Russell King <[email protected]>
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To enable sharing of the arm_pmu code with arm64, this patch factors it
out to drivers/perf/. A new drivers/perf directory is added for
performance monitor drivers to live under.
MAINTAINERS is updated accordingly. Files added previously without a
corresponsing MAINTAINERS update (perf_regs.c, perf_callchain.c, and
perf_event.h) are also added.
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Greg Kroah-Hartman <[email protected]>
Cc: Ingo Molnar <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Paul Mackerras <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Russell King <[email protected]>
Cc: Will Deacon <[email protected]>
Signed-off-by: Mark Rutland <[email protected]>
[will: augmented Kconfig help slightly]
Signed-off-by: Will Deacon <[email protected]>
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