| Age | Commit message (Collapse) | Author | Files | Lines |
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This sorts out merge conflicts with the arm/gpio branch that
already got merged into mainline Linux.
Signed-off-by: Arnd Bergmann <[email protected]>
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Add empty version of l2x0_of_init for when CONFIG_CACHE_L2X0 is not selected.
Signed-off-by: Rob Herring <[email protected]>
Acked-by: Barry Song <[email protected]>
Reviewed-by: Shawn Guo <[email protected]>
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Conflicts:
arch/arm/Kconfig
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Commit "ARM: gic: add irq_domain support" (b49b6ff) breaks SPARSE_IRQ
on platforms with GIC. When SPARSE_IRQ is enabled, all NR_IRQS or
mach_desc->nr_irqs will be allocated by arch_probe_nr_irqs(). This caused
irq_alloc_descs to allocate irq_descs after the pre-allocated space.
Make irq_alloc_descs search for an exact irq range and assume it has
been pre-allocated on failure. For DT probing dynamic allocation is used.
DT enabled platforms should set their nr_irqs to NR_IRQ_LEGACY and have all
irq_chips allocate their irq_descs with irq_alloc_descs if SPARSE_IRQ is
enabled.
gic_init irq_start param is changed to be signed with negative meaning do
dynamic Linux irq assigment.
Signed-off-by: Rob Herring <[email protected]>
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This adds ARM gic interrupt controller initialization using device tree
data.
The initialization function is intended to be called by of_irq_init
function like this:
const static struct of_device_id irq_match[] = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
{}
};
static void __init init_irqs(void)
{
of_irq_init(irq_match);
}
Signed-off-by: Rob Herring <[email protected]>
Reviewed-by: Jamie Iles <[email protected]>
Tested-by: Thomas Abraham <[email protected]>
Acked-by: Grant Likely <[email protected]>
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Convert the gic interrupt controller to use irq domains in preparation
for device-tree binding and MULTI_IRQ. This allows for translation between
GIC interrupt IDs and Linux irq numbers.
The meaning of irq_offset has changed. It now is just the number of skipped
GIC interrupt IDs for the controller. It will be 16 for primary GIC and 32
for secondary GICs.
Signed-off-by: Rob Herring <[email protected]>
Cc: Marc Zyngier <[email protected]>
Reviewed-by: Jamie Iles <[email protected]>
Tested-by: Thomas Abraham <[email protected]>
Acked-by: Grant Likely <[email protected]>
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into highbank/soc
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http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
* 'devel-stable' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm: (178 commits)
ARM: 7139/1: fix compilation with CONFIG_ARM_ATAG_DTB_COMPAT and large TEXT_OFFSET
ARM: gic, local timers: use the request_percpu_irq() interface
ARM: gic: consolidate PPI handling
ARM: switch from NO_MACH_MEMORY_H to NEED_MACH_MEMORY_H
ARM: mach-s5p64x0: remove mach/memory.h
ARM: mach-s3c64xx: remove mach/memory.h
ARM: plat-mxc: remove mach/memory.h
ARM: mach-prima2: remove mach/memory.h
ARM: mach-zynq: remove mach/memory.h
ARM: mach-bcmring: remove mach/memory.h
ARM: mach-davinci: remove mach/memory.h
ARM: mach-pxa: remove mach/memory.h
ARM: mach-ixp4xx: remove mach/memory.h
ARM: mach-h720x: remove mach/memory.h
ARM: mach-vt8500: remove mach/memory.h
ARM: mach-s5pc100: remove mach/memory.h
ARM: mach-tegra: remove mach/memory.h
ARM: plat-tcc: remove mach/memory.h
ARM: mach-mmp: remove mach/memory.h
ARM: mach-cns3xxx: remove mach/memory.h
...
Fix up mostly pretty trivial conflicts in:
- arch/arm/Kconfig
- arch/arm/include/asm/localtimer.h
- arch/arm/kernel/Makefile
- arch/arm/mach-shmobile/board-ap4evb.c
- arch/arm/mach-u300/core.c
- arch/arm/mm/dma-mapping.c
- arch/arm/mm/proc-v7.S
- arch/arm/plat-omap/Kconfig
largely due to some CONFIG option renaming (ie CONFIG_PM_SLEEP ->
CONFIG_ARM_CPU_SUSPEND for the arm-specific suspend code etc) and
addition of NEED_MACH_MEMORY_H next to HAVE_IDE.
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http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
* 'gpio' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm: (43 commits)
ARM: 7135/1: ep93xx: bring back missing <mach/gpio.h>
ARM: 7104/1: plat-pxa: break out GPIO driver specifics
ARM: 7103/1: plat-pxa: move PXA GPIO driver to GPIO subsystem
ARM: 7042/3: mach-ep93xx: break out GPIO driver specifics
ARM: 7101/1: arm/tegra: Replace <mach/gpio.h> with <mach/gpio-tegra.h>
ARM: 7094/1: arm/tegra: Move EN_VDD_1V05_GPIO to board-harmony.h
ARM: 7083/1: rewrite U300 GPIO to use gpiolib
ARM: 7074/1: gpio: davinci: eliminate unused variable warnings
ARM: 7063/1: Orion: gpio: add missing include of linux/types.h
ARM: 7055/1: arm/tegra: mach/gpio.h: include linux/types.h to fix build
ARM: 7054/1: arm/tegra: Delete custom gpio_to_irq, and irq_to_gpio
ARM: 7053/1: gpio/tegra: Implement gpio_chip.to_irq
ARM: 7052/1: gpio/tegra: Remove use of irq_to_gpio
ARM: 7057/1: mach-pnx4008: rename GPIO header
ARM: 7056/1: plat-nomadik: kill off <plat/gpio.h>
ARM: 7050/1: mach-sa1100: delete irq_to_gpio() function
ARM: 7049/1: mach-sa1100: move SA1100 GPIO driver to GPIO subsystem
ARM: 7045/1: mach-lpc32xx: break out GPIO driver specifics
ARM: 7044/1: mach-lpc32xx: move LPC32XX GPIO driver to GPIO subsystem
ARM: 7043/1: mach-ixp2000: rename GPIO header
...
Fix up trivial conflicts in arch/arm/mach-u300/Kconfig manually
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git://github.com/mzyngier/arm-platforms into devel-stable
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This patch remove the hardcoded link between local timers and PPIs,
and convert the PPI users (TWD, MCT and MSM timers) to the new
*_percpu_irq interface. Also some collateral cleanup
(local_timer_ack() is gone, and the interrupt handler is strictly
private to each driver).
PPIs are now useable for more than just the local timers.
Additional testing by David Brown (msm8250 and msm8660) and
Shawn Guo (imx6q).
Cc: David Brown <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Acked-by: David Brown <[email protected]>
Tested-by: David Brown <[email protected]>
Tested-by: Shawn Guo <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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PPI handling is a bit of an odd beast. It uses its own low level
handling code and is hardwired to the local timers (hence lacking
a registration interface).
Instead, switch the low handling to the normal SPI handling code.
PPIs are handled by the handle_percpu_devid_irq flow.
This also allows the removal of some duplicated code.
Cc: Kukjin Kim <[email protected]>
Cc: David Brown <[email protected]>
Cc: Bryan Huntsman <[email protected]>
Cc: Tony Lindgren <[email protected]>
Cc: Paul Mundt <[email protected]>
Cc: Magnus Damm <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Acked-by: David Brown <[email protected]>
Tested-by: David Brown <[email protected]>
Tested-by: Shawn Guo <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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we save the l2x0 registers at the first initialization, and platform codes
can get them to restore l2x0 status after wakeup.
Cc: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Barry Song <[email protected]>
Reviewed-by: Santosh Shilimkar <[email protected]>
Tested-by: Shawn Guo <[email protected]>
Signed-off-by: Russell King <[email protected]>
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This adds probing for ARM L2x0 cache controllers via device tree. Support
includes the L210, L220, and PL310 controllers. The binding allows setting
up cache RAM latencies and filter addresses (PL310 only).
Signed-off-by: Rob Herring <[email protected]>
Acked-by: Grant Likely <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Acked-by: Olof Johansson <[email protected]>
Acked-by: Barry Song <[email protected]>
Signed-off-by: Russell King <[email protected]>
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This tries to clear up the confusion between integers and iomem pointers
in the marvell pxa platform. MMIO addresses are supposed to be __iomem*
values, in order to let the Linux type checking work correctly. This
patch moves the cast to __iomem as far back as possible, to the place
where the MMIO virtual address windows are defined.
Signed-off-by: Arnd Bergmann <[email protected]>
Signed-off-by: Eric Miao <[email protected]>
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When the cpu is powered down in a low power mode, the gic cpu
interface may be reset, and when the cpu cluster is powered
down, the gic distributor may also be reset.
This patch uses CPU_PM_ENTER and CPU_PM_EXIT notifiers to save
and restore the gic cpu interface registers, and the
CPU_CLUSTER_PM_ENTER and CPU_CLUSTER_PM_EXIT notifiers to save
and restore the gic distributor registers.
Original-author: Gary King <[email protected]>
Signed-off-by: Colin Cross <[email protected]>
Signed-off-by: Santosh Shilimkar <[email protected]>
Tested-and-Acked-by: Shawn Guo <[email protected]>
Tested-by: Vishwanath BS <[email protected]>
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Fighting unfixed U-Boots and other beasts that may the cache in
a locked-down state when starting the kernel, we make sure to
disable all cache lock-down when initializing the l2x0 so we
are in a known state.
Cc: Srinidhi Kasagar <[email protected]>
Cc: Rabin Vincent <[email protected]>
Cc: Adrian Bunk <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Catalin Marinas <[email protected]>
Cc: Will Deacon <[email protected]>
Reviewed-by: Santosh Shilimkar <[email protected]>
Reported-by: Jan Rinze <[email protected]>
Tested-by: Robert Marklund <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Signed-off-by: Russell King <[email protected]>
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<asm/hardware/pl080.h> doesn't have protection to deal with multiple inclusion.
And so we get compilation errors in cases where this file is included more than
once. This patch adds #ifdefs at the top of file to protect it against multiple
inclusions.
Signed-off-by: Viresh Kumar <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
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This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and
PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3
bits.
The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits
[19:17] for Way size, however the existing code only uses 2 bits to
get this value. This results in incorrect cachesize calculations.
It also results in performing operations on the whole cache when we
erroneously decide that the range is big enough (due to l2x0_size being
too small) and also prints incorrect cachesize.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Acked-by: Will Deacon <[email protected]>
Cc: [email protected]
Signed-off-by: Russell King <[email protected]>
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Rather than marking the mach/gpio.h header files which want to use the
trivial GPIOLIB implementation, mark those which do not want to use it
instead. This means that by default, you get the trivial implementation
and only have to do something extra if you need to. This should
encourage the use of the trivial default implementation.
As an additional bonus, several gpio.h header files become empty.
Acked-by: H Hartley Sweeten <[email protected]>
Tested-by: Jamie Iles <[email protected]>
Acked-by: Kukjin Kim <[email protected]>
Signed-off-by: Russell King <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:
PCI: remove printks about disabled bridge windows
PCI: fold pci_calc_resource_flags() into decode_bar()
PCI: treat mem BAR type "11" (reserved) as 32-bit, not 64-bit, BAR
PCI: correct pcie_set_readrq write size
PCI: pciehp: change wait time for valid configuration access
x86/PCI: Preserve existing pci=bfsort whitelist for Dell systems
PCI: ARI is a PCIe v2 feature
x86/PCI: quirks: Use pci_dev->revision
PCI: Make the struct pci_dev * argument of pci_fixup_irqs const.
PCI hotplug: cpqphp: use pci_dev->vendor
PCI hotplug: cpqphp: use pci_dev->subsystem_{vendor|device}
x86/PCI: config space accessor functions should not ignore the segment argument
PCI: Assign values to 'pci_obff_signal_type' enumeration constants
x86/PCI: reduce severity of host bridge window conflict warnings
PCI: enumerate the PCI device only removed out PCI hieratchy of OS when re-scanning PCI
PCI: PCIe AER: add aer_recover_queue
x86/PCI: select direct access mode for mmconfig option
PCI hotplug: Rename is_ejectable which also exists in dock.c
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ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc
* 'next/devel' of ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (128 commits)
ARM: S5P64X0: External Interrupt Support
ARM: EXYNOS4: Enable MFC on Samsung NURI
ARM: EXYNOS4: Enable MFC on universal_c210
ARM: S5PV210: Enable MFC on Goni
ARM: S5P: Add support for MFC device
ARM: EXYNOS4: Add support FIMD on SMDKC210
ARM: EXYNOS4: Add platform device and helper functions for FIMD
ARM: EXYNOS4: Add resource definition for FIMD
ARM: EXYNOS4: Change devname for FIMD clkdev
ARM: SAMSUNG: Add IRQ_I2S0 definition
ARM: SAMSUNG: Add platform device for idma
ARM: EXYNOS4: Add more registers to be saved and restored for PM
ARM: EXYNOS4: Add more register addresses of CMU
ARM: EXYNOS4: Add platform device for dwmci driver
ARM: EXYNOS4: configure rtc-s3c on NURI
ARM: EXYNOS4: configure MAX8903 secondary charger on NURI
ARM: EXYNOS4: configure ADC on NURI
ARM: EXYNOS4: configure MAX17042 fuel gauge on NURI
ARM: EXYNOS4: configure regulators and PMIC(MAX8997) on NURI
ARM: EXYNOS4: Increase NR_IRQS for devices with more IRQs
...
Fix up tons of silly conflicts:
- arch/arm/mach-davinci/include/mach/psc.h
- arch/arm/mach-exynos4/Kconfig
- arch/arm/mach-exynos4/mach-smdkc210.c
- arch/arm/mach-exynos4/pm.c
- arch/arm/mach-imx/mm-imx1.c
- arch/arm/mach-imx/mm-imx21.c
- arch/arm/mach-imx/mm-imx25.c
- arch/arm/mach-imx/mm-imx27.c
- arch/arm/mach-imx/mm-imx31.c
- arch/arm/mach-imx/mm-imx35.c
- arch/arm/mach-mx5/mm.c
- arch/arm/mach-s5pv210/mach-goni.c
- arch/arm/mm/Kconfig
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Aside of the usual motivation for constification, this function has a
history of being abused a hook for interrupt and other fixups so I turned
this function const ages ago in the MIPS code but it should be done
treewide.
Due to function pointer passing in varous places a few other functions
had to be constified as well.
Signed-off-by: Ralf Baechle <[email protected]>
To: Anton Vorontsov <[email protected]>
To: Chris Metcalf <[email protected]>
To: Colin Cross <[email protected]>
Acked-by: "David S. Miller" <[email protected]>
To: Eric Miao <[email protected]>
To: Erik Gilling <[email protected]>
Acked-by: Guan Xuetao <[email protected]>
To: "H. Peter Anvin" <[email protected]>
To: Imre Kaloz <[email protected]>
To: Ingo Molnar <[email protected]>
To: Ivan Kokshaysky <[email protected]>
To: Jesse Barnes <[email protected]>
To: Krzysztof Halasa <[email protected]>
To: Lennert Buytenhek <[email protected]>
To: Matt Turner <[email protected]>
To: Nicolas Pitre <[email protected]>
To: Olof Johansson <[email protected]>
Acked-by: Paul Mundt <[email protected]>
To: Richard Henderson <[email protected]>
To: Russell King <[email protected]>
To: Thomas Gleixner <[email protected]>
Cc: Andrew Morton <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Jesse Barnes <[email protected]>
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Since Samsung EXYNOS4210 cannot support register banking in GIC,
so needs to update CPU interface base address.
The 'gic_chip_data' is used for it, this patch moves gic_chip_data
structure declaraton to arch/arm/include/asm/hardware/gic.h to use
it.
Cc: Russell King <[email protected]>
Signed-off-by: Changhwan Youn <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
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A pcmcia_init callback isn't used on any of the platforms. Drop it.
Signed-off-by: Dmitry Eremin-Solenikov <[email protected]>
Signed-off-by: Eric Miao <[email protected]>
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This allows platforms to specify the clcokevent name upon registration.
Acked-by: Catalin Marinas <[email protected]>
Signed-off-by: Russell King <[email protected]>
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This allows platforms to specify the clocksource name upon
registration, which is necessary should they wish to register more
than one sp804 clocksource.
Acked-by: Catalin Marinas <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: Lucas De Marchi <[email protected]>
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Conflicts:
arch/arm/Kconfig
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Few architectures combine the GIC with an external interrupt
controller. On such systems it may be necessary to update both
the GIC registers and the external controller's registers to control
IRQ behavior.
This can be addressed in couple of possible methods.
1. Export common GIC routines along with 'struct irq_chip gic_chip'
and allow architectures to have custom function by override.
2. Provide architecture specific function pointer hooks
within GIC library and leave platforms to add the necessary
code as part of these hooks.
First one might be non-intrusive but have few shortcomings like arch
needs to have there own custom gic library. Locks used should be
common since it caters to same IRQs etc. Maintenance point of view
also it leads to multiple file fixes.
The second probably is cleaner and portable. It ensures that all the
common GIC infrastructure is not touched and also provides archs to
address their specific issue.
Cc: Russell King <[email protected]>
Signed-off-by: Santosh Shilimkar <[email protected]>
Acked-by: Colin Cross <[email protected]>
Tested-by: Colin Cross <[email protected]>
Signed-off-by: Russell King <[email protected]>
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In sysctl_soft_reset(), switch to slow mode before resetting the system
via the system controller. This is required.
Reviewed-by: Stanley Miao <[email protected]>
Signed-off-by: Shiraz Hashim <[email protected]>
Signed-off-by: Russell King <[email protected]>
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The effect of cache sync operation is to drain the store buffer and
wait for all internal buffers to be empty. In normal conditions, store
buffer is able to merge the normal memory writes within its 32-byte
data buffers. Due to this erratum present in r3p0, the effect of cache
sync operation on the store buffer still remains when the operation
completes. This means that the store buffer is always asked to drain
and this prevents it from merging any further writes.
This can severely affect performance on the write traffic esp. on
Normal memory NC one.
The proposed workaround is to replace the normal offset of cache sync
operation(0x730) by another offset targeting an unmapped PL310
register 0x740.
Signed-off-by: srinidhi kasagar <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Acked-by: Catalin Marinas <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Timers on Versatile Express mainboard are used as system clock/event
sources. Driver assumes that they are clocked with 1MHz signal.
Old V2M firmware apparently configured it by default, but on newer
boards one can observe that "sleep 1" command takes over 30 seconds
to finish, as the timers are fed with 32kHz instead...
This patch performs required magic and also removes code clearing
timer's control registers, as exactly the same operations are
performed by the timer driver few jiffies later.
Signed-off-by: Pawel Moll <[email protected]>
Tested-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (243 commits)
omap2: Make OMAP2PLUS select OMAP_DM_TIMER
OMAP4: hwmod data: Fix alignment and end of line in structurefields
OMAP4: hwmod data: Move the DMA structures
OMAP4: hwmod data: Move the smartreflex structures
OMAP4: hwmod data: Fix missing SIDLE_SMART_WKUP in smartreflexsysc
arm: omap: tusb6010: add name for MUSB IRQ
arm: omap: craneboard: Add USB EHCI support
omap2+: Initialize serial port for dynamic remuxing for n8x0
omap2+: Add struct omap_board_data and use it for platform level serial init
omap2+: Allow hwmod state changes to mux pads based on the state changes
omap2+: Add support for hwmod specific muxing of devices
omap2+: Add omap_mux_get_by_name
OMAP2: PM: fix compile error when !CONFIG_SUSPEND
MAINTAINERS: OMAP: hwmod: update hwmod code, data maintainership
OMAP4: Smartreflex framework extensions
OMAP4: hwmod: Add inital data for smartreflex modules.
OMAP4: PM: Program correct init voltages for scalable VDDs
OMAP4: Adding voltage driver support
OMAP4: Register voltage PMIC parameters with the voltage layer
OMAP3: PM: Program correct init voltages for VDD1 and VDD2
...
Fix up trivial conflict in arch/arm/plat-omap/Kconfig
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'versatile' into devel
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The commit 6ac6b817f3f4c23c5febd960d8deb343e13af5f3 (ARM: pxa: encode
IRQ number into .nr_irqs) removed definition of ITE_LAST_IRQ which
caused the following build error:
CC arch/arm/common/it8152.o
arch/arm/common/it8152.c: In function 'it8152_init_irq':
arch/arm/common/it8152.c:86: error: 'IT8152_LAST_IRQ' undeclared (first use in this function)
arch/arm/common/it8152.c:86: error: (Each undeclared identifier is reported only once
arch/arm/common/it8152.c:86: error: for each function it appears in.)
make[2]: *** [arch/arm/common/it8152.o] Error 1
Defining the IT8152_LAST_IRQ in the arch/arm/include/hardware/it8152.c
fixes the build.
Signed-off-by: Mike Rapoport <[email protected]>
Signed-off-by: Eric Miao <[email protected]>
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This patch adds the PL310 Auxiliary Control Register bitfields
so that SOC's can use these bit fields to construct the AUXCTRL
value to be passed/programmed instead of hardcoding it.
Signed-off-by: Santosh Shilimkar <[email protected]>
Acked-by: Catalin Marinas <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
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Avoid adding nasty genirq-specific code to local timers to enable PPI
interrupts. Instead, provide a gic function to do this.
Signed-off-by: Russell King <[email protected]>
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Provide a standard get_irqnr_preamble assembler macro for platforms
to use, which retrieves the base address of the GIC CPU interface
from gic_cpu_base_addr. Allow platforms to override this by defining
HAVE_GET_IRQNR_PREAMBLE.
Reviewed-by: Catalin Marinas <[email protected]>
Tested-by: Abhijeet Dharmapurikar <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Every architecture using the GIC has a gic_cpu_base_addr pointer for
GIC 0 for their entry assembly code to use to decode the cause of the
current interrupt. Move this into the common GIC code.
Reviewed-by: Catalin Marinas <[email protected]>
Tested-by: Abhijeet Dharmapurikar <[email protected]>
Signed-off-by: Russell King <[email protected]>
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We don't need to re-pass the base address for the CPU interfaces to the
GIC for secondary CPUs, as it will never be different from the boot CPU
- and even if it was, we'd overwrite the boot CPU's base address.
Get rid of this argument, and rename to gic_secondary_init().
Reviewed-by: Catalin Marinas <[email protected]>
Tested-by: Abhijeet Dharmapurikar <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Provide gic_init() which initializes the GIC distributor and current
CPU's GIC interface for the boot (or single) CPU.
Reviewed-by: Catalin Marinas <[email protected]>
Tested-by: Abhijeet Dharmapurikar <[email protected]>
Signed-off-by: Russell King <[email protected]>
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This patch is the identical GIC demux implementation
merge V3. Instead of implementing same code over and
over simply share it in entry-macro-gic.S. The shared
code is based on the realview implementation.
Each GIC demux instance still has to setup the base address
of the controller using the get_irqnr_preamble macro. The
rest of the GIC specific code can be shared.
Signed-off-by: Magnus Damm <[email protected]>
Acked-by: Srinidhi Kasagar <[email protected]>
Signed-off-by: Russell King <[email protected]>
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From: Rob Herring <[email protected]>
The timer-sp h/w used on versatile platforms can also be used for other
platforms, so move it to a common location.
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Signed-off-by: Eric Miao <[email protected]>
Cc: Haojian Zhuang <[email protected]>
Cc: Mike Rapoport <[email protected]>
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git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base into devel-stable
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git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into devel-stable
Conflicts:
arch/arm/mach-s3c64xx/dev-audio.c
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The cache size is needed for to optimise range based
maintainance operations
Signed-off-by: Santosh Shilimkar <[email protected]>
Acked-by: Catalin Marinas <[email protected]>
Acked-by: Linus Walleij <[email protected]>
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Replace tab with space after #define to be consisten with other
define in the file. Also move the bit mask below the register offsets.
Signed-off-by: Santosh Shilimkar <[email protected]>
Acked-by: Catalin Marinas <[email protected]>
Acked-by: Linus Walleij <[email protected]>
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This patch adds L2X0 Prefetch and Power control register.
Signed-off-by: Kyungmin Park <[email protected]>
Acked-by: Catalin Marinas <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
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