blaster4385/linux-IllusionX - Linux kernel with personal config changes for arch linux

Age	Commit message (Collapse)	Author	Files	Lines
2015-06-25	ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)	Vineet Gupta	1	-2/+62
	L2 cache on ARCHS processors is called SLC (System Level Cache) For working DMA (in absence of hardware assisted IO Coherency) we need to manage SLC explicitly when buffers transition between cpu and controllers. Signed-off-by: Vineet Gupta <[email protected]>
2015-06-22	ARCv2: MMUv4: support aliasing icache config	Vineet Gupta	1	-1/+13
	This is also default for AXS103 release Signed-off-by: Vineet Gupta <[email protected]>
2015-06-22	ARCv2: MMUv4: cache programming model changes	Vineet Gupta	1	-15/+97
	Caveats about cache flush on ARCv2 based cores - dcache is PIPT so paddr is sufficient for cache maintenance ops (no need to setup PTAG reg - icache is still VIPT but only aliasing configs need PTAG setup So basically this is departure from MMU-v3 which always need vaddr in line ops registers (DC_IVDL, DC_FLDL, IC_IVIL) but paddr in DC_PTAG, IC_PTAG respectively. Signed-off-by: Vineet Gupta <[email protected]>
2015-06-19	ARC: untangle cache flush loop	Vineet Gupta	1	-25/+55
	- Remove the ifdef'ery and write distinct versions for each mmu ver even if there is some code duplication Signed-off-by: Vineet Gupta <[email protected]>
2015-06-19	ARC: cacheflush: No need to retain DC_CTRL from __before_dc_op()	Vineet Gupta	1	-20/+19
	That is because __after_dc_op() already reads it for status check, so it is better anyways to use that "newer" value. Also reduces the clutter in callers for passing from/to these routines. Signed-off-by: Vineet Gupta <[email protected]>
2015-06-19	ARC: cacheflush: move some code around, delete old comments	Vineet Gupta	1	-165/+102
	Signed-off-by: Vineet Gupta <[email protected]>
2015-06-19	ARC: mm/cache_arc700.c -> mm/cache.c	Vineet Gupta	1	-0/+723
	Signed-off-by: Vineet Gupta <[email protected]>