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2024-01-20Merge tag 'riscv-for-linus-6.8-mw4' of ↵Linus Torvalds2-3/+8
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull more RISC-V updates from Palmer Dabbelt: - Support for tuning for systems with fast misaligned accesses. - Support for SBI-based suspend. - Support for the new SBI debug console extension. - The T-Head CMOs now use PA-based flushes. - Support for enabling the V extension in kernel code. - Optimized IP checksum routines. - Various ftrace improvements. - Support for archrandom, which depends on the Zkr extension. - The build is no longer broken under NET=n, KUNIT=y for ports that don't define their own ipv6 checksum. * tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (56 commits) lib: checksum: Fix build with CONFIG_NET=n riscv: lib: Check if output in asm goto supported riscv: Fix build error on rv32 + XIP riscv: optimize ELF relocation function in riscv RISC-V: Implement archrandom when Zkr is available riscv: Optimize hweight API with Zbb extension riscv: add dependency among Image(.gz), loader(.bin), and vmlinuz.efi samples: ftrace: Add RISC-V support for SAMPLE_FTRACE_DIRECT[_MULTI] riscv: ftrace: Add DYNAMIC_FTRACE_WITH_DIRECT_CALLS support riscv: ftrace: Make function graph use ftrace directly riscv: select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY lib/Kconfig.debug: Update AS_HAS_NON_CONST_LEB128 comment and name riscv: Restrict DWARF5 when building with LLVM to known working versions riscv: Hoist linker relaxation disabling logic into Kconfig kunit: Add tests for csum_ipv6_magic and ip_fast_csum riscv: Add checksum library riscv: Add checksum header riscv: Add static key for misaligned accesses asm-generic: Improve csum_fold RISC-V: selftests: cbo: Ensure asm operands match constraints ...
2024-01-17Merge tag 'riscv-for-linus-6.8-mw1' of ↵Linus Torvalds2-0/+220
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for many new extensions in hwprobe, along with a handful of cleanups - Various cleanups to our page table handling code, so we alwayse use {READ,WRITE}_ONCE - Support for the which-cpus flavor of hwprobe - Support for XIP kernels has been resurrected * tag 'riscv-for-linus-6.8-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (52 commits) riscv: hwprobe: export Zicond extension riscv: hwprobe: export Zacas ISA extension riscv: add ISA extension parsing for Zacas dt-bindings: riscv: add Zacas ISA extension description riscv: hwprobe: export Ztso ISA extension riscv: add ISA extension parsing for Ztso use linux/export.h rather than asm-generic/export.h riscv: Remove SHADOW_OVERFLOW_STACK_SIZE macro riscv; fix __user annotation in save_v_state() riscv: fix __user annotation in traps_misaligned.c riscv: Select ARCH_WANTS_NO_INSTR riscv: Remove obsolete rv32_defconfig file riscv: Allow disabling of BUILTIN_DTB for XIP riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macro riscv: Make XIP bootable again riscv: Fix set_direct_map_default_noflush() to reset _PAGE_EXEC riscv: Fix module_alloc() that did not reset the linear mapping permissions riscv: Fix wrong usage of lm_alias() when splitting a huge linear mapping riscv: Check if the code to patch lies in the exit section riscv: Use the same CPU operations for all CPUs ...
2024-01-11dt-bindings: riscv: Document cbop-block-sizeDaniel Henrique Barboza1-0/+5
Following the examples of cbom-block-size and cboz-block-size, cbop-block-size is the cache size of Zicbop (cbo.prefetch) operations. The most common case is to have all cache block sizes to be the same size (e.g. profiles such as rva22u64 mandates a 64 bytes size for all cache operations), but there's no specification requirement for that, and an implementation can have different cache sizes for each operation. Cc: Rob Herring <robh@kernel.org> Cc: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20231029123500.739409-1-dbarboza@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-01-11dt-bindings: riscv: permit numbers in "riscv,isa"Conor Dooley1-1/+1
There are some extensions that contain numbers, such as Zve32f, which are enabled by the "max" cpu type in QEMU. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231208-uncolored-oxidant-5ab37dd3ab84@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-01-11dt-bindings: riscv: cpus: Clarify mmu-type interpretationSamuel Holland1-2/+2
The current description implies that only a single address translation mode is available to the operating system. However, some implementations support multiple address translation modes, and the operating system is free to choose between them. Per the RISC-V privileged specification, Sv48 implementations must also implement Sv39, and likewise Sv57 implies support for Sv48. This means it is possible to describe all supported address translation modes using a single value, by naming the largest supported mode. This appears to have been the intended usage of the property, so note it explicitly. Fixes: 4fd669a8c487 ("dt-bindings: riscv: convert cpu binding to json-schema") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231227175739.1453782-1-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-01-09Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support"Palmer Dabbelt1-0/+6
Clément Léger <cleger@rivosinc.com> says: This series add support for a few more extensions that are present in the RVA22U64/RVA23U64 (either mandatory or optional) and that are useful for userspace: - Zicond - Zacas - Ztso Series currently based on riscv/for-next. * b4-shazam-lts: riscv: hwprobe: export Zicond extension riscv: hwprobe: export Zacas ISA extension riscv: add ISA extension parsing for Zacas dt-bindings: riscv: add Zacas ISA extension description riscv: hwprobe: export Ztso ISA extension riscv: add ISA extension parsing for Ztso Link: https://lore.kernel.org/r/20231220155723.684081-1-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-01-09dt-bindings: riscv: add Zacas ISA extension descriptionClément Léger1-0/+6
Add description for the Zacas ISA extension which was ratified recently. Signed-off-by: Clément Léger <cleger@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231220155723.684081-4-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-12-20dt-bindings: riscv: cpus: Add AMD MicroBlaze V compatibleMichal Simek1-0/+1
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. It is hardware compatible with classic MicroBlaze processor. Signed-off-by: Michal Simek <michal.simek@amd.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/d442d916204d26f82c1c3a924a4cdfb117960e1b.1699270661.git.michal.simek@amd.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-12-12dt-bindings: riscv: add Zfa ISA extension descriptionClément Léger1-0/+6
Add description for the Zfa ISA extension[1]. Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/view [1] Signed-off-by: Clément Léger <cleger@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231114141256.126749-21-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-12-12dt-bindings: riscv: add Zvfh[min] ISA extension descriptionClément Léger1-0/+12
Add description for Zvfh[min] ISA extension[1]. Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view [1] Signed-off-by: Clément Léger <cleger@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231114141256.126749-18-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-12-12dt-bindings: riscv: add Zihintntl ISA extension descriptionClément Léger1-0/+6
Add description for Zihintntl ISA extension[1]. Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view [1] Signed-off-by: Clément Léger <cleger@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231114141256.126749-15-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-12-12dt-bindings: riscv: add Zfh[min] ISA extensions descriptionClément Léger1-0/+13
Add description of Zfh[min] ISA extensions[1]. Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view [1] Signed-off-by: Clément Léger <cleger@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231114141256.126749-12-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-12-12dt-bindings: riscv: add vector crypto ISA extensions descriptionClément Léger1-0/+96
Add Zv* vector crypto extensions that were added in "RISC-V Cryptography Extensions Volume II" specificationi[1]: - Zvbb: Vector Basic Bit-manipulation - Zvbc: Vector Carryless Multiplication - Zvkb: Vector Cryptography Bit-manipulation - Zvkg: Vector GCM/GMAC. - Zvkned: NIST Suite: Vector AES Block Cipher - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash - Zvksed: ShangMi Suite: SM4 Block Cipher - Zvksh: ShangMi Suite: SM3 Secure Hash - Zvkn: NIST Algorithm Suite - Zvknc: NIST Algorithm Suite with carryless multiply - Zvkng: NIST Algorithm Suite with GCM. - Zvks: ShangMi Algorithm Suite - Zvksc: ShangMi Algorithm Suite with carryless multiplication - Zvksg: ShangMi Algorithm Suite with GCM. - Zvkt: Vector Data-Independent Execution Latency. Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view [1] Signed-off-by: Clément Léger <cleger@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231114141256.126749-9-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-12-12dt-bindings: riscv: add scalar crypto ISA extensions descriptionClément Léger1-0/+80
Add description for scalar crypto ISA extensions: - Zbkb - Zbkc - Zbkx - Zknd - Zkne - Zknh - Zkr - Zksed - Zksh - Zkt Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231114141256.126749-6-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-11-30Merge patch series "Add Huashan Pi board support"Conor Dooley1-0/+4
Inochi Amaoto <inochiama@outlook.com> says: Huashan Pi board is an embedded development platform based on the CV1812H chip. Add minimal device tree files for this board. Currently, it can boot to a basic shell. NOTE: this series is based on the Jisheng's Milk-V Duo patch. Link: https://en.sophgo.com/product/introduce/huashan.html Link: https://en.sophgo.com/product/introduce/cv181xH.html Link: https://lore.kernel.org/linux-riscv/20231006121449.721-1-jszhang@kernel.org/ Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-11-30dt-bindings: riscv: Add SOPHGO Huashan Pi board compatiblesInochi Amaoto1-0/+4
Document the compatible strings for the SOPHGO Huashan Pi board which uses the SOPHGO CV1812H SoC. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Link: https://en.sophgo.com/product/introduce/huashan.html Link: https://en.sophgo.com/product/introduce/cv181xH.html Acked-by: Chen Wang <unicorn_wang@outlook.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-11-02Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds1-0/+12
Pull kvm updates from Paolo Bonzini: "ARM: - Generalized infrastructure for 'writable' ID registers, effectively allowing userspace to opt-out of certain vCPU features for its guest - Optimization for vSGI injection, opportunistically compressing MPIDR to vCPU mapping into a table - Improvements to KVM's PMU emulation, allowing userspace to select the number of PMCs available to a VM - Guest support for memory operation instructions (FEAT_MOPS) - Cleanups to handling feature flags in KVM_ARM_VCPU_INIT, squashing bugs and getting rid of useless code - Changes to the way the SMCCC filter is constructed, avoiding wasted memory allocations when not in use - Load the stage-2 MMU context at vcpu_load() for VHE systems, reducing the overhead of errata mitigations - Miscellaneous kernel and selftest fixes LoongArch: - New architecture for kvm. The hardware uses the same model as x86, s390 and RISC-V, where guest/host mode is orthogonal to supervisor/user mode. The virtualization extensions are very similar to MIPS, therefore the code also has some similarities but it's been cleaned up to avoid some of the historical bogosities that are found in arch/mips. The kernel emulates MMU, timer and CSR accesses, while interrupt controllers are only emulated in userspace, at least for now. RISC-V: - Support for the Smstateen and Zicond extensions - Support for virtualizing senvcfg - Support for virtualized SBI debug console (DBCN) S390: - Nested page table management can be monitored through tracepoints and statistics x86: - Fix incorrect handling of VMX posted interrupt descriptor in KVM_SET_LAPIC, which could result in a dropped timer IRQ - Avoid WARN on systems with Intel IPI virtualization - Add CONFIG_KVM_MAX_NR_VCPUS, to allow supporting up to 4096 vCPUs without forcing more common use cases to eat the extra memory overhead. - Add virtualization support for AMD SRSO mitigation (IBPB_BRTYPE and SBPB, aka Selective Branch Predictor Barrier). - Fix a bug where restoring a vCPU snapshot that was taken within 1 second of creating the original vCPU would cause KVM to try to synchronize the vCPU's TSC and thus clobber the correct TSC being set by userspace. - Compute guest wall clock using a single TSC read to avoid generating an inaccurate time, e.g. if the vCPU is preempted between multiple TSC reads. - "Virtualize" HWCR.TscFreqSel to make Linux guests happy, which complain about a "Firmware Bug" if the bit isn't set for select F/M/S combos. Likewise "virtualize" (ignore) MSR_AMD64_TW_CFG to appease Windows Server 2022. - Don't apply side effects to Hyper-V's synthetic timer on writes from userspace to fix an issue where the auto-enable behavior can trigger spurious interrupts, i.e. do auto-enabling only for guest writes. - Remove an unnecessary kick of all vCPUs when synchronizing the dirty log without PML enabled. - Advertise "support" for non-serializing FS/GS base MSR writes as appropriate. - Harden the fast page fault path to guard against encountering an invalid root when walking SPTEs. - Omit "struct kvm_vcpu_xen" entirely when CONFIG_KVM_XEN=n. - Use the fast path directly from the timer callback when delivering Xen timer events, instead of waiting for the next iteration of the run loop. This was not done so far because previously proposed code had races, but now care is taken to stop the hrtimer at critical points such as restarting the timer or saving the timer information for userspace. - Follow the lead of upstream Xen and ignore the VCPU_SSHOTTMR_future flag. - Optimize injection of PMU interrupts that are simultaneous with NMIs. - Usual handful of fixes for typos and other warts. x86 - MTRR/PAT fixes and optimizations: - Clean up code that deals with honoring guest MTRRs when the VM has non-coherent DMA and host MTRRs are ignored, i.e. EPT is enabled. - Zap EPT entries when non-coherent DMA assignment stops/start to prevent using stale entries with the wrong memtype. - Don't ignore guest PAT for CR0.CD=1 && KVM_X86_QUIRK_CD_NW_CLEARED=y This was done as a workaround for virtual machine BIOSes that did not bother to clear CR0.CD (because ancient KVM/QEMU did not bother to set it, in turn), and there's zero reason to extend the quirk to also ignore guest PAT. x86 - SEV fixes: - Report KVM_EXIT_SHUTDOWN instead of EINVAL if KVM intercepts SHUTDOWN while running an SEV-ES guest. - Clean up the recognition of emulation failures on SEV guests, when KVM would like to "skip" the instruction but it had already been partially emulated. This makes it possible to drop a hack that second guessed the (insufficient) information provided by the emulator, and just do the right thing. Documentation: - Various updates and fixes, mostly for x86 - MTRR and PAT fixes and optimizations" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (164 commits) KVM: selftests: Avoid using forced target for generating arm64 headers tools headers arm64: Fix references to top srcdir in Makefile KVM: arm64: Add tracepoint for MMIO accesses where ISV==0 KVM: arm64: selftest: Perform ISB before reading PAR_EL1 KVM: arm64: selftest: Add the missing .guest_prepare() KVM: arm64: Always invalidate TLB for stage-2 permission faults KVM: x86: Service NMI requests after PMI requests in VM-Enter path KVM: arm64: Handle AArch32 SPSR_{irq,abt,und,fiq} as RAZ/WI KVM: arm64: Do not let a L1 hypervisor access the *32_EL2 sysregs KVM: arm64: Refine _EL2 system register list that require trap reinjection arm64: Add missing _EL2 encodings arm64: Add missing _EL12 encodings KVM: selftests: aarch64: vPMU test for validating user accesses KVM: selftests: aarch64: vPMU register test for unimplemented counters KVM: selftests: aarch64: vPMU register test for implemented counters KVM: selftests: aarch64: Introduce vpmu_counter_access test tools: Import arm_pmuv3.h KVM: arm64: PMU: Allow userspace to limit PMCR_EL0.N for the guest KVM: arm64: Sanitize PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR} before first run KVM: arm64: Add {get,set}_user for PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR} ...
2023-11-01Merge tag 'soc-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2-0/+33
Pull SoC DT updates from Arnd Bergmann: "There are a couple new SoCs that are supported for the first time: - AMD Pensando Elba is a data processing unit based on Cortex-A72 CPU cores - Sophgo makes RISC-V based chips, and we now support the CV1800B chip used in the milkv-duo board and the massive sg2042 chip in the milkv-pioneer, a 64-core developer workstation. - Qualcomm Snapdragon 720G (sm7125) is a close relative of Snapdragon 7c and gets added with some Xiaomi phones - Renesas gains support for the R8A779F4 (R-Car S4-8) automotive SoC and the RZ/G3S (R9A08G045) embedded SoC. There are also a bunch of newly supported machines that use already supported chips. On the 32-bit side, we have: - USRobotics USR8200 is a NAS/Firewall/router based on the ancient Intel IXP4xx platform - A couple of machines based on the NXP i.MX5 and i.MX6 platforms - One machine each for Allwinner V3s, Aspeed AST2600, Microchip sama5d29 and ST STM32mp157 The other ones all use arm64 cores on chips from allwinner, amlogic, freescale, mediatek, qualcomm and rockchip" * tag 'soc-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (641 commits) ARM: dts: BCM5301X: Set switch ports for Linksys EA9200 ARM: dts: BCM5301X: Set fixed-link for extra Netgear R8000 CPU ports ARM: dts: BCM5301X: Explicitly disable unused switch CPU ports ARM: dts: BCM5301X: Relicense Vivek's code to the GPL 2.0+ / MIT ARM: dts: BCM5301X: Relicense Felix's code to the GPL 2.0+ / MIT ARM: dts: BCM5301X: Set MAC address for Asus RT-AC87U arm64: dts: socionext: add missing cache properties riscv: dts: thead: convert isa detection to new properties arm64: dts: Update cache properties for socionext arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports arm64: dts: ti: k3-am654-icssg2: add ICSSG2 Ethernet support arm64: dts: ti: k3-am65-main: Add ICSSG IEP nodes arm64: dts: ti: k3-am62p5-sk: Updates for SK EVM arm64: dts: ti: k3-am62p: Add nodes for more IPs arm64: dts: rockchip: Add Turing RK1 SoM support dt-bindings: arm: rockchip: Add Turing RK1 dt-bindings: vendor-prefixes: add turing arm64: dts: rockchip: Add DFI to rk3588s arm64: dts: rockchip: Add DFI to rk356x arm64: dts: rockchip: Always enable DFI on rk3399 ...
2023-10-12dt-bindings: riscv: Add Zicond extension entryAnup Patel1-0/+6
Add an entry for the Zicond extension to the riscv,isa-extensions property. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-10-12dt-bindings: riscv: Add smstateen entryMayuresh Chitale1-0/+6
Add an entry for the Smstateen extension to the riscv,isa-extensions property. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-10-07dt-bindings: riscv: Add Milk-V Duo board compatiblesJisheng Zhang1-0/+4
Document the compatible strings for the Milk-V Duo board[1] which uses the SOPHGO CV1800B SoC[2]. Link: https://milkv.io/duo [1] Link: https://en.sophgo.com/product/introduce/cv180xB.html [2] Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-06dt-bindings: riscv: Add T-HEAD C920 compatiblesChen Wang1-0/+1
The C920 is RISC-V CPU cores from T-HEAD Semiconductor. Notably, the C920 core is used in the SOPHGO's SG2042 SoC. Acked-by: Chao Wei <chao.wei@sophgo.com> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-06dt-bindings: riscv: add sophgo sg2042 bindingsChen Wang1-0/+28
Add DT binding documentation for the SOPHGO's SG2042 Soc [1] and the Milk-V Pioneer board [2]. Link: https://en.sophgo.com/product/introduce/sg2042.html [1] Link: https://milkv.io/pioneer [2] Acked-by: Chao Wei <chao.wei@sophgo.com> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-09-22dt-bindings: riscv: cpus: Add missing additionalProperties on ↵Rob Herring1-0/+1
interrupt-controller node The "interrupt-controller" CPU child node is missing constraints on extra properties. Add "additionalProperties: false" to fix this. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230915201946.4184468-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
2023-08-16dt-bindings: riscv: Add BeagleV Ahead board compatiblesDrew Fustini1-0/+4
Document the compatible strings for the BeagleV Ahead board which uses the T-Head TH1520 SoC. Link: https://beagleboard.org/beaglev-ahead Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Drew Fustini <dfustini@baylibre.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-05dt-bindings: riscv: deprecate riscv,isaConor Dooley2-23/+270
intro ===== When the RISC-V dt-bindings were accepted upstream in Linux, the base ISA etc had yet to be ratified. By the ratification of the base ISA, incompatible changes had snuck into the specifications - for example the Zicsr and Zifencei extensions were spun out of the base ISA. Fast forward to today, and the reason for this patch. Currently the riscv,isa dt property permits only a specific subset of the ISA string - in particular it excludes version numbering. With the current constraints, it is not possible to discern whether "rv64i" means that the hart supports the fence.i instruction, for example. Future systems may choose to implement their own instruction fencing, perhaps using a vendor extension, or they may not implement the optional counter extensions. Software needs a way to determine this. versioning schemes ================== "Use the extension versions that are described in the ISA manual" you may say, and it's not like this has not been considered. Firstly, software that parses the riscv,isa property at runtime will need to contain a lookup table of some sort that maps arbitrary versions to versions it understands. There is not a consistent application of version number applied to extensions, with a higgledy-piggledy collection of tags, "bare" and versioned documents awaiting the reader on the "recently ratified extensions" page: https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions As an aside, and this is reflected in the patch too, since many extensions have yet to appear in a release of the ISA specs, they are defined by commits in their respective "working draft" repositories. Secondly, there is an issue of backwards compatibility, whereby allowing numbers in the ISA string, some parsers may be broken. This would require an additional property to be created to even use the versions in this manner. ~boolean properties~ string array property ========================================== If a new property is needed, the whole approach may as well be looked at from the bottom up. A string with limited character choices etc is hardly the best approach for communicating extension information to software. Switching to using properties that are defined on a per extension basis, allows us to define explicit meanings for the DT representation of each extension - rather than the current situation where different operating systems or other bits of software may impart different meanings to characters in the string. Clearly the best source of meanings is the specifications themselves, this just provides us the ability to choose at what point in time the meaning is set. If an extension changes incompatibility in the future, a new property will be required. Off-list, some of the RVI folks have committed to shoring up the wording in either the ISA specifications, the riscv-isa-manual or so that in the future, modifications to and additions or removals of features will require a new extension. Codifying that assertion somewhere would make it quite unlikely that compatibility would be broken, but we have the tools required to deal with it, if & when it crops up. It is in our collective interest, as consumers of extension meanings, to define a scheme that enforces compatibility. The use of individual elements, rather than a single string, will also permit validation that the properties have a meaning, as well as potentially reject mutually exclusive combinations, or enforce dependencies between extensions. That would not have be possible with the current dt-schema infrastructure for arbitrary strings, as we would need to add a riscv,isa parser to dt-validate! That's not implemented in this patch, but rather left as future work (for the brave, or the foolish). parser simplicity ================= Many systems that parse DT at runtime already implement an function that can check for the presence of a string in an array of string, as it is similar to the process for parsing a list of compatible strings, so a bunch of new, custom, DT parsing should not be needed. Getting rid of "riscv,isa" parsing would be a nice simplification, but unfortunately for backwards compatibility with old dtbs, existing parsers may not be removable - which may greatly simplify dt parsing code. In Linux, for example, checking for whether a hart supports an extension becomes as simple as: of_property_match_string(node, "riscv,isa-extensions", "zicbom") vendor extensions ================= Compared to riscv,isa, this proposed scheme promotes vendor extensions, oft touted as the strength of RISC-V, to first-class citizens. At present, extensions are defined as meaning what the RISC-V ISA specifications say they do. There is no realistic way of using that interface to provide cross-platform definitions for what vendor extensions mean. Vendor extensions may also have even less consistency than RVI do in terms of versioning, or no care about backwards compatibility. The new property allows us to assign explicit meanings on a per vendor extension basis, backed up by a description of their meanings. fin === Create a new file to store the extension meanings and a new riscv,isa-base property to replace the aspect of riscv,isa that is not represented by the new property - the base ISA implemented by a hart. As a starting point, add properties for extensions currently used in Linux. Finally, mark riscv,isa as deprecated, as removing support for it in existing programs would be an ABI break. CC: Palmer Dabbelt <palmer@dabbelt.com> CC: Paul Walmsley <paul.walmsley@sifive.com> CC: Rob Herring <robh+dt@kernel.org> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> CC: Alistair Francis <alistair.francis@wdc.com> CC: Andrew Jones <ajones@ventanamicro.com> CC: Anup Patel <apatel@ventanamicro.com> CC: Atish Patra <atishp@atishpatra.org> CC: Jessica Clarke <jrtc27@jrtc27.com> CC: Rick Chen <rick@andestech.com> CC: Leo <ycliang@andestech.com> CC: Oleksii <oleksii.kurochko@gmail.com> CC: linux-riscv@lists.infradead.org CC: qemu-riscv@nongnu.org CC: u-boot@lists.denx.de CC: devicetree@vger.kernel.org CC: linux-kernel@vger.kernel.org Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230702-eats-scorebook-c951f170d29f@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-06-30Merge tag 'riscv-for-linus-6.5-mw1' of ↵Linus Torvalds1-7/+13
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for ACPI - Various cleanups to the ISA string parsing, including making them case-insensitive - Support for the vector extension - Support for independent irq/softirq stacks - Our CPU DT binding now has "unevaluatedProperties: false" * tag 'riscv-for-linus-6.5-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (78 commits) riscv: hibernate: remove WARN_ON in save_processor_state dt-bindings: riscv: cpus: switch to unevaluatedProperties: false dt-bindings: riscv: cpus: add a ref the common cpu schema riscv: stack: Add config of thread stack size riscv: stack: Support HAVE_SOFTIRQ_ON_OWN_STACK riscv: stack: Support HAVE_IRQ_EXIT_ON_IRQ_STACK RISC-V: always report presence of extensions formerly part of the base ISA dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support RISC-V: remove decrement/increment dance in ISA string parser RISC-V: rework comments in ISA string parser RISC-V: validate riscv,isa at boot, not during ISA string parsing RISC-V: split early & late of_node to hartid mapping RISC-V: simplify register width check in ISA string parsing perf: RISC-V: Limit the number of counters returned from SBI riscv: replace deprecated scall with ecall riscv: uprobes: Restore thread.bad_cause riscv: mm: try VMA lock-based page fault handling first riscv: mm: Pre-allocate PGD entries for vmalloc/modules area RISC-V: hwprobe: Expose Zba, Zbb, and Zbs RISC-V: Track ISA extensions per hart ...
2023-06-29Merge tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-0/+29
Pull ARM SoC devicetree updates from Arnd Bergmann: "The biggest change this time is for the 32-bit devicetree files, which are all moved to a new location, using separate subdirectories for each SoC vendor, following the same scheme that is used on arm64, mips and riscv. This has been discussed for many years, but so far we never did this as there was a plan to move the files out of the kernel entirely, which has never happened. The impact of this will be that all external patches no longer apply, and anything depending on the location of the dtb files in the build directory will have to change. The installed files after 'make dtbs_install' keep the current location. There are six added SoCs here that are largely variants of previously added chips. Two other chips are added in a separate branch along with their device drivers. - The Samsung Exynos 4212 makes its return after the Samsung Galaxy Express phone is addded at last. The SoC support was originally added in 2012 but removed again in 2017 as it was unused at the time. - Amlogic C3 is a Cortex-A35 based smart IP camera chip - Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of the still common MSM8916 (Snapdragon 410) phone chip that has been supported for a long time. - Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end laptop chips, used in the Lenovo Flex 5G, which is added along with the reference board. - Qualcomm SDX75 is the latest generation modem chip that is used as a peripherial in phones but can also run a standalone Linux. Unlike the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55. - Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the Xuantie C910 core, a step up from all previously added rv64 chips. All of the above come with reference board implementations, those included there are 39 new board files, but only five more 32-bit this time, probably a new low: - Marantec Maveo board based on dhcor imx6ull module - Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip - Epson Moverio BT-200 AR glasses based on TI OMAP4 - PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM - ICnova ADB4006 board based on Allwinner A20 On the 64-bit side, there are also fewer addded machines than we had in the recent releases: - Three boards based on NXP i.MX8: Emtop SoM & Baseboard, NXP i.MX8MM EVKB board and i.MX8MP based Gateworks Venice gw7905-2x device. - NVIDIA IGX Orin and Jetson Orin Nano boards, both based on tegra234 - Qualcomm gains support for 6 reference boards on various members of their IPQ networking SoC series, as well as the Sony Xperia M4 Aqua phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board on top of the various reference platforms for their new chips. - Rockchips support for several newer boards: Indiedroid Nova (rk3588), Edgeble Neural Compute Module 6B (rk3588), FriendlyARM NanoPi R2C Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn Fastrhino R66S/R68S (rk3568) - TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex Verdin family with AM62 COM, carrier and dev boards Other changes to existing boards contain the usual minor improvements along with - continued updates to clean up dts files based on dtc warnings and binding checks, in particular cache properties and node names - support for devicetree overlays on at91, bcm283x - significant additions to existing SoC support on mediatek, qualcomm, ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST STM32MP1 As usual, a lot more detail is available in the individual merge commits" * tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (926 commits) ARM: mvebu: fix unit address on armada-390-db flash ARM: dts: Move .dts files to vendor sub-directories kbuild: Support flat DTBs install ARM: dts: Add .dts files missing from the build ARM: dts: allwinner: Use quoted #include ARM: dts: lan966x: kontron-d10: add PHY interrupts ARM: dts: lan966x: kontron-d10: fix SPI CS ARM: dts: lan966x: kontron-d10: fix board reset ARM: dts: at91: Enable device-tree overlay support for AT91 boards arm: dts: Enable device-tree overlay support for AT91 boards arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller ARM: dts: at91: use generic name for shutdown controller ARM: dts: BCM5301X: Add cells sizes to PCIe nodes dt-bindings: firmware: brcm,kona-smc: convert to YAML riscv: dts: sort makefile entries by directory riscv: defconfig: enable T-HEAD SoC MAINTAINERS: add entry for T-HEAD RISC-V SoC riscv: dts: thead: add sipeed Lichee Pi 4A board device tree riscv: dts: add initial T-HEAD TH1520 SoC device tree riscv: Add the T-HEAD SoC family Kconfig option ...
2023-06-23Merge patch series "dt-bindings: riscv: cpus: switch to ↵Palmer Dabbelt1-1/+7
unevaluatedProperties: false" Conor Dooley <conor@kernel.org> says: From: Conor Dooley <conor.dooley@microchip.com> Do the various bits needed to drop the additionalProperties: true that we currently have in riscv/cpu.yaml, to permit actually enforcing what people put in cpus nodes. * b4-shazam-merge: dt-bindings: riscv: cpus: switch to unevaluatedProperties: false dt-bindings: riscv: cpus: add a ref the common cpu schema Link: https://lore.kernel.org/r/20230615-creamer-emu-ade0fa0bdb68@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-06-23Merge patch series "ISA string parser cleanups"Palmer Dabbelt1-2/+2
Conor Dooley <conor@kernel.org> says: From: Conor Dooley <conor.dooley@microchip.com> Here are some bits that were discussed with Drew on the "should we allow caps" threads that I have now created patches for: - splitting of riscv_of_processor_hartid() into two distinct functions, one for use purely during early boot, prior to the establishment of the possible-cpus mask & another to fit the other current use-cases - that then allows us to then completely skip some validation of the hartid in the parser - the biggest diff in the series is a rework of the comments in the parser, as I have mostly found the existing (sparse) ones to not be all that helpful whenever I have to go back and look at it - from writing the comments, I found a conditional doing a bit of a dance that I found counter-intuitive, so I've had a go at making that match what I would expect a little better - `i` implies 4 other extensions, so add them as extensions and set them for the craic. Sure why not like... * b4-shazam-merge: RISC-V: always report presence of extensions formerly part of the base ISA dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support RISC-V: remove decrement/increment dance in ISA string parser RISC-V: rework comments in ISA string parser RISC-V: validate riscv,isa at boot, not during ISA string parsing RISC-V: split early & late of_node to hartid mapping RISC-V: simplify register width check in ISA string parsing Link: https://lore.kernel.org/r/20230607-audacity-overhaul-82bb867a825f@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-06-22dt-bindings: riscv: cpus: switch to unevaluatedProperties: falseConor Dooley1-1/+1
To permit validation of cpu nodes, swap "additionalProperties: true" out for "unevaluatedProperties: false". Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230615-viper-stoic-1ff8efd7d51d@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-06-22dt-bindings: riscv: cpus: add a ref the common cpu schemaConor Dooley1-0/+6
To permit validation of RISC-V cpu nodes, "additionalProperties: true" needs to be swapped for "unevaluatedProperties: false". To facilitate this in a way that passes dt_binding_check, a reference to the cpu schema is required. Disallow the generic cache-op-block-size property that that drags in, since the RISC-V CBO extensions do not require a common size, and have individual properties. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230615-dubiously-parasail-79d34cefedce@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-06-21dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm supportConor Dooley1-2/+2
Similar to commit 41ebfc91f785 ("dt-bindings: riscv: explicitly mention assumption of Zicsr & Zifencei support"), the Zicntr and Zihpm extensions also used to be part of the base ISA but were removed after the bindings were merged. Document the assumption of their presence in the base ISA. Suggested-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230607-rerun-retinal-5e8ba89e98f1@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-06-19dt-bindings: riscv: cpus: drop unneeded quotesKrzysztof Kozlowski1-3/+3
Cleanup bindings dropping unneeded quotes. Once all these are fixed, checking for this can be enabled in yamllint. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230609140706.64623-1-krzysztof.kozlowski@linaro.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-06-17dt-bindings: riscv: Add T-HEAD TH1520 board compatiblesJisheng Zhang1-0/+29
Several SoMs and boards are available that feature the T-HEAD TH1520 SoC. Document the compatible strings. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-06-08dt-bindings: Change Damien Le Moal's contact emailDamien Le Moal1-1/+1
Change my email address to dlemoal@kernel.org. Signed-off-by: Damien Le Moal <dlemoal@kernel.org> Link: https://lore.kernel.org/r/20230514222614.115299-1-dlemoal@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
2023-06-06dt-bindings: riscv: drop invalid comment about riscv,isa lower-case reasoningConor Dooley1-1/+1
"Ease of parsing" may have been the initial argument for keeping this string in lower-case, but parsers may have been written that expect lower-case only. For example, the one in released kernels currently does not behave correctly for multi-letter extensions that begin with a capital letter. Allowing upper-case here brings about no benefit but would break compatibility between new devicetrees and older kernels. Drop the comment to avoid confusing people. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/tencent_3B8290DDC66D3E624132ED39C7465CDC9807@qq.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-05-01dt-bindings: riscv: explicitly mention assumption of Zicsr & Zifencei supportConor Dooley1-0/+6
The dt-binding was defined before the extraction of csr access and fence.i into their own extensions, and thus the presence of the I base extension implies Zicsr and Zifencei. There's no harm in adding them obviously, but for backwards compatibility with DTs that existed prior to that extraction, software is unable to differentiate between "i" and "i_zicsr_zifencei" without any further information. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230427-fence-blurred-c92fb69d4137@wendy Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-04-28Merge tag 'riscv-for-linus-6.4-mw1' of ↵Linus Torvalds1-0/+6
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for runtime detection of the Svnapot extension - Support for Zicboz when clearing pages - We've moved to GENERIC_ENTRY - Support for !MMU on rv32 systems - The linear region is now mapped via huge pages - Support for building relocatable kernels - Support for the hwprobe interface - Various fixes and cleanups throughout the tree * tag 'riscv-for-linus-6.4-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (57 commits) RISC-V: hwprobe: Explicity check for -1 in vdso init RISC-V: hwprobe: There can only be one first riscv: Allow to downgrade paging mode from the command line dt-bindings: riscv: add sv57 mmu-type RISC-V: hwprobe: Remove __init on probe_vendor_features() riscv: Use --emit-relocs in order to move .rela.dyn in init riscv: Check relocations at compile time powerpc: Move script to check relocations at compile time in scripts/ riscv: Introduce CONFIG_RELOCATABLE riscv: Move .rela.dyn outside of init to avoid empty relocations riscv: Prepare EFI header for relocatable kernels riscv: Unconditionnally select KASAN_VMALLOC if KASAN riscv: Fix ptdump when KASAN is enabled riscv: Fix EFI stub usage of KASAN instrumented strcmp function riscv: Move DTB_EARLY_BASE_VA to the kernel address space riscv: Rework kasan population functions riscv: Split early and final KASAN population functions riscv: Use PUD/P4D/PGD pages for the linear mapping riscv: Move the linear mapping creation in its own function riscv: Get rid of riscv_pfn_base variable ...
2023-04-27Merge tag 'devicetree-for-6.4-1' of ↵Linus Torvalds1-170/+0
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: "Bindings: - Convert Qcom IOMMU, Amlogic timer, Freescale sec-v4.0, Toshiba TC358764 display bridge, Parade PS8622 display bridge, and Xilinx FPGA bindings to DT schema format - Add qdu1000 and sa8775p SoC support to Qcom PDC interrupt controller - Add MediaTek MT8365 UART and SYSIRQ bindings - Add Arm Cortex-A78C and X1C core compatibles - Add vendor prefix for Novatek - Remove bindings for stih415, sti416, stid127 platforms - Drop uneeded quotes in schema files. This is preparation for yamllint checking quoting for us. - Add missing (unevaluated|additional)Properties constraints on child node schemas - Clean-up schema comments formatting - Fix I2C and SPI node bus names in schema examples - Clean-up some display compatibles schema syntax - Fix incorrect references to lvds.yaml - Gather all cache controller bindings in a common directory DT core: - Convert unittest to new void .remove platform device hook - kerneldoc fixes for DT address of_pci_range_to_resource/ of_address_to_resource functions" * tag 'devicetree-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (46 commits) dt-bindings: rng: Drop unneeded quotes dt-bindings: arm/soc: mediatek: Drop unneeded quotes dt-bindings: soc: qcom: Drop unneeded quotes dt-bindings: i2c: samsung: Fix 'deprecated' value dt-bindings: display: Fix lvds.yaml references dt-bindings: display: simplify compatibles syntax dt-bindings: display: mediatek: simplify compatibles syntax dt-bindings: drm/bridge: ti-sn65dsi86: Fix the video-interfaces.yaml references dt-bindings: timer: Drop unneeded quotes dt-bindings: interrupt-controller: qcom,pdc: document qcom,qdu1000-pdc dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775p dt-bindings: reset: remove stih415/stih416 reset dt-bindings: net: dwmac: sti: remove stih415/sti416/stid127 dt-bindings: irqchip: sti: remove stih415/stih416 and stid127 dt-bindings: iommu: Convert QCOM IOMMU to YAML dt-bindings: irqchip: ti,sci-inta: Add optional power-domains property dt-bindings: Add missing (unevaluated|additional)Properties on child node schemas of: address: Reshuffle to remove forward declarations of: address: Fix documented return value of of_pci_range_to_resource() of: address: Document return value of of_address_to_resource() ...
2023-04-26dt-bindings: riscv: add sv57 mmu-typeConor Dooley1-0/+1
Dumping the dtb from new versions of QEMU warns that sv57 is an undocumented mmu-type. The kernel has supported sv57 for about a year, so bring it into the fold. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230424-rival-habitual-478567c516f0@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-04-14Merge tag 'sunxi-dt-for-6.4-1' of ↵Arnd Bergmann1-0/+5
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt - added D1 crypto node - enabled DVFS on OrangePi PC2 board - added GPIO line names on Nezha D1 board - added suniv USB nodes and enabled on licheepi-nano - new suniv boards: PopStick v1.1 and Lctech Pi - added Allwinner T113-s DTSI - added MangoPi MQ-R T113-s board variant - swapped DMA names for A23, A31, A33, D1, H3, H5, V3s * tag 'sunxi-dt-for-6.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: riscv: dts: allwinner: d1: Switch dma-names order for snps,dw-apb-uart nodes ARM: dts: sunxi: h3/h5: Switch dma-names order for snps,dw-apb-uart nodes ARM: dts: sun8i: v3s: Switch dma-names order for snps,dw-apb-uart nodes ARM: dts: sun8i: a23/a33: Switch dma-names order for snps,dw-apb-uart nodes ARM: dts: sun6i: a31: Switch dma-names order for snps,dw-apb-uart nodes ARM: dts: sunxi: add MangoPi MQ-R-T113 board dt-bindings: arm: sunxi: document MangoPi MQ-R board names ARM: dts: sunxi: add Allwinner T113-s SoC .dtsi dts: add riscv include prefix link ARM: dts: suniv: Add Lctech Pi F1C200s devicetree ARM: dts: suniv: add device tree for PopStick v1.1 dt-binding: arm: sunxi: add two board compatible strings dt-bindings: vendor-prefixes: add Source Parts and Lctech names ARM: dts: suniv: licheepi-nano: enable USB ARM: dts: suniv: add USB-related device nodes riscv: dts: nezha-d1: add gpio-line-names arm64: dts: allwinner: h5: OrangePi PC2: add OPP table to enable DVFS riscv: dts: allwinner: d1: Add crypto engine node Link: https://lore.kernel.org/r/20230408125156.GA17050@jernej-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-04-05dt-bindings: riscv: Add SiFive S7 compatibleHal Feng1-0/+1
Add a new compatible string in cpu.yaml for SiFive S7 CPU core which is used on SiFive U74-MC core complex etc. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-04dt-bindings: move cache controller bindings to a cache directoryConor Dooley1-170/+0
There's a bunch of bindings for (mostly l2) cache controllers scattered to the four winds, move them to a common directory. I renamed the freescale l2cache.txt file, as while that might make sense when the parent dir is fsl, it's confusing after the move. The two Marvell bindings have had a "marvell," prefix added to match their compatibles. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230330173255.109731-1-conor@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
2023-03-27dt-bindings: arm: sunxi: document MangoPi MQ-R board namesAndre Przywara1-0/+5
The MangoPi MQ-R board is a small development board, using Allwinner SoCs with co-packaged DRAM. There are versions with a RISC-V core and ones with two Arm Cortex-A7 cores. Add the board/SoC compatible string pair to the list of known boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230320005249.13403-4-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-03-14dt-bindings: riscv: Document cboz-block-sizeAndrew Jones1-0/+5
The Zicboz operation (cbo.zero) operates on a block-size defined for the cpu-core. While we already have the riscv,cbom-block-size property, it only provides the block size for Zicbom operations. Even though it's likely Zicboz and Zicbom will use the same size, that's not required by the specification. Create another property specifically for Zicboz. Cc: Rob Herring <robh@kernel.org> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230224162631.405473-4-ajones@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-27Merge tag 'soc-drivers-6.3' of ↵Linus Torvalds1-1/+8
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "As usual, there are lots of minor driver changes across SoC platforms from NXP, Amlogic, AMD Zynq, Mediatek, Qualcomm, Apple and Samsung. These usually add support for additional chip variations in existing drivers, but also add features or bugfixes. The SCMI firmware subsystem gains a unified raw userspace interface through debugfs, which can be used for validation purposes. Newly added drivers include: - New power management drivers for StarFive JH7110, Allwinner D1 and Renesas RZ/V2M - A driver for Qualcomm battery and power supply status - A SoC device driver for identifying Nuvoton WPCM450 chips - A regulator coupler driver for Mediatek MT81xxv" * tag 'soc-drivers-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (165 commits) power: supply: Introduce Qualcomm PMIC GLINK power supply soc: apple: rtkit: Do not copy the reg state structure to the stack soc: sunxi: SUN20I_PPU should depend on PM memory: renesas-rpc-if: Remove redundant division of dummy soc: qcom: socinfo: Add IDs for IPQ5332 and its variant dt-bindings: arm: qcom,ids: Add IDs for IPQ5332 and its variant dt-bindings: power: qcom,rpmpd: add RPMH_REGULATOR_LEVEL_LOW_SVS_L1 firmware: qcom_scm: Move qcom_scm.h to include/linux/firmware/qcom/ MAINTAINERS: Update qcom CPR maintainer entry dt-bindings: firmware: document Qualcomm SM8550 SCM dt-bindings: firmware: qcom,scm: add qcom,scm-sa8775p compatible soc: qcom: socinfo: Add Soc IDs for IPQ8064 and variants dt-bindings: arm: qcom,ids: Add Soc IDs for IPQ8064 and variants soc: qcom: socinfo: Add support for new field in revision 17 soc: qcom: smd-rpm: Add IPQ9574 compatible soc: qcom: pmic_glink: remove redundant calculation of svid soc: qcom: stats: Populate all subsystem debugfs files dt-bindings: soc: qcom,rpmh-rsc: Update to allow for generic nodes soc: qcom: pmic_glink: add CONFIG_NET/CONFIG_OF dependencies soc: qcom: pmic_glink: Introduce altmode support ...
2023-02-25Merge tag 'riscv-for-linus-6.3-mw1' of ↵Linus Torvalds1-0/+6
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: "There's a bunch of fixes/cleanups throughout the tree as usual, but we also have a handful of new features: - Various improvements to the extension detection and alternative patching infrastructure - Zbb-optimized string routines - Support for cpu-capacity in the RISC-V DT bindings - Zicbom no longer depends on toolchain support - Some performance and code size improvements to ftrace - Support for ARCH_WANT_LD_ORPHAN_WARN - Oops now contain the faulting instruction" * tag 'riscv-for-linus-6.3-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (67 commits) RISC-V: add a spin_shadow_stack declaration riscv: mm: hugetlb: Enable ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP riscv: Add header include guards to insn.h riscv: alternative: proceed one more instruction for auipc/jalr pair riscv: Avoid enabling interrupts in die() riscv, mm: Perform BPF exhandler fixup on page fault RISC-V: take text_mutex during alternative patching riscv: hwcap: Don't alphabetize ISA extension IDs RISC-V: fix ordering of Zbb extension riscv: jump_label: Fixup unaligned arch_static_branch function RISC-V: Only provide the single-letter extensions in HWCAP riscv: mm: fix regression due to update_mmu_cache change scripts/decodecode: Add support for RISC-V riscv: Add instruction dump to RISC-V splats riscv: select ARCH_WANT_LD_ORPHAN_WARN for !XIP_KERNEL riscv: vmlinux.lds.S: explicitly catch .init.bss sections from EFI stub riscv: vmlinux.lds.S: explicitly catch .riscv.attributes sections riscv: vmlinux.lds.S: explicitly catch .rela.dyn symbols riscv: lds: define RUNTIME_DISCARD_EXIT RISC-V: move some stray __RISCV_INSN_FUNCS definitions from kprobes ...
2023-02-24Merge tag 'devicetree-for-6.3' of ↵Linus Torvalds1-2/+1
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: "DT core: - Add node lifecycle unit tests - Add of_property_present() helper aligned with fwnode API - Print more information on reserved regions on boot - Update dtc to upstream v1.6.1-66-gabbd523bae6e - Use strscpy() to instead of strncpy() in DT core - Add option for schema validation on %.dtb targets Bindings: - Add/fix support for listing multiple patterns in DT_SCHEMA_FILES - Rework external memory controller/bus bindings to properly support controller specific child node properties - Convert loongson,ls1x-intc, fcs,fusb302, sil,sii8620, Rockchip RK3399 PCIe, Synquacer I2C, and Synquacer EXIU bindings to DT schema format - Add RiscV SBI PMU event mapping binding - Add missing contraints on Arm SCMI child node allowed properties - Add a bunch of missing Socionext UniPhier glue block bindings and example fixes - Various fixes for duplicate or conflicting type definitions on DT properties" * tag 'devicetree-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (66 commits) dt-bindings: regulator: Add mps,mpq7932 power-management IC of: dynamic: Fix spelling mistake "kojbect" -> "kobject" dt-bindings: drop Sagar Kadam from SiFive binding maintainership dt-bindings: sram: qcom,imem: document sm8450 dt-bindings: interrupt-controller: convert loongson,ls1x-intc.txt to json-schema dt-bindings: arm: Add Cortex-A715 and X3 of: dynamic: add lifecycle docbook info to node creation functions of: add consistency check to of_node_release() of: do not use "%pOF" printk format on node with refcount of zero of: unittest: add node lifecycle tests of: update kconfig unittest help of: add processing of EXPECT_NOT to of_unittest_expect of: prepare to add processing of EXPECT_NOT to of_unittest_expect of: Use preferred of_property_read_* functions of: Use of_property_present() helper of: Add of_property_present() helper of: reserved_mem: Use proper binary prefix dt-bindings: Fix multi pattern support in DT_SCHEMA_FILES of: reserved-mem: print out reserved-mem details during boot dt-bindings: serial: restrict possible child node names ...
2023-02-21dt-bindings: drop Sagar Kadam from SiFive binding maintainershipConor Dooley1-2/+1
Sagar's email listed in maintainers is bouncing as his division was sold off by the company. I attempted to contact him some days ago on what the bounce email told me was his new contact information, but am yet to receive a response. Paul and Palmer are listed on each of the bindings, both of whom were alive & well as of Wednesday so the bindings remain maintained. CC: Sagar Kadam <sagar.kadam@openfive.com> CC: Sagar Kadam <sagar.kadam@sifive.com> Link: https://lore.kernel.org/all/785425ca-4000-a7e4-16d6-4d68c91b158d@kernel.org/ Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230217180035.39658-1-conor@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
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