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2024-09-04net: microchip: add FDMA libraryDaniel Machon7-0/+417
Add new FDMA library for interacting with the FDMA engine on Microchip Sparx5 and lan966x switch chips, in an effort to reduce duplicate code and provide a common set of symbols and functions. Signed-off-by: Daniel Machon <[email protected]> Reviewed-by: Steen Hegelund <[email protected]> Reviewed-by: Jens Emil Schulz Østergaard <[email protected]> Reviewed-by: Horatiu Vultur <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-09-04net: mana: Fix error handling in mana_create_txq/rxq's NAPI cleanupSouradeep Chakrabarti2-9/+15
Currently napi_disable() gets called during rxq and txq cleanup, even before napi is enabled and hrtimer is initialized. It causes kernel panic. ? page_fault_oops+0x136/0x2b0 ? page_counter_cancel+0x2e/0x80 ? do_user_addr_fault+0x2f2/0x640 ? refill_obj_stock+0xc4/0x110 ? exc_page_fault+0x71/0x160 ? asm_exc_page_fault+0x27/0x30 ? __mmdrop+0x10/0x180 ? __mmdrop+0xec/0x180 ? hrtimer_active+0xd/0x50 hrtimer_try_to_cancel+0x2c/0xf0 hrtimer_cancel+0x15/0x30 napi_disable+0x65/0x90 mana_destroy_rxq+0x4c/0x2f0 mana_create_rxq.isra.0+0x56c/0x6d0 ? mana_uncfg_vport+0x50/0x50 mana_alloc_queues+0x21b/0x320 ? skb_dequeue+0x5f/0x80 Cc: [email protected] Fixes: e1b5683ff62e ("net: mana: Move NAPI from EQ to CQ") Signed-off-by: Souradeep Chakrabarti <[email protected]> Reviewed-by: Haiyang Zhang <[email protected]> Reviewed-by: Shradha Gupta <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-09-04pinctrl: baytrail: Drop duplicate return statementAndy Shevchenko1-3/+1
No need to repeat 'return ret;' inside and outside conditional. Just use one outside conditional for both cases. Acked-by: Mika Westerberg <[email protected]> Signed-off-by: Andy Shevchenko <[email protected]>
2024-09-04printk: nbcon: Use raw_cpu_ptr() instead of open codingJohn Ogness1-2/+1
There is no need to open code a non-migration-checking this_cpu_ptr(). That is exactly what raw_cpu_ptr() is. Signed-off-by: John Ogness <[email protected]> Reviewed-by: Petr Mladek <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Petr Mladek <[email protected]>
2024-09-04cpu: Fix W=1 build kernel-doc warningThorsten Blum1-3/+1
Building the kernel with W=1 generates the following warning: kernel/cpu.c:2693: warning: This comment starts with '/**', but isn't a kernel-doc comment. The function topology_is_core_online() is a simple helper function and doesn't need a kernel-doc comment. Use a normal comment instead. Signed-off-by: Thorsten Blum <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/all/[email protected]
2024-09-04Merge remote-tracking branch 'kvmarm/arm64-shared-6.12' into for-next/poeWill Deacon2-2/+3
Pull in the AT instruction conversion patch from the KVM arm64 tree, as this is a shared dependency between the POE series from Joey and the AT emulation series for Nested Virtualisation from Marc.
2024-09-04Merge branch 'linus' into smp/coreThomas Gleixner1385-8721/+17050
Pull in upstream changes so further patches don't conflict.
2024-09-04timers: Annotate possible non critical data race of next_expiryAnna-Maria Behnsen1-5/+37
Global timers could be expired remotely when the target CPU is idle. After a remote timer expiry, the remote timer_base->next_expiry value is updated while holding the timer_base->lock. When the formerly idle CPU becomes active at the same time and checks whether timers need to expire, this check is done lockless as it is on the local CPU. This could lead to a data race, which was reported by sysbot: https://lore.kernel.org/r/[email protected] When the value is read lockless but changed by the remote CPU, only two non critical scenarios could happen: 1) The already update value is read -> everything is perfect 2) The old value is read -> a superfluous timer soft interrupt is raised The same situation could happen when enqueueing a new first pinned timer by a remote CPU also with non critical scenarios: 1) The already update value is read -> everything is perfect 2) The old value is read -> when the CPU is idle, an IPI is executed nevertheless and when the CPU isn't idle, the updated value will be visible on the next tick and the timer might be late one jiffie. As this is very unlikely to happen, the overhead of doing the check under the lock is a way more effort, than a superfluous timer soft interrupt or a possible 1 jiffie delay of the timer. Document and annotate this non critical behavior in the code by using READ/WRITE_ONCE() pair when accessing timer_base->next_expiry. Reported-by: [email protected] Signed-off-by: Anna-Maria Behnsen <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Frederic Weisbecker <[email protected]> Link: https://lore.kernel.org/all/[email protected] Closes: https://lore.kernel.org/lkml/[email protected]
2024-09-04printk: Use the BITS_PER_LONG macroJinjie Ruan1-1/+2
sizeof(unsigned long) * 8 is the number of bits in an unsigned long variable, replace it with BITS_PER_LONG macro to make it simpler. Signed-off-by: Jinjie Ruan <[email protected]> Reviewed-by: John Ogness <[email protected]> Reviewed-by: Petr Mladek <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Petr Mladek <[email protected]>
2024-09-04Merge tag 'ti-driver-soc-for-v6.12' of ↵Arnd Bergmann5-201/+166
https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/drivers TI SoC driver updates for v6.12 - pm33xx/knav_qmss_queue/pruss: Cleanups around device_node scope based cleanups - knav: Additional fixes around of property - k3-ringacc: Optimizations for data structure * tag 'ti-driver-soc-for-v6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: soc: ti: pm33xx: do device_node auto cleanup soc: ti: knav_qmss_queue: do device_node auto cleanup soc: ti: pruss: do device_node auto cleanup soc: ti: pruss: factor out memories setup soc: ti: knav: Use of_property_read_variable_u32_array() soc: ti: knav: Drop unnecessary check for property presence soc: ti: k3-ringacc: Constify struct k3_ring_ops Link: https://lore.kernel.org/r/20240903155632.525twuumykwnfkiz@subtitle Signed-off-by: Arnd Bergmann <[email protected]>
2024-09-04clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SELMichel Alex1-2/+2
Commit 4e197ee880c24ecb63f7fe17449b3653bc64b03c ("clk: imx6ul: add ethernet refclock mux support") sets the internal clock as default ethernet clock. Since IMX6UL_CLK_ENET_REF cannot be parent for IMX6UL_CLK_ENET1_REF_SEL, the call to clk_set_parent() fails. IMX6UL_CLK_ENET1_REF_125M is the correct parent and shall be used instead. Same applies for IMX6UL_CLK_ENET2_REF_SEL, for which IMX6UL_CLK_ENET2_REF_125M is the correct parent. Cc: [email protected] Signed-off-by: Alex Michel <[email protected]> Reviewed-by: Oleksij Rempel <[email protected]> Link: https://lore.kernel.org/r/AS1P250MB0608F9CE4009DCE65C61EEDEA9922@AS1P250MB0608.EURP250.PROD.OUTLOOK.COM Signed-off-by: Abel Vesa <[email protected]>
2024-09-04iommu/amd: Do not set the D bit on AMD v2 table entriesJason Gunthorpe1-1/+1
The manual says that bit 6 is IGN for all Page-Table Base Address pointers, don't set it. Fixes: aaac38f61487 ("iommu/amd: Initial support for AMD IOMMU v2 page table") Reviewed-by: Vasant Hegde <[email protected]> Signed-off-by: Jason Gunthorpe <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
2024-09-04iommu/amd: Correct the reported page sizes from the V1 tableJason Gunthorpe1-1/+2
The HW only has 52 bits of physical address support, the supported page sizes should not have bits set beyond this. Further the spec says that the 6th level does not support any "default page size for translation entries" meaning leafs in the 6th level are not allowed too. Rework the definition to use GENMASK to build the range of supported pages from the top of physical to 4k. Nothing ever uses such large pages, so this is a cosmetic/documentation improvement only. Reported-by: Joao Martins <[email protected]> Reviewed-by: Vasant Hegde <[email protected]> Signed-off-by: Jason Gunthorpe <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
2024-09-04iommu/amd: Remove the confusing dummy iommu_flush_ops tlb opsJason Gunthorpe2-44/+0
The iommu driver is supposed to provide these ops to its io_pgtable implementation so that it can hook the invalidations and do the right thing. They are called by wrapper functions like io_pgtable_tlb_add_page() etc, which the AMD code never calls. Instead it directly calls the AMD IOMMU invalidation functions by casting to the struct protection_domain. Remove it all. Reviewed-by: Vasant Hegde <[email protected]> Signed-off-by: Jason Gunthorpe <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
2024-09-04iommu/amd: Fix typo of , instead of ;Jason Gunthorpe1-3/+3
Generates the same code, but is not the expected C style. Fixes: aaac38f61487 ("iommu/amd: Initial support for AMD IOMMU v2 page table") Reviewed-by: Vasant Hegde <[email protected]> Signed-off-by: Jason Gunthorpe <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
2024-09-04iommu/amd: Remove conditions from domain free pathsJason Gunthorpe1-19/+10
Don't use tlb as some flag to indicate if protection_domain_alloc() completed. Have protection_domain_alloc() unwind itself in the normal kernel style and require protection_domain_free() only be called on successful results of protection_domain_alloc(). Also, the amd_iommu_domain_free() op is never called by the core code with a NULL argument, so remove all the NULL tests as well. Reviewed-by: Vasant Hegde <[email protected]> Signed-off-by: Jason Gunthorpe <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
2024-09-04iommu/amd: Narrow the use of struct protection_domain to invalidationJason Gunthorpe2-19/+25
The AMD io_pgtable stuff doesn't implement the tlb ops callbacks, instead it invokes the invalidation ops directly on the struct protection_domain. Narrow the use of struct protection_domain to only those few code paths. Make everything else properly use struct amd_io_pgtable through the call chains, which is the correct modular type for an io-pgtable module. Signed-off-by: Jason Gunthorpe <[email protected]> Reviewed-by: Vasant Hegde <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
2024-09-04iommu/amd: Store the nid in io_pgtable_cfg instead of the domainJason Gunthorpe7-14/+20
We already have memory in the union here that is being wasted in AMD's case, use it to store the nid. Putting the nid here further isolates the io_pgtable code from the struct protection_domain. Fixup protection_domain_alloc so that the NID from the device is provided, at this point dev is never NULL for AMD so this will now allocate the first table pointer on the correct NUMA node. Signed-off-by: Jason Gunthorpe <[email protected]> Reviewed-by: Vasant Hegde <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
2024-09-04iommu/amd: Remove amd_io_pgtable::pgtbl_cfgJason Gunthorpe2-4/+4
This struct is already in iop.cfg, we don't need two. AMD is using this API sort of wrong, the cfg is supposed to be passed in and then the allocation function will allocate ops memory and copy the passed config into the new memory. Keep it kind of wrong and pass in the cfg memory that is already part of the pagetable struct. Reviewed-by: Vasant Hegde <[email protected]> Signed-off-by: Jason Gunthorpe <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
2024-09-04iommu/amd: Rename struct amd_io_pgtable iopt to pgtblJason Gunthorpe4-22/+22
There is struct protection_domain iopt and struct amd_io_pgtable iopt. Next patches are going to want to write domain.iopt.iopt.xx which is quite unnatural to read. Give one of them a different name, amd_io_pgtable has fewer references so call it pgtbl, to match pgtbl_cfg, instead. Suggested-by: Alejandro Jimenez <[email protected]> Reviewed-by: Vasant Hegde <[email protected]> Signed-off-by: Jason Gunthorpe <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
2024-09-04iommu/amd: Remove the amd_iommu_domain_set_pt_root() and relatedJason Gunthorpe2-37/+0
Looks like many refactorings here have left this confused. There is only one storage of the root/mode, it is in the iop struct. increase_address_space() calls amd_iommu_domain_set_pgtable() with values that it already stored in iop a few lines above. amd_iommu_domain_clr_pt_root() is zero'ing memory we are about to free. It used to protect against a double free of root, but that is gone now. Remove amd_iommu_domain_set_pgtable(), amd_iommu_domain_set_pt_root(), amd_iommu_domain_clr_pt_root() as they are all pointless. Reviewed-by: Vasant Hegde <[email protected]> Signed-off-by: Jason Gunthorpe <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
2024-09-04iommu/amd: Remove amd_iommu_domain_update() from page table freeingJason Gunthorpe2-3/+2
It is a serious bug if the domain is still mapped to any DTEs when it is freed as we immediately start freeing page table memory, so any remaining HW touch will UAF. If it is not mapped then dev_list is empty and amd_iommu_domain_update() does nothing. Remove it and add a WARN_ON() to catch this class of bug. Reviewed-by: Vasant Hegde <[email protected]> Signed-off-by: Jason Gunthorpe <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
2024-09-04iommu/amd: Set the pgsize_bitmap correctlyJason Gunthorpe1-24/+4
When using io_pgtable the correct pgsize_bitmap is stored in the cfg, both v1_alloc_pgtable() and v2_alloc_pgtable() set it correctly. This fixes a bug where the v2 pgtable had the wrong pgsize as protection_domain_init_v2() would set it and then do_iommu_domain_alloc() immediately resets it. Remove the confusing ops.pgsize_bitmap since that is not used if the driver sets domain.pgsize_bitmap. Fixes: 134288158a41 ("iommu/amd: Add domain_alloc_user based domain allocation") Reviewed-by: Vasant Hegde <[email protected]> Signed-off-by: Jason Gunthorpe <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
2024-09-04iommu/amd: Allocate the page table root using GFP_KERNELJason Gunthorpe1-1/+1
Domain allocation is always done under a sleepable context, the v1 path and other drivers use GFP_KERNEL already. Fix the v2 path to also use GFP_KERNEL. Fixes: 0d571dcbe7c6 ("iommu/amd: Allocate page table using numa locality info") Reviewed-by: Vasant Hegde <[email protected]> Signed-off-by: Jason Gunthorpe <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
2024-09-04iommu/amd: Move allocation of the top table into v1_alloc_pgtableJason Gunthorpe2-21/+8
All the page table memory should be allocated/free within the io_pgtable struct. The v2 path is already doing this, make it consistent. It is hard to see but the free of the root in protection_domain_free() is a NOP on the success path because v1_free_pgtable() does amd_iommu_domain_clr_pt_root(). The root memory is already freed because free_sub_pt() put it on the freelist. The free path in protection_domain_free() is only used during error unwind of protection_domain_alloc(). Reviewed-by: Vasant Hegde <[email protected]> Signed-off-by: Jason Gunthorpe <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
2024-09-04arm64: dts: imx: rename gpio hog as <gpio name>-hogFrank Li9-13/+13
Rename admin_led_lower to admin-led-lower-hog. Rename gpio rs485_en as rs485-en-hog. Rename gpio uart4_rs485_en to uart4-rs485-en-hog. Fix below warning: arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dtb: gpio@76: 'admin_led_lower' does not match any of the regexes: '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtb: gpio@30230000: 'rs485_en' does not match any of the regexes: '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtb: gpio@30220000: 'uart4_rs485_en' does not match any of the regexes: '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$', 'pinctrl-[0-9]+' Reviewed-by: Alexander Stein <[email protected]> Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: imx8mp-var-som-symphony: Add Variscite Symphony board and ↵Tarang Raval3-0/+371
VAR-SOM-MX8MP SoM Adds the DTSI file for the Variscite VAR-SOM-MX8MP System on Module which is delivered with the Variscite Symphony Evaluation Kit. Initial support includes: - Serial console - eMMC - SD card Signed-off-by: Tarang Raval <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: imx8mm-var-som: drop unused top-level compatibleKrzysztof Kozlowski1-1/+0
The Variscite VAR-SOM-MX8MM System-on-Module cannot be used alone without motherboard, so drop the top-level compatible field to avoid any false impression that such usage is possible. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: ls1088ardb: add new RTC PCF2131 supportJoy Zou1-0/+7
Add RTC PCF2131 node for new ls1088ardb board.. Signed-off-by: Joy Zou <[email protected]> Reviewed-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: colibri-imx8x: Cleanup commentsJoão Paulo Gonçalves1-4/+0
Remove unnecessary comments. The Colibri-iMX8X doesn't support FlexCAN, and the GPU is already enabled in the SOC dtsi. Signed-off-by: João Paulo Gonçalves <[email protected]> Signed-off-by: Francesco Dolcini <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: colibri-imx8x: Add 50mhz clock for ethPhilippe Schenker1-0/+15
Change enet0_lpcg to get the clock value needed in Colibri-iMX8X for 100mbps ethernet. Signed-off-by: Philippe Schenker <[email protected]> Signed-off-by: Francesco Dolcini <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: colibri-imx8x: Add adma_pwmJoão Paulo Gonçalves4-0/+21
Add adma_pwm node for Colibri-iMX8X carrier boards. Signed-off-by: João Paulo Gonçalves <[email protected]> Signed-off-by: Francesco Dolcini <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: colibri-imx8x: Add vpu supportJoão Paulo Gonçalves1-1/+27
Enable VPU on Colibri-iMX8X. Signed-off-by: João Paulo Gonçalves <[email protected]> Signed-off-by: Francesco Dolcini <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: colibri-imx8x: Add USB3803 HUBFrancesco Dolcini1-0/+20
Add USB3803 HUB, this is required for Bluetooth and USB functionalities. Signed-off-by: Francesco Dolcini <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: colibri-imx8x: Add PMIC thermal zoneFrancesco Dolcini2-2/+43
Add PMIC thermal zones. Signed-off-by: Francesco Dolcini <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: colibri-imx8x: Add sound cardJoão Paulo Gonçalves1-1/+46
Add audio support for Colibri-iMX8X sound card. Signed-off-by: João Paulo Gonçalves <[email protected]> Signed-off-by: Francesco Dolcini <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: colibri-imx8x: Add fxl6408 gpio expanderFrancesco Dolcini1-0/+15
Add fxl6408 gpio expander, this is required for Wi-Fi, Bluetooth and USB functionalities. Signed-off-by: Francesco Dolcini <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: colibri-imx8x: Add analog inputsJoão Paulo Gonçalves4-1/+28
Add adc nodes for analog inputs support for all Colibri-iMX8X carrier boards. Signed-off-by: João Paulo Gonçalves <[email protected]> Signed-off-by: Francesco Dolcini <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: colibri-imx8x: Add usb supportEmanuele Ghidoli4-4/+111
Add USB HOST and OTG support to Colibri-iMX8X carrier boards. Signed-off-by: Emanuele Ghidoli <[email protected]> Signed-off-by: Francesco Dolcini <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: imx8qm-mek: add usb 3.0 and related type C nodesFrank Li1-0/+87
Enable usb3.0 and related usb type C nodes. Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: imx8qm-mek: add i2c in mipi[0,1] subsystemFrank Li1-0/+30
Add i2c node in mipi[0,1] subystem for imx8qm-mek. Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: imx8qm-mek: add pwm and i2c in lvds subsystemFrank Li1-0/+68
Add pwm[0,1] and i2c[0,1] in lvds subsystem. Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: imx8qm-mek: add cm4 remote-proc and related memory regionFrank Li1-0/+93
Add two cm4 remote-proc and related memory regions. Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: imx8qm: add mipi subsystemFrank Li2-0/+36
Include common imx8-ss-mipi0.dtsi and imx8-ss-mipi1.dtsi. Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: imx8: add basic mipi subsystemFrank Li2-0/+267
Add basic mipi subsystem for imx8qm and imx8qxp. Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: imx8qm: add lvds subsystemFrank Li2-0/+86
Add irqsteer, pwm and i2c in lvds subsystem. Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: imx8: add basic lvds0 and lvds1 subsystemFrank Li2-0/+177
Add basic lvds0 and lvds1 subsystem for imx8qm an imx8qxp. Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: imx95: Add NETCMIX block control supportWei Fang1-0/+12
Add NETCMIX block control support. Signed-off-by: Wei Fang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: freescale: rename gw7905 to gw75xxTim Harvey5-8/+8
The GW7905 was renamed to GW7500 before production release. While we typically do not change compatibles, the GW7905 was never released before its product name was changed to a GW7500. The use the the 'xx' wildcard is to denote the fact that this device-tree can support range of board models from GW7500 to GW7599 as has been done historically with the Gateworks baseboards to support various build customizatoins based on the same PCB. Signed-off-by: Tim Harvey <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-09-04arm64: dts: imx93-11x11-evk: Add PWM backlight for "LVDS" connectorLiu Ying1-0/+30
J702 on i.MX93 11x11 EVK base board is a 40-pin connector labelled "LVDS". This connector supports PWM backlight with default 12V power supply and ADP5585 PWM controller. Add support for the backlight. Signed-off-by: Liu Ying <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
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